© 2019 IJSRST | Volume 6 | Issue 3 | Print ISSN: 2395-6011 | Online ISSN: 2395-602X

Themed Section: Science and Technology

Design Implementation of Successive Approximation Register A/D

Converter
Dr. Priyesh P. Gandhi
Principal, Sigma Institute of Engineering, Vadodara, Gujarat, India
ABSTRACT

This paper presents design implementation of Successive Approximation Register ADC. The ADC is the main
building block in modem signal processing and communication systems. Main purpose of the ADC is to convert
analog input into an equivalent digital output. There are many ADCs depending on the application like Sigma
Delta ADC, Pipelined ADC, SAR ADC. The Successive Approximation Register (SAR) ADC is the most widely
used converter in industrial control applications. It has good ratio of speed/power and has compact size that
make this converter into an inexpensive device. A low power 8-bit 200MS/s Successive Approximation Register
Analog to Digital Converter is designed and implemented in 180nm TSMC CMOS VLSI process. To reduce the
complexity of design TG based D Flip-flop and charge scaling DAC are used. To increase the conversion rate
and reduce the overall power dissipation of ADC Dynamic Latch Comparator is used.
Keywords : Analog to Digital Converters (ADCs), Successive Approximation (SAR), Flash ADC, Propagation
delay, Offset Voltage, Power Dissipation Spurious Free Dynamic Range (SFDR).

I. INTRODUCTION II. METHODS AND MATERIAL

High-performance applications like as broadband

communication systems require high-performance
analog-to-digital converters (ADCs). Due to advantages
given by the digital systems, they are mostly used in
many fields such as instrumentation, control,
communication and computers. In many such
applications they are not available in digital form. Most Figure 1. Signal Characteristics caused by A/D and D/A
of the physical quantities such as temperature, pressure, Conversion
displacement, vibrations etc. are available in analog
form. These quantities are represented accurately in ADC converts analog signals into discrete time or
analog form, but it is difficult to process, store or digital signals. DAC performs the reverse operation.
transmit the analog signal because error gets Figure 1
introduced easily, due to noise. Hence to reduce these
errors it is always better to express these physical illustrates these two operations. The original analog
quantities in the digital form. The digital signal is filtered by an anti-aliasing filter to remove any
representation of signal makes storage possible, high-frequency harmonics that may cause an effect
processing simpler and transmission easier. Hence A to known as aliasing. The signal is sampled and held and
D conversion is necessary. then converted into a digital signal. Next the DAC

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converts the digital signal back into an analog signal. Table 1. Comparison of ADC Architectures
Note that the output of the DAC is not as "smooth" as
the original signal. A low-pass filter returns the analog Architecture Latenc Speed Accurac
signal back to its original form after eliminating the y y
higher order harmonics caused by the conversion. This Flash No High Low
example illustrates the main differences between Folding/interpolati No Medium Low-
analog and digital signals. Whereas the analog signal is ng -High Medium
continuous and infinite valued, the digital signal in is Delta-Sigma Yes Low High
discrete with respect to time and quantized. The term Pipeline Yes Medium Medium
continuous-time signal refers to a signal whose -High
response with respect to time is uninterrupted. Simply SAR Yes Low Medium
stated, the signal has a continuous value for the entire -High
segment of time for which the signal exists. By
referring to the analog signal as infinite valued, we The steep rise in the demand of compact devices has
mean that the signal can possess any value between the revolute the world. To reconstruct the exact signals in
parameters of the system. The digital signal, on the high quality better converters are needed. Apart from
other hand, is discrete with respect to time. This means the problem of technology scaling and reduced supply
that the signal is defined for only certain or discrete voltages, another important aspect of use of ADCs are
periods of time. A signal that is quantized can only converting analog signals in the digital to store them
have certain values for each discrete period [14]. for the future use. In different types of ADCs available
like flash ADC, folding and interpolating ADC, two-
There are many ADC architectures are available like step ADC, pipeline ADC, successive-approximation-
flash ADC, sigma delta ADC, folding and interpolating register (SAR) ADC, delta-sigma ADC, integrating
ADC, two-step ADC, pipelined ADC, SARADC etc. ADC etc; SAR ADC optimize the design which is the
Comparison of various ADC architectures is shown in reason to choose SAR ADC. The main advantage of
Table 1 and its application based on resolution is also SAR ADC is good ratio of speed to power. The SAR
shown in Figure 2. ADC has compact design compare to flash ADC, which
makes SAR ADC inexpensive. The Successive
Among various ADC architectures, the SAR ADC has Approximation (SAR) architecture is very suitable for
the attractive feature of maintaining high accuracy at data acquisition; it has resolutions ranging from 8 bits
medium conversion rate. For this reason, it is used to 18 bits and sampling rates ranging from 50 KHz to
extensively in acquisition systems and high 50 MHz.
performance digital communication systems where
both precision and smaller area is critical. Flash or parallel converters have the highest speed of
any type of ADC. As seen in Figure 2, they utilize one
Table 1 shows the comparisons among various ADC comparator per quantization level ( -1) and resistors.
Architectures. The reference voltage is divided into values, each of
which is fed into a comparator. The input voltage is
compared with each reference value and results in a
thermometer code at the output of the comparators. A
thermometer code will exhibit all zeros for each
resistor level if the value of is less than the value on

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the resistor string, and ones if is greater than or equal

to voltage on the resistor string. A simple -1: N digital
thermometer decoder circuit converts the compared
data into an N-bit digital word. The advantage of this
converter is the speed with which one conversion can
take place. Each clock pulse generates an output digital
word. The advantage of having high speed, however, is
counterbalanced by the doubling of area with each bit
of increased resolution. For example, an 8-bit converter
requires 255 comparators, but a 9-bit ADC requires 511!
Figure 3. Block Diagram of Two Step Flash ADC
The flash converters have traditionally been limited to
The converter is separated into two complete Flash
8-bit resolution with conversion speeds of 10 - 40 Ms/s
ADCs with feed-forward circuitry. The first converter
using CMOS technology. The disadvantages of the
generates a rough estimate of the value of the input,
Flash ADC are the area and power requirements of the
and the second converter performs a fine conversion.
-1 comparators. The speed is limited by the switching
The advantages of this architecture are that the
of the comparators and the digital logic [14].
number of comparators is greatly reduced from that of
the Flash converter. For example, an 8-bit Flash
converter requires 255 comparators, while the two-step
Flash requires only 30. The tradeoff is that the
conversion process takes two steps instead of one, with
the speed limited by the bandwidth and settling time
required by the residue amplifier and the summer.
The conversion process is as follows:

1. After the input is sampled, the most significant bits

(MSBs) are converted by the first Flash ADC.
2. The result is then converted back to an analog
Figure 2. Block Diagram of Flash ADC voltage with the DAC and subtracted with the original
input.
Another type of Flash converter is called the two-step 3. The result of the subtraction, known as the residue,
Flash converter or a parallel, feed-forward ADC. The is then multiplied by and input into the second ADC.
basic block diagram of a two-step converter is shown in The multiplication not only allows the two ADCs to be
Figure3 [14]. identical, but also increases the quantum level of the
signal input into the second ADC.
4. The second ADC produces the least significant bits
through a Flash conversion.

This type of ADC is an improvement of flash ADC. The

folder basically folds the conventional linear I/O
response to be sandwiched in between a smaller
voltage range, so that they require a lesser number of
comparators. When the number of comparators is

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reduced, it automatically reduces the circuit's power in the DAC are decided. In order to achieve N-bit
demand. A typical block diagram of a folding ADC is resolutions, a successive approximation ADC requires
shown in Figure 4. The analog preprocessor, in front of N clock cycles. Because the performance is limited by
the fine quantizer, consists of folding amplifiers that DAC linearity, the calibration of the DAC is needed to
generate the folded signals. The folded signal is like the achieve high resolution.
residue signal in a sub ranging ADC, except for the fact
that the residue signal is not generated from the output
results of the coarse quantizer. A high conversion rate
is achieved because the coarse and fine quantizers are
in parallel. The open-loop design of the folding
amplifiers also speeds up the converter. Ideally, an
analog preprocessor should generate a saw tooth
waveform, but this is difficult to implement. Instead, a
triangle waveform is used in actual implementation,
but sharp corners remain difficult to realize. The actual
waveform is more sinusoidal and causes nonlinearity Figure 5. Architecture of SAR ADC.
errors in the ADC. This type of architecture would suit
The SAR ADC uses a binary search mechanism to
a medium resolution of 4-8-bit for the sampling
convert the analog signal to the digital signal. It has
frequency ranges above 100 MHz [14].
several advantages. It uses fewer analog components in
its design making its design compact. It also has a very
low latency compared to other circuits. Figure 5 shows
the block diagram of a SAR ADC [14].

2. Proposed Successive Approximation Register (SAR)

ADC
2.1 SAR Logic

Figure 4. Block Diagram of Folding ADC The successive approximation register (SAR) is based
on ring counter and shift register. In Figure 6, numbers
1. Existing Architectures of Successive of D Flip-flop (DFF) with set and reset are the major
Approximation Register (SAR) ADC part of SAR.

It consists of a comparator, a DAC and a successive

approximation register (SAR). The successive
approximation ADC uses a binary search algorithm to
find the closest digital code for an input signal. When
an input signal is applied to the converter, the
comparator simply determines whether the input
signal is larger or smaller than the DAC output and
produces one digital bit at a time starting from the
MSB. The SAR stores the produced digital bit and uses
the information to change the DAC output for the next
Figure 6. SAR Block Diagram
comparison. This operation is repeated until all the bits

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SAR logic consists of a ring counter and a shift register.

At least 2N-1 flip flops are employed in this kind of The most basic DAC is seen in Figure 7(a) Comprised of
SAR. SAR control logic determines the value of bits a simple resistor string of 2N identical resistors and
sequentially based on the result of the comparator. switches, the analog output is simply the voltage
Each conversion takes 9 clock cycles. In the first clock division of the resistors at the selected tap. Note that a
cycle, SAR is in the reset mode and all the outputs are N:2N decoder will be required to provide the 2N
zero. In the next 8 clock cycles, data is converted, and signals controlling the switches. This architecture
each bit is determined sequentially. The last cycle is for typically results in good accuracy, provided that no
storing the results of the complete conversion. In each output current is required and that the values of the
cycle of clock, one of the outputs in the ring counter resistors are within the specified error tolerance of the
sets a Flip Flop in the code register. The output of Flip converter. One big advantage of a resistor string is that
Flop is used as the clock signal for the previous Flip the output will always be guaranteed to be monotonic.
Flop. At rising edge of the clock, this Flip Flop loads
the result from the comparator.

2.2 DAC Logic

The digital to analog converter (DAC) converts the
digital word at the output of the SAR logic to an analog
value. Then in the comparator, this value is compared
to the input signal. A wide variety of DAC
architectures exist, ranging from very simple to
complex. Each, of course, has its own merits. Some use
Figure 8. An R-2R Digital-to-Analog converter
voltage division, whereas others employ current
steering and even charge scaling to map the digital Another DAC architecture that incorporates fewer
value into an analog quantity. In the following three resistors is called the R-2R ladder network [14]. This
different architectures of capacitive DAC are configuration consists of a network of resistors
presented. Resister string DAC, R-2R Ladder DAC, alternating in value of Rand 2R. Figure 8. illustrates an
Current string DAC, Cyclic DAC, Pipeline DAC, N-bit R-2R ladder. Starting at the right end of the
Charge Scaling DAC. network, notice that the resistance looking to the right
of any node to ground is 2R. The digital input
determines whether each resistor is switched to ground
(non inverting input) or to the inverting input of the
Op-Amp. Each node voltage is related to VREF, by a
binary-weighted relationship caused by the voltage
division of the ladder network. The total current
flowing from VREF is constant, since the potential at the
bottom of each switched resistor is always zero volts
(either ground or virtual ground). Therefore, the node
voltages will remain constant for any value of the
digital input.

Figure 7. (a) A Simple Resistor String DAC

(b) use of a Binary Switch Array

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has two reference voltages as shown in Fig.10. A

positive reference voltage of +VREF and a negative
reference voltage of –VREF or ground. It must select
Volt or 0 Volt depending on the output of each bit of D
Flip-flop which acts as a selection line. Mux is
implemented using two TGs.

Figure 9. A Generic Current Steering DAC

Figure 9 illustrates a generic current steering DAC.

This configuration requires a set of current sources,
each having a unit value of current, I. Since there are
no current sources generating iout when all the digital
inputs are zero, the MSB, DZN_Z, is offset by two bits
instead of one. For example, for a 3-bit converter, Figure 10. 1-Bit CMOS Switch
seven current sources will be needed, labeled from Do
III. Simulation Result
to D6. The binary signal controls whether the current
sources are connected to either iout or some other
2.4 Simulation Results of SAR ADC
summing node. The output current, iOUT> has the range
of
0 ≤ iout ≤ (2N-1) -----(1)
and can be any integer multiple of I in between. An
interesting issue to note is the format of the digital
code required to drive the switches. Since there are 2N-
1 current source, the digital input will be in the form of
a thermometer code. This code will be all 1's from the
LSB up to the value of the kth bit, Dk , and all O's above
it. The point at which the input code changes from all Figure 11. Transient Simulation of Sample and Hold
l's to all D's "floats" up or down and resembles the
(Fm= 10MHz, Fs = 100MHz)
action of a thermometer, hence the name. Typically, a
thermometer encoder is used to convert binary input
data into a thermometer code.

2.3 CMOS Switch

This CMOS switch converts the 1-bit digital to an

analog signal. Fig.10 shows the circuit level diagram of
1-bit DAC. It is made using 2×1 multiplexer. As the Figure 12. Transient Simulation of Comparator
number of bits is only 1-Bit, the corresponding analog
output will also have two levels and like the digital
output. The present 1-Bit digital-to-analog converter

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Figure 12. Propagation Delay of Comparator

Figure 16. Transient Simulation of CMOS Switch

Figure 13. Offset of Comparator Figure 17. Transient Simulation of OPAMP as Buffer

Figure 14. Transient response of D Flip-Flop

Figure 18. Frequency Response of Two Stage Op-Amp

Figure 15. Output of 8 bit SAR Logic

Figure 19. Simulation of 8- Bit Charge Scaling DAC

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2.5 Simulation Results of 8- Bit SAR ADC

Figure 23. Offset of Dynamic Latch Comparator

2.6 Simulation Results of 8 - Bit SAR ADC using

Dynamic Latch Comparator

Figure 20. Simulation Result of 8- Bit SAR ADC

Figure 24. Simulation Results of 8- Bit SAR ADC using

Dynamic Latch Comparator
Figure 21. Transient Simulation of Dynamic Latch
Comparator Table 2 illustrates the comparison of SAR ADC based
on different comparator design. Table 3 illustrates the
comparative design analysis for SAR ADC Designs for
the circuit designers to fully explore the trade-offs in
SAR ADCs.

Figure 22. Propagation Delay of Dynamic Latch

Comparator

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Table 2. Comparison of SAR ADC based on different V. REFERENCES

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Table 3. Comparative Design Analysis of SAR ADC

Parameter /Value [2] [13] [7] This Work

Technology 180nm 180nm 180nm 180nm
Supply voltage 1.8V 1.2V 0.5V 1.8V
Samples 80kS/s 50MS/s 4kS/s 200MS/s
Resolution 8 bit 10 bit 8bit 8 bit
Power Consumption 164.97mW 980µW 100mW 12.3nW

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