VLSI Lecture series
CMOS Fabrication
Process
nMOS and pMOS structure on P Type Substrate
Create n well or p well For nMOS and pMOS, special region must be created in which
region and channel semiconductor type is opposite to the substrate type, these region
stop region
are called wells or tubs.
p well is created in n type substrate and n well is created in p type
Grow field oxide (Thick substrate.
Oxide) and gate oxide
(Thin Oxide) nMOS transistor are created in p type substrate or p well and pMOS
transistor are created in n type substrate or n well.
Deposit and pattern
That well should be of defined boundary to have fixed channel stop
polysilicon layer region.
Thick Oxide is grown in active region of nMOS and pMOS.
The thin gate oxide is grown on the surface through thermal
Implant source, drain
region and substrate oxidation.
contacts As per circuit make a pattern of polysilicon layer.
After that create n+ and p+ regions for source, drain and substrate.
Create contact
windows, deposit and Final metallization for metal interconnects.
pattern metal layer
nMOS and pMOS on P Type Substrate
VLSI Lecture series
Twin Tube Fabrication
Process
Basics of Twin tube fabrication process
In our previous video, I have explained nMOS and pMOS structure on P Type Substrate.
In that, there can be issues regarding, mutual coupling in between nMOS and pMOS.
There can be major issues regarding, Latch up for CMOS fabrication.
To avoid those issues, we should fabrication nMOS and pMOS by twin tube fabrication
process.
Let us use n Type substrate.
The resistivity of substrate should be higher.
n – Type Substrate
Higher the resistivity lesser the current
through substrate.
Then we should grow n+ layer epitaxially.
Epitaxial Layer That is having lesser resistance compared to
substrate.
n – Type Substrate
SiO2 Layer
After that, substrate is subjected to oxidation
and we grow SiO2 layer.
Epitaxial Layer
n – Type Substrate
SiO2 Layer
SiO2 layer is etched using masking.
Two windows are formed, One for n-well and
Epitaxial Layer
another for p-well.
n – Type Substrate
P+ diffusion
Photoresist mask
SiO2 Layer
P well 1st window is covered by photoresist mask.
Then p type impurities diffused to form p
Epitaxial Layer well.
n – Type Substrate
N+ diffusion
Photoresist mask
SiO2 Layer
2nd window is covered by photoresist mask.
n well p well
Then n type impurities diffused to form n
well.
Epitaxial Layer
n – Type Substrate
SiO2 Layer
Grow Thin SiO2 layer by thermal oxidation
n well p well for Gate terminal
Grow Polysilicon layer for photolithography
Epitaxial Layer and pattern making.
n – Type Substrate
SiO2 Layer
n well p well
Each SiO2 and Polysilicon to implant Drain
and Source.
Epitaxial Layer
n – Type Substrate
p+ diffusion
Photoresist mask
SiO2 Layer p well covered with photoresist mask and p+
p+ p+
n well p well diffusion is done to form source and drain
region
Epitaxial Layer
n – Type Substrate
n+ diffusion
Photoresist mask
SiO2 Layer n well covered with photoresist mask and n+
p+ p+ n+ n+
n well p well diffusion is done to form source and drain
region
Epitaxial Layer
n – Type Substrate
S G D S G D
SiO2 Layer Metal diffusion is done for contact
p+ p+ n+ n+
n well p well formation.
Metal etching is done.
Epitaxial Layer Contact formations for source S, Drain D and
Gate G is done
n – Type Substrate
VLSI Lecture series
Photolithography
Photolithography
It is a process to produce circuit/pattern on the Si Layer.
UV light exposure is used.
Two important steps are there in photolithography
1. Photographic Masking : It contains information which we want to project on
Si wafer.
2. Photographic Etching : It contains pattern information which we wants to
remove from layer.
There are two types of photographic etching
Wet Etching (By Chemical)
Dry Etching (By UV light exposure)
VLSI Lecture series
Ion Implantation
and it’s Advantage
over Diffusion
Ion Implantation
It is alternative to diffusion process in IC fabrication.
Diffusion Process is done at high temperature, but Ion implantation
is done at low temperature.
In Ion Implantation, high energy dopant ions are accelerated, so that
ions can easily penetrate the Si wafer.
The depth of penetration can be increased by increasing accelerating
voltage.
