Syllabus

CMOS Fabrication Process

 Create a pattern.
 Oxidize small layer, about 1µm
thick.
 Place photoresist on top of SiO2
 Place mask(pattern) above
photoresist and expose it to UV
light.
CMOS Fabrication Process
 Etch away SiO2 using HF acid
or plasma.
 Remove remaining photoresist
with acids.
CMOS Fabrication Process
A thin layer of oxide is deposited.
A thin layer of polysilicon is
deposited using Chemical Vapor
Deposition (CVD) .
CMOS Fabrication Process
Remove oxide layer using acid.
Dope open area using Ion
implantation or diffusion.
CMOS Fabrication Process
Problems with Current CMOS
Fabrication
Optical lithography is limited by the light frequency.
Material limitations
Yield limitations
Space limitations
Future Changes in CMOS Fabrication
Material changes like using high-k materials.
Design changes
 SOI(Silicon On Insulator)
 Double Gate (Finfet)
 Twin-Tub Process
What is CMOS?

 Complementary metal–oxide–semiconductor (CMOS)

 Has many different uses:
 Integrated Circuits
 Data converters
 Integrated transceivers
 Image sensors
 Logic circuits
What is CMOS?
Complementary MOS fabrication
 CMOS Technology depends on using both N-Type and P-Type devices on
the same chip.
 The two main technologies to do this task are:
 P-Well
 The substrate is N-Type. The N-Channel device is built into a P-Type
well within the parent N-Type substrate. The P-channel device is
built directly on the substrate.
 N-Well
 The substrate is P-Type. The N-channel device is built directly on the
substrate, while the P-channel device is built into a N-type well
within the parent P-Type substrate.
Complementary MOS fabrication
 Two more advanced technologies to do this task are:
Becoming more popular for sub-micron geometries where device
performance and density must be pushed beyond the limits of the
conventional p & n-well CMOS processes.
 Twin Tub
 Both an N-Well and a P-Well are manufactured on a lightly doped N-
type substrate.
 Silicon-on-Insulator (SOI) CMOS Process
 SOI allows the creation of independent, completely isolated nMOS
and pMOS transistors virtually side-by-side on an insulating
substrate.
 P-well on N-substrate
Steps :
 N-type substrate
 Oxidation, and mask (MASK 1) to create P-well (4-5m deep)
 P-well doping

P-well acts as substrate for nMOS devices.

The two areas are electrically isolated using thick field oxide (and often
isolation implants [not shown here])

N-type substrate
Poly silicon Gate Formation
Steps :
 Remove p-well definition oxide
 Grow thick field oxide
 Pattern (MASK 2) to expose nMOS and pMOS active regions
 Grow thin layer of SiO2 (~0.1m) gate oxide, over the entire chip surface
 Deposit polysilicon on top of gate oxide to form gate structure
 Pattern poly on gate oxide (MASK 3)

Thin gate Gate (patterned

oxide (SiO2) polysilicon on thin
oxide)

Thick
field nMOS active
oxide P
region
pMOS active N-type substrate
region
nMOS P+ Source/Drain diffusion – self-aligned to Poly
gate
Implant P+ nMOS S/D regions (MASK 4)

P+ implant/diffusion

P+ mask

Thick
field
oxide P

N-type substrate
pMOS N+ Source/Drain difusion – self-aligned to Poly
gate

Implant N+ pMOS S/D regions (MASK 5 – often the inverse of MASK 4)

N+ implant/diffusion

N+ mask

P+ N+ P

N-type substrate
 pMOS N+ Source/Drain diffusion, contact holes
& métallisation
Oxide and pattern for contact holes (MASK 6)
Deposit metal and pattern (MASK 7)
Passivation oxide and pattern bonding pads (MASK 8)

P-well acts as substrate for nMOS devices.

Two separate substrates : requires two separate substrate connections
Definition of substrate connection areas can be included in MASK 4/MASK5
Vin

Vdd Vout Vss

N+ for N- P+ (for P-
substrate substrate
contact) contact)
P
P+ P channel N+
Device N channel
Device
N-type substrate
 CMOS N-well process

An N-well process is also widely used

Vin
P+ for P-substrate
contact) Vdd Vout Vss N+ (for N-
substrate
contact)

N-well
N + N channel P +
Device P channel
Device
P-type substrate
Composite layout and cross-section view of n-well
CMOS device (excludes passivation and patterning of wire-
bonding pads)
Twin-Tub (Twin-Well) CMOS Process
Twin-Tub (Twin-Well) CMOS Process
This technology provides the basis for separate optimization of the nMOS and
pMOS transistors, thus making it possible for threshold voltage, body effect
and
the channel transconductance of both types of transistors to be tuned
independently.

Generally, the starting material is a n+ or p+ substrate, with a lightly doped

epitaxial layer on top.

Steps:
 Tub formation
 Thin-oxide construction
 Source and drain implantations
 Contact cut definition
 Mettalization
Twin-Tub (Twin-Well) CMOS Process
This epitaxial layer provides the actual substrate on which the n-well and the

p- well are formed.

The aim of epitaxy is to grow high-purity silicon layers of controlled

thickness with accurately determined dopant concentrations distributed
homogeneously throughout the layer.

In the conventional p & n-well CMOS process, the doping density of the well
region is typically about one order of magnitude higher than the substrate,
which, among other effects, results in unbalanced drain parasitics.

The twin-tub process avoids this problem.

Since two independent doping steps are performed for the creation of the
well
regions, the dopant concentrations can be carefully optimized to produce the
desired device characteristics.
Silicon-on-Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, technologists have

sought to use an insulating substrate to improve process characteristics
such as speed and latch-up susceptibility.

The SOI CMOS technology allows the creation of independent,

completely isolated nMOS and pMOS transistors virtually side-by-side
on an insulating substrate.
Silicon-on-Insulator (SOI) CMOS Process
The main advantages of this technology are the higher integration
density (because of the absence of well regions), complete avoidance
of the latch-up problem, and lower parasitic capacitances compared
to the conventional p & n-well or twin-tub CMOS processes.

A cross-section of nMOS and pMOS devices using SOI process is

shown
below.

The SOI CMOS process is considerably more costly than the standard p
& n-well CMOS process.

Yet the improvements of device performance and the absence of latch-

up
problems can justify its use, especially for deep-sub-micron devices.
 Silicon-on-Insulator (SOI) CMOS Process
A thin film of very lightly doped n-type Si is
grown over an insulator. Sapphire or Sio2 is a
commonly used insulator fig(a)

An anisotropic etch is used to etch away the Si

except where a diffusion area will be needed
fig(b,c)

The p-islands are formed next by masking the n-

islands with a photoresist . A p-type dopant,
Boron, for example – is implanted. The p-islands
will become the n-channel device fig (d)

The p-islands are then covered with a photoresist

and an n-type dopants – phosphorous, for example
– is implanted to form the n-islands. The n-islands
will become the p-channel device fid (e)

A thin gate oxide is grown over all of the Si

structures. This is normally done by thermal
oxidation
 Silicon-on-Insulator (SOI) CMOS Process
A polysilicon film is deposited over the oxide. Often the
polysilicon is doped with phosphorous to reduce its resistivity
fig (f)

The polysilicon is then patterened by photomasking and is

etched fig (g)

Next step is to form the n-doped source and drain of the n-

channel devices in the p-islands. The n-islands are covered with
a photoresist and an n-type dopant, normally phosphorous is
implanted. The dopant will be blocked at the n-islands by the
photoresist. After this step n-channel devices are complete fig
(h)

 The p-channel devices are formed by masking the p-islands

and implanting a p-type dopant such as Boron. The polysilicon
over the gate of the n-islands will block the dopant from the
gate, thus forming the p-channel devices fig (i)

A layer of phosphorous glass or other insulator such as Sio2

is then deposited over the entire structure
Silicon-on-Insulator (SOI) CMOS Process
The glass is etched at contact cut locations. The metallization layer is
formed next by evaporating aluminium over the entire surface and etching it
to leave only the desired metal wires. The aluminium will flow through the
contact cuts to make contact with the diffusion or polysilicon regions fig (j)
Advantages of SOI Technology
Due to the absence of wells, transistor structures denser than bulk silicon
are feasible. Also direct n-to-p connections may be made

Lower substrate capacitances provide the possibility for faster circuits

No field-inversion problems exist (insulating substrate)

No latchup because of the isolation of the n- and p- transistors by the

insulating substrate

Because there is no conducting substrate, there are no body-effect

problems

There is enhanced radiation tolerance

Stick diagrams
Stick diagrams
Sketch a stick diagram for the below expression
Y=(A+B+C).D