Lecture 2: CMOS and Manufacturing Process

VLSI
Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors

Today: How to build your own simple CMOS chip

CMOS transistors Building logic gates from transistors Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip

Class

Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si

Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
Si Si Si Si
-

Si Si Si

Si Si Si

Si B

+ -

Si Si Si

As Si

Si

p-n Junctions
A junction between p-type and ntype semiconductor forms a diode. Current flows only in one direction
p-type anode n-type cathode

MOS Structure

nMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor
Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Source Gate Drain Even though gate is no longer made of metal
Polysilicon SiO2

n+ p

n+ bulk Si

nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage:
P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2 0 n+ p n+ S bulk Si D

nMOS Operation Cont.

When the gate is at a high voltage:
Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D

pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain

p+ n

p+ bulk Si

Power Supply Voltage

GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes
High VDD would damage modern tiny transistors Lower VDD saves power

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

Photo-Lithographic Process
optical mask oxidation

photoresist removal (ashing)

photoresist coating stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry

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Circuit Under Design & Layout View

VDD M2

VDD

M4 Vin Vout Vout2

M1

M3

Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps
A GND Y VDD

p+

n+

n+ p substrate

p+ n well

p+

n+

substrate tap

well tap

Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

Detailed Mask Views

Six masks
n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

p substrate

Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light

Photoresist SiO2

p substrate

Lithography
Expose photoresist through n-well mask Strip off exposed photoresist

Photoresist SiO2

p substrate

Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

Photoresist SiO2

p substrate

Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

SiO2

p substrate

n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si

Ion Implantation
Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well

Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

n well p substrate

Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

Polysilicon Thin gate oxide n well p substrate

Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

n well p substrate

N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

n+ Diffusion

n well p substrate

N-diffusion cont.
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n+

n+ n well p substrate

n+

N-diffusion cont.
Strip off oxide to complete patterning step

n+

n+ n well p substrate

n+

P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

M e ta l

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Layout

Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules

Transistor Layout

Transistor

5 2 1

Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

CMOS Process Layers

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

Layers in 0.25 m CMOS process

Intra-Layer Design Rules

Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
Metal2 3

Different Potential 9 Polysilicon 2 Metal1 3

4

Well

Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

CMOS Inverter Layout

GND In VD D

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A

Design tools

Layout Editor

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Sticks Diagram
VDD In

3/1 Out

Dimensionless layout entities Only topology is important Final layout generated by compaction program

1/1
GND
Stick diagram of inverter