Code No.
: 22EEC12
CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (Autonomous)
B.E. (EEE) IV Sem (Main) Examination May – June 2024
Digital Electronics
Time: 3 Hours Max Marks: 60
Note: Answer ALL questions from Part-A at one place in the same order and Part–B
(Internal Choice)
Part - A
(5Q X 2M = 10 Marks)
M CO BT
1 (i) Convert (BAD)16 to Octal Equivalent. (2) 1 2
(ii) Divide 10101 with 101.
2 If X is 1 in the given logic function, then z=? (2) 2 2
[X + Z ∗ (Y + X)] ∗ [𝑋̅ + 𝑍(𝑋 + 𝑌)] = 1
3 Define Race Around Condition and how to avoid it. (2) 3 1
4 Define following terms as related to DAC: i) linearity ii) Resolution. (2) 4 1
5 List the major differences between PLA and PAL. (2) 5 1
Part - B
(5Q X 10M = 50 Marks)
M CO BT
6 (a) Explain the working of two inputs TTL NAND gates. (5) 1 2
(b) (i) Using 2’s complement, subtract 1111012 from 110102. (5) 1 2
(ii) Convert 534.6728 to Hexadecimal representation.
(iii) Find A16.2B16 + BC2.D116.
(OR)
7 (a) Find the Hamming code for binary bit 1 0 0 0. Consider even parity bits. (5) 1 2
(b) Design a 4-to-16 decoder using two 74x138 IC’s. (5) 1 2
8 (a) (i) Simplify the following Boolean expression (5) 2 2
F= ∑(3,5,7,10,11,12,13,14) + d(0,15) using K-map
(ii) Implement F = ∑(1, 4, 5, 7, 9) using 2X1 multiplexers.
(b) (i) Design a half-adder circuit and realize it using only NOR gates. (5) 2 2
(ii) Realize F(A, B, C, D) = Σ (1, 3, 4, 11, 12, 13, 14, 15) using a suitable
MUX.
(OR)
9 (a) (i) Design a magnitude comparator circuit for 2-bit binary numbers 𝐴 = (5) 2 2
𝐴1 𝐴0 ,𝐵 = 𝐵1 𝐵0 , the outputs are X,Y,Z where X is 1 if A>B ,Y is 1 if
A=B and Z is 1 if A<B
(ii) Design a logic circuit that will produce 1, only when input
represented by a 3-bit binary number is greater than 4 or less than 2.
(b) Design the BCD–to–seven–segment decoder using a minimum number (5) 2 2
of gates.
10 (a) Implement T & D Flip Flops using JK Flip Flops. (5) 3 2
(b) Design and draw the 3 bit synchronous up counter. (5) 3 2
Page 1 of 2
Code No.: 22EEC12
(OR)
11 (a) (i) The circuit shown below is a shift register initially loaded with 1010. (5) 3 2
Find the data present in the register after four clock pulses.
(ii) For the circuit shown in below, assume Q = 1 initially. Find the
output of the circuit for the next four clock pulses.
(b) What is state assignment? Explain with a suitable example? (5) 3 2
12 (a) An analog input of 1.675 V is applied to a 4- bit analog-to-digital (5) 4 3
converter using successive approximation algorithm. Find the digital
output. Mention the references in the order against which the
comparisons are performed to achieve the digital output.
(b) Draw the schematic block diagram of dual slope A/D converter and (5) 4 3
explain its operation. Derive expression for its output voltage.
(OR)
13 (a) Convert 0100 (digital) to analog output using weighted resistor DAC. (5) 4 3
Assume the analog output shall be in the range of 0-4 V and the analog
output for 0000 is 0.125 V.
(b) Draw the circuit of a ladder type DAC for 4-bits and derive the (5) 4 3
expression for output voltage.
14 (a) Construct the PROM using the conversion from BCD code to Excess-3 (5) 5 4
code.
(b) Obtain 16x8 memory using 16x4 memory ICs. (5) 5 4
(OR)
15 (a) Implement the following functions using PLA. (5) 5 4
A(x,y,z) = ∑m(1,2,4,6) B(x,y,z) = ∑m(0,1,6,7) c(x,y,z) = ∑m(2,6)
(b) Explain the DRAM cell for read and write operations with a neat (5) 5 4
diagram.
*****
Page 2 of 2
