EC1312 DIGITAL LOGIC CIRCUITS Part A 1. Convert 757.25 10 and 235610 to octal. 2. Convert 757.25 10 and 235610 to binary.

y. 3. Convert the following binary to decimal a) (1011011.1101)2 and (b) 1011102. 4. Convert (FACE)16 to base 8 number. 5. Find the decimal equivalent of (123)9. 6. Convert the following numbers with the indicated bases to decimal: (4310)5 and (198)12. 7. Convert the Hexadecimal number 68BE to binary and octal. 8. Determine the base of the number for the following operations to be correct 14/2 = 5 9. Perform the hexadecimal addition of i) 1A6 and 4D3 and ii) 1A8 and 67B. 10. Express -67 in twos complement form. 11. Using twos complement perform the subtraction 10011012 1101002. 12. Using twos complement perform the subtraction 1810 3310. 13. Obtain the 1s and 2s complements of the following binary numbers: (a) 01101011 (b) 00000000 14. Add the decimals 67 and 54 using BCD code. 15. Convert (1029)10 to Gray code. 16. Convert 5310 to excess 3 code and show that excess-3 code is self complementing or reflecting code. 17. What are the characters that can be encoded using the most common 7 bit alphanumeric code. 18. How is letter A coded in ASCII code? What bit must be complemented to change an ASCII letter from lower to upper case and vice versa? 19. Express 15 bit Hamming code in general. 20. Define positive and negative digital logic. 21. State two absorption properties of Boolean algebra. 22. State De-Morgans laws. 23. Show how bubbled AND gate works as NOR gate. 24. Why NAND and NOR gates are called as universal gates? 25. Simplify the Boolean function F = (A + (BC)) 26. Minimize the expression using Boolean theorems F= xy + xyz + xz + xyz. Draw the logic diagram for the minimized function. 27. If A and B are Boolean variables and if A= 1 and (A+B) = 0, find B. 28. Realize the function F (A, B) = AB + AB using NAND gates only. 29. How many inputs and gates are required for the expression W = ABD + ACD + EF 30. Name two canonical forms of Boolean algebra. 30. Express the function f(x,y,z) = x + yz as a sum of minterms. 31. For the given function write the Boolean expression in product of maxterms form f( a,b,c) = m (2,3,5,6,7). 32. Plot the expression in K-map F (w, x, y) = (0, 1, 3, 5, 6) + d (2, 4) 33. Show the Karnaugh map with the encircled groups for the Boolean function, F = C+ AD + ABD. 34. List out the differences between half adder and full adder. 35. Write down the truth table of a full adder.

36. Implement half adder circuit using logic gates. 37. Implement half subtractor circuit using logic gates. 1. Implement the function f = m (0, 1, 4, 5, 7) using 8 to 1 multiplexer. 2. Design a half subtractor using 2 to 4 decoder. 3. Write the excitation tables of JK and D flip-flops. 4. Draw the logic diagram of three bit ring counter. 5. What is a demultiplexer? 6. Write the characteristic equation of JK and D flip-flop. 7. Convert an SR flip-flop to D flip-flop. 8. Define glitch. 9. Draw a 1 to 2 demultiplexer and 2 to1 multiplexer. 10. List out the limitations of SR flip-flop. 11. Convert a D flip flop into a T flip flop. 12. If a serial in serial out shift register has N stages and if the clock frequency is f, what will be the time delay between input and output? 13. Distinguish between combinational and sequential circuits. 14. Describe the behaviour of SR flip-flop by means of a table. 15. How many flip-flops are required to build a counter of modulus 14 and modulus 8? 16. Differentiate between Moore and Mealy type sequential circuits. 17. Implement a NAND gate using 4:1 Multiplexer. 18. What are state diagrams and state table? 19. What are shift register counters? List two widely used shift register counters. 20. Explain in brief about state reduction. 21. Distinguish between multiplexer and demultiplexer. 22. Derive the characteristic equation of T flip-flop. 23. When a sequential machine is said to be trivial? 24. List out the differences between a flip-flop and a latch. 25. Why a serial counter is referred to as asynchronous. 26. Define fundamental-mode operation. 27. Why critical race is said to be harmful and how it is avoided in asynchronous sequential Circuits? 28. What is FPGA? 29. Define Noise margin. 30. What are cycles in asynchronous sequential circuits? 31. What are races? 32. Define Fan-in and Fan out? 33. Why CMOS is preferred to TTL? 34. Compare PLA and PAL 35. What are the basic parameters to be noted before selecting an IC?

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PART - B Using K-map simplify the expression Y (A, B, C, D) = m1+m3+m5+ m7+m8+m9+ m0+m2+m10+m12+m13.Indicate the prime implicants, essential and non-essential prime implicants. Realize the logic circuit using AND-OR-INVERT gates and also by using NAND gates. (16) Obtain the simplified function for the Boolean function

Y (A, B, C, D) =m1+m3+m5+m7+m8+m9+ m0+m2+m10+m12+m13 using Quine McClusky method. Obtain the NAND and NOR implementation of the simplified expression. (16) 3. i) Draw and explain the working of 4 bit adder subtractor circuit. (8) ii) Simplify using K-map to obtain a minimum POS expression (A + B + C + D) (A + B+ C + D) (A + B + C + D) ( A + B + C + D) ( A+ B + C + D) (A + B + C + D) (8) 4. i) Write short notes on i) alphanumeric codes and ii) Error detection and correction methods (6) ii) Design a 4 bit BCD to Excess- 3 code converter. (10) 5. i) Simplify F (A,B,C,D) = m ( 1,3,5,8,9,11,15) + d (2,13).If dont care conditions are not taken into care what will be the simplified Boolean function? Write your comments on it. Implement both circuits using logic gates. (12) ii) Add 26 and 39 using Excess-3 code. (4) 6. Simplify using five variable mapping F = m( 8,9,10,11,13,15,16,18,21,24,25,26,27,30,31) (16) 7. i ) State and prove De - Morgans theorems using two variables (6) ii) Design a 4 bit Binary to gray code converter. (10) 8. i) Realize the functions of NOT, AND ,OR and NAND gates only with NOR gates. (8) ii) Convert the decimal 65 to BCD, Excess-3 and Gray code (4) iii) Encode data bits 1001 into a seven bit even parity Hamming code. (4) 9. i) Design a two bit magnitude Comparator (8) ii) Simplify the following Boolean function in SOP and POS form using K-map F ( A,B,C,D) = m( 3,4,9,13,14,15) + d ( 2,5,10,12) (8) 10. Simplify the following function using K map and tabular methods. Compare the methods. F ( A,B,C,D) = m(4,5,6,7,8) + d (11,12,13,14,15).Implement the result using NAND gates. (16) 11. What are codes? Explain the different codes with examples. (16) 12. i) Design a Half subtractor using NAND- NAND logic (6) ii) Design a four bit gray to binary code converter. (10) 13. i) Explain the working of carry look ahead generator (10) ii) Prove the following Boolean identities i) x + xyz + yzx + wx + wx + xy = x + y ii) (X1 + X2) (X1 X3 + X3) (X2 + X1X3) = X1X2 (6) 14. i) The state of 12 cell register is 010110010111.What is its contents if it represents a) Three decimal digits in BCD b) Three decimal digits in Excess- 3 code. c) Three decimal digits in 2421 code d) Three decimal digits in 84-2-1 code. (8) ii) A majority gate is a digital circuit whose output is equal to 1 if majority of its inputs are 1s. The output is 0 otherwise. Using a truth table, find the Boolean function implemented by a 3-input majority gate. Simplify the function and implement it with logic gates. (8) 15. i) Construct a BCD to Excess -3 code converter using full adders (8) ii) Design an 8421 to gray code converter. (8) 16. Implement the following expression with 2 - input NAND NOT gates. Assume that only true values of the inputs are available. F = (AB + AB) (CD + CD).Also use a multiple level implementations to

reduce the number of gates. Hint Use a two level AND OR implementation plus NOT gates on the inputs as needed. Then convert to NAND NOT gates. (16) Simplify the following switching function F(A,B,C,D,E) = m(1,3,6,10,11,12,14,15,17,19,20,22,24,29,30) (16) 18. i) Design and implement a full adder circuit using logic gates and also by using half adders. (8) ii) Perform the following arithmetic using twos complement (+27) + (-61), (-27) + (+61) and (-27) + (-61). (6) iii) Generate the parity bits for 8421 BCD code in an odd parity system. (2) 17. 1. i. Design a logic circuit to simulate the function f ( A,B,C) = A(B + C) by using only NAND gates. (4) ii. Explain with truth table and gate level circuits diagram for a full adder. (12) 2. i. What is a decoder ? How is it different from encoder? (6) ii. Implement the following function with a Multiplexer f (a, b, c, d) = ( 0, 1, 3, 4, 8, 9, 15) (10) 3. Design a MOD 10 synchronous counter using JK flip-flops. Write the excitation table and state table. (16) 4. i. Compare Moore and Mealy circuits. (4) ii. Draw and explain the block diagram of Mealy circuit. (12) 5. Using SR flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000, (16) 6. Design a mod 5 synchronous counter using JK flip flops with separate logic circuitry for each J and K input. Construct a timing diagram and determine the duty cycle of the output of the most significant stage. (16) 7. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, D are equal to the present states of A, B, C respectively. The next state of A is equal to the EX-OR of present states of C and D. (16) 8. i.Implement full adder circuit using, a) Decoder b) Multiplexer (12) ii. How can you convert a decoder into a demultiplexer? (4) 9. i. Show that the characteristic equation of Q ( ++1) of JK flip flop is Q(++1) = JQ + KQ (4) ii. A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists of a full adder circuit connected to a D flip-flop, as shown below. Derive the state table and state diagram of the sequential circuit. (12)

10. i. Reduce the number of states in the following state table and tabulate the reduced state table. Present state a b c d e f g h Next State x=0 x=1 f b d c f e g a d c f b g h g a x=0 0 0 0 1 0 1 0 1 Output x=1 0 0 0 0 0 1 1 0

(8)

ii. Starting from state a, and the input sequence 01110010011, determine the output sequence for the given and reduced state stable. (8) 11. Design a synchronous decade counter using D flip flop. (16) 12. i. Explain the working of a master slave JK flip flop. (6) ii. For a four bit even parity bit generator, inputs come serially. The four bits of the input sequence are to be examined by the circuit and circuit produces a parity bit which is to be added in the original sequence. The circuit should get ready for receiving another four bits after producing a parity bit for the last sequence. Draw the state diagram and write down the state transition table. (10) 13. i. Using 8 to 1 multiplexer, realize the Boolean function T = f ( w, x, y, z) = m ( 0, 1, 2, 4, 5, 7, 8, 9, 12, 13) (8) ii. Realize the function given in ( i ) using Decoder and external gates. (8) 14. A sequential circuit has four flip-flops ABCD and an input x is describe the following state equations. A ( t + 1) = ( CD + CD) x + (CD + CD)x B ( t + 1) = A C ( t + 1) = B D ( t + 1) = C a. Obtain the sequence of states when x = 1 starting from ABCD = 0001 b. Obtain the sequence of states when x = 0 starting from ABCD = 0000 (16)

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15. Implement the function Y(A,B,C,D) = m ( 1, 3, 5, 7, 8, 9, 0, 2, 10, 12, 13) using 4:1 MUX. (16) 16. i. Implement the logic function Y(A,B,C) = m ( 1, 2, 7) using 74151A and 74153. (8) Implement a 3 to 8 line decoder. (8) 17. A sequential circuit with 2 D flip-flops A and B and input X and output Y is specified by the following next state and output equations. A( t + 1) = AX + BX B( t + 1) = AX Y = ( A + B ) X i. Draw the logic diagram of the circuit ii. Derive the state table iii.Derive the state diagram (16)

18. Design a Mod-14 up-down counter using T flip-flops. (16) 19. Develop the state diagram and primitive flow table for a logic system that has two inputs S and R and a single output Q. The device is to be an edge triggered SR flip-flop but without a clock. The device changes state on the rising edges of the two inputs.Static input values are not to have any effect in changing the Q output. (16) 20. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z. The output is to remain a 0 as long as X1 is a 0. The first change in X2 that occurs while X1 is a 1 will cause a Z to be a 1. Z is to remain a 1 until X1 returns to 0. Construct a state diagram and flow table. Determine the output equations. (16) 21. (i) Explain the operation of TTL NAND gate with a neat circuit diagram. (ii) Draw the circuit of CMOS NOR gate and explain its operation. Mention any two points about the advantages of CMOS over the other digital logic families. (8) (8)

22. (i) Using ROM, design a combinational circuit which accepts 3 bit number and generates an output binary number equivalent to the square of input number. (8) (ii) A combinational circuit is defined by the functions F1 (A, B, C) =m(3, 5, 6, 7), F2 (A, B, C) = m(0, 2, 4, 7). Implement the circuit using PLA. (8) 23. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are Y1=x1 +x1y2 ' +x2y1 Y2=x2 +x1y1' y2+x1y1 Z= x2+y1 (i) Draw the logic diagram of the circuit. (6) (ii) Derive the transition table and output map. (5) (ii) Obtain a flow table for the circuit. (5) 24. An asynchronous sequential circuit is described by the excitation and output functions Y = x1x2' +(x1+x2' ) y and Z =y (i) Draw the logic diagram of the circuit with a NOR SR latch. (ii)Derive the transition table and output map.

(6) (5)

(iii)Obtain a two-state flow table.

(5)