www.Vidyarthiplus.

com

Question Paper Code : 31298

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013.
Third Semester
Computer Science and Engineering
CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL PRINCIPLES
AND SYSTEM DESIGN
(Common to Information Technology)
(Regulation 2008/2010)
(Common to PTCS 2202 Digital Principles and System Design for B.E.
—

(Part-Time) Second Semester CSE Regulation 2009)

— —

Time : Three hours Maximum: 100 marks

Answer ALL questions.

PART A (10 x 2 = 20 marks)

1. Convert (1001010.1101001)2 to base 16 and (23 1.07)8 to base 10.

2. Realize XOR gate using only 4 NAND gates.
3. Implement F = XY’ Z + Y’ Z’+X’ Z using AOl logic.
4. Obtain the truth table for BCD to Excess-3 code converter.
5. Draw the truth table and circuit thagram of 4 to 2 encoder.
6. Distinguish EEPROM and flash memory.
7. Realize a JK ffip-flop using D ffip-flop be and gates.
8. Write the HDL code for up-down counter using behavioral model.
9. Distinguish fundamental mode circuit and pulse mode circuit.
10. Define primitive flow table.

PART B — (5 x 16 = 80 marks)

11. (a) Simplify the following Boolean function using Quine-McClusky method F = (A, B, C,
D, E)= ∑ m (0, 1, 3, 7, 13, 14, 21, 26, 8)+ ∑ d (2, 5, 9, 11, 17, 24). (16)
Or
(b) (i) Simplify the given Boolean function in POS form using K-map and draw the logic
diagram using only NOR gates.
F(A, B, C,D)= ∑ m (0,1, 4,7,8,10,12, 15)+ ∑ d (2, 6,11,14). (10)
(ii) Convert 78.510 into binary. (3)
(iii) Find the dual and complement of the following Boolean expression.
xyz’+x’yz+z(xy+w). (3).
12. (a) Design a combinational circuit to perform BCD addition. (16)
Or
(b) (i) Design a - —4-bit- —-magnitude comparator with three outputs:
A>B,A=B&A<B (12)
(ii) Construct a 4-bit odd parity generator circuit using gates. (4)
13. (a) (1) Realize 4 x 16 decoder using two 3 x 8 decoders with enable input. (4)
(ii) Implement the two following Boolean functions using 8 x 2 PROM.
Fl = ∑ m (3, 5, 6, 7) and F2 = ∑ m (1, 2, 3, 4). (6)

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

(iii) Implement the following function using a multiplexer.

F(W, X, Y, Z)= ∑ m (0, 1, 3, 4, 8, 9, 15). (6)
Or
(b) Implement the following two Boolean functions using PLA with 3 inputs, 4 product terms
and 2 outputs.
Fl = ∑ m (3, 5,6, 7) and F2 = ∑ m (1, 2, 3, 4). (16)

14. (a) Design a synchronous counter with the following sequence: 0,1,3,7,6,4 and repeats. Use JK
ffip-flops. (16)

(b) Design the sequential circuit specified by the following state diagram using T ffip-flops (16)

15. (a) (i) What is the objective of state assignment in asynchronous circuit? Explain race-
free state assignment with an example (8)
(ii) Discuss about static, dynamic and essential hazards in asynchronous sequential circuits
(8)
Or
(b) Design an asynchronous sequential circuit with inputs xl and x2 and one output z. Initially
and at any time if both the inputs are 0, output is equal to 0. When xl or x2 becomes 1, z
becomes 1. When second input also becomes 1, z = 0; The output stays at 0 until circuit goes
back to initial state. . . (16)

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

Question Paper Code : 31298

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013.
Third Semester
Computer Science and Engineering
CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL PRINCIPLES
AND SYSTEM DESIGN
(Common to Information Technology)
(Regulation 2008/2010)
(Common to PTCS 2202 Digital Principles and System Design for B.E.
—

(Part-Time) Second Semester CSE Regulation 2009)

— —

Time : Three hours Maximum: 100 marks

Answer ALL questions.

PART A (10 x 2 = 20 marks)

1. Convert (1001010.1101001)2 to base 16 and (23 1.07)8 to base 10.

2. Realize XOR gate using only 4 NAND gates.
3. Implement F = XY’ Z + Y’ Z’+X’ Z using AOl logic.
4. Obtain the truth table for BCD to Excess-3 code converter.
5. Draw the truth table and circuit thagram of 4 to 2 encoder.
6. Distinguish EEPROM and flash memory.
7. Realize a JK ffip-flop using D ffip-flop be and gates.
8. Write the HDL code for up-down counter using behavioral model.
9. Distinguish fundamental mode circuit and pulse mode circuit.
10. Define primitive flow table.

PART B — (5 x 16 = 80 marks)

11. (a) Simplify the following Boolean function using Quine-McClusky method F = (A, B, C,
D, E)= ∑ m (0, 1, 3, 7, 13, 14, 21, 26, 8)+ ∑ d (2, 5, 9, 11, 17, 24). (16)
Or
(b) (i) Simplify the given Boolean function in POS form using K-map and draw the logic
diagram using only NOR gates.
F(A, B, C,D)= ∑ m (0,1, 4,7,8,10,12, 15)+ ∑ d (2, 6,11,14). (10)
(ii) Convert 78.510 into binary. (3)
(iii) Find the dual and complement of the following Boolean expression.
xyz’+x’yz+z(xy+w). (3).
12. (a) Design a combinational circuit to perform BCD addition. (16)
Or
(b) (i) Design a - —4-bit- —-magnitude comparator with three outputs:
A>B,A=B&A<B (12)
(ii) Construct a 4-bit odd parity generator circuit using gates. (4)
13. (a) (1) Realize 4 x 16 decoder using two 3 x 8 decoders with enable input. (4)
(ii) Implement the two following Boolean functions using 8 x 2 PROM.
Fl = ∑ m (3, 5, 6, 7) and F2 = ∑ m (1, 2, 3, 4). (6)

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

(iii) Implement the following function using a multiplexer.

F(W, X, Y, Z)= ∑ m (0, 1, 3, 4, 8, 9, 15). (6)
Or
(b) Implement the following two Boolean functions using PLA with 3 inputs, 4 product terms
and 2 outputs.
Fl = ∑ m (3, 5,6, 7) and F2 = ∑ m (1, 2, 3, 4). (16)

14. (a) Design a synchronous counter with the following sequence: 0,1,3,7,6,4 and repeats. Use JK
ffip-flops. (16)

(b) Design the sequential circuit specified by the following state diagram using T ffip-flops (16)

15. (a) (i) What is the objective of state assignment in asynchronous circuit? Explain race-
free state assignment with an example (8)
(ii) Discuss about static, dynamic and essential hazards in asynchronous sequential circuits
(8)
Or
(b) Design an asynchronous sequential circuit with inputs xl and x2 and one output z. Initially
and at any time if both the inputs are 0, output is equal to 0. When xl or x2 becomes 1, z
becomes 1. When second input also becomes 1, z = 0; The output stays at 0 until circuit goes
back to initial state. . . (16)

www.Vidyarthiplus.com
 Reg. No. :

Question Paper Code : T3027

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009

Third Semester

Computer Science and Engineering

CS 2202 — DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. Draw the logic diagram for the Boolean expression ((A + B) C)′D using
NAND gates.

2. Perform subtraction using 1’s complement (11010)2 – (10000)2.

3. Perform 9’s and 10’s compliment subtraction between 18 and –24.

4. Draw the logic diagram for half adder.

5. What is the difference between decoder and demultiplexer?

6. What is programmable logic array? How does it differ from ROM?

7. Write down the difference between sequential and combinational circuits.

8. What is race around condition?

9. What is meant by lockout condition?

10. What are the steps for design of asynchronous sequential circuit?
 PART B — (5 × 16 = 80 Marks)

11. (a) Simplify the following Boolean expression using Quine McCluskey
method :

F = ∑ m (0, 9, 15, 24, 29, 30) + d (8, 11, 31) . (16)

Or

(b) (i) Implement Boolean expression for EXOR gate using NAND and
NOR gates. (8)

(ii) Prove that ( AB + C + D )(C ′ + D )(C ′ + D + E ) = ABC + D . (4)

(iii) Using 2’s complement perform (42)10 – (68)10. (4)

12. (a) (i) Explain the gray code to binary converter with the necessary
diagram. (10)

(ii) Design a half subtractor circuit. (6)

Or

(b) With neat diagram explain BCD subtractor using 9’s and 10’s
complement method. (16)

13. (a) Explain with necessary diagram a BCD to 7 segment display decoder.
(16)

Or

(b) (i) Write the comparison between PROM, PLA, PAL. (6)

(ii) Design a BCD to excess-3 code converter and implement using

PLA. (10)

14. (a) Design and implement a Mod-5 synchronous counter using JK flip-flop.
Draw the timing diagram also. (16)

Or

(b) (i) Explain the working of master slave JK flip-flop. (10)

(ii) Draw the diagram for a 3 bit ripple counter. (6)

2 T 3027
15. (a) (i) Design a comparator. (6)

(ii) Design a non sequential ripple counter which will go through the
states 3, 4, 5, 7, 8, 9, 10, 3, 4 .................. draw bush diagram also.
(10)

Or
(b) (i) Design a parity checker. (6)
(ii) Design a sequential circuit with JK flip-flop. (10)

0|1

————––––——

3 T 3027
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
 www.vidyarthiplus.com

www.vidyarthiplus.com Page 1
 www.vidyarthiplus.com

www.vidyarthiplus.com Page 2
 www.vidyarthiplus.com

Reg. No. :

Question Paper Code : 55293

21
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.

Third Semester

Computer Science and Engineering

4
CS 2202— DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 marks

Answer ALL questions.

21
PART A — (10 × 2 = 20 marks)

1. Perform the following code conversions:

(1010 .10 )16 → (?)2 → (?)8 → (?)10
4

2. State the different ways for representing the signed binary numbers.

3. With block diagram show how a full adder can be designed by using two
half adders and one OR gate.

4. List the modeling techniques available in HDL.

5. Define decoder. Draw the block diagram and truth table for 2 to 4 decoder.
21

6. What is the difference between Programmable array logic (PAL) and

Programmable logic array (PLA)?

7. How many flip flops are required for designing synchronous MOD60
counter?

8. Write down the characteristic equation for JK and T flip flops.

4

9. What is meant by Race condition in Asynchronous sequential circuit?

10. Define Hazard. List the Hazards in combinational circuit.

www.vidyarthiplus.com
 www.vidyarthiplus.com

PART B — (5 × 16 = 80 marks)

11. (a) Simplify the following Boolean function F using Karnaugh map
method:
(i) F(A, B, C, D)= ∑ (1,4,5,6,12,14,15) (4)
(ii) F(A, B, C, D) = ∑ (0,1,2,4,5,7,11,15) (4)

21
(iii) F(A, B, C, D) = ∑ (2,3,10,11,12,13,14,15) (4)
(iv) F(A, B, C, D) = ∑ (0,2,4,5,6,7,8,10,13,15) (4)

Or
(b) simplify the following Boolean expressions to a minimum number of

4
literals:
(i) AC + ABC + A C (2)

(ii) XYZ + X Y + XY Z (2)

(iii) XY + YZ + X Y Z (2)
(iv) A B + ABD + AB D + A C D + A B C (5)
(v) BD + BC D + A B C D (5)
21
12. (a) Consider the combinational circuit shown in Figure 1.
(i) Derive the Boolean expressions for T 1 through T4. Evaluate the
outputs F1 and F2 as a function of the four inputs. (4)
(ii) List the truth table with 16 binary combinations of the four
input variables. Then list the binary values for T1 through T4
4

and outputs F1 and F2 in the table. (4)

(iii) Plot the output Boolean function obtained in part (ii) on maps
and show that simplified Boolean expressions are equivalent to
the ones obtained in Part (i) (8)
21

Figure 1.
4

Or
(b) (i) With suitable block diagram explain Binary multiplier. (8)
(ii) Write a detailed note on carry propagation. (8)

2 55293

www.vidyarthiplus.com
 www.vidyarthiplus.com

13. (a) Construct a 5 to 32 line decoder with four 3 to 8 line decoders with
enable and a 2 to 4 line decoder. Use block diagrams for components.(16)

Or
(b) (i) Implement the following Boolean function with 16 × 1
multiplexer :
F ( A , B , C , D ) = ∑ (0 , 1, 3, 4 , 8 , 9 ,15 ) ,

21
Use block diagram representation. (6)
(ii) Write HDL gate level description for 3 to 8 line decoder. (4)
(iii) With suitable timing diagram explain how Read operation is
performed in Random access memory. (6) [6]

4
14. (a) Design a MOD 16 up counter using JK Flip flops. (16) [16]

Or
(b) With suitable example explain state reduction and state assignment.(16)

15. (a) Write a detailed note on Race free state assignment. (16) [16]

Or
(b)
21
With suitable design example, explain ASM Chart. (16) 16J

———————
4
21
4

3 55293

www.vidyarthiplus.com
 www.Vidyarthiplus.com

1
Reg. No. :

42
Question Paper Code : 13082
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.

19
Common to B.E./B.Tech. Computer Science and Engineering/Information
Technology

Third Semester

141302 — DIGITAL PRINCIPLES AND SYSTEMS DESIGN

Time : Three hours

42
(Regulation 2010)

Maximum : 100 marks

Answer ALL questions.

19
PART A — (10 × 2 = 20 marks)

1. Simplify the expression ((AB’ + ABC)’ + A (B + AB’))’.

2. Find the minimum expression of

42

Y = Π (0, 1, 3, 5, 6, 7, 10, 14,15).

3. Draw the full adder circuit as a collection of two half adder.

4. A circuit is to be designed that has one control line and three data lines. When
9

the control line is high, the circuit is to detect when one of the data lines has a
1 on it. No more than one data line will ever have a 1 on it. When the control
line is low, the circuit will output a 0, regardless of what is on the data lines.
21

5. The input frequency of a 7497 binary rate multiplier is 64 K Hz. What will its
output be if the multiplier word is 1011?

6. Implement a digital circuit that statistics the following :

94

F (A, B, C) = Σ (0, 2, 3, 4, 7), d (A, B, C) = (1)

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

1
7. Given a 8 bit data word 01011011, generate the 13 bit composite word for the
Hamming code that corrects single errors and detects double errors.

42
8. Draw a 4- bit binary synchronous counter with D flip flops.

9. Draw a circuit that has no static hazards and implement the boolean function

19
F (A, B, C, D) = Σ (0,2,6, 7, 8, 10, 12)

10. Find a critical race free state assignment for the reduced flow table shown.

42
19
PART B — (5 × 16 = 80 marks)

11. (a) Reduce the expression using Quine McCluskey method.

F (x 1 , x 2 , x 3 , x 4 , x 5 ) = Σm (0, 2, 4, 5, 6, 7, 8, 10, 14, l7, l8, 21, 29, 31) +
Σd (11, 20, 22). (16)
42

Or

(b) Explain the conversion of regular expression into canonical expression

and their simplification in SOP and POS forms. (16)

12. (a) Design a combinational circuit that multiplies by 5 an input decimal digit
9

represented in BCD. The output is also in BCD. Show that the outputs
can be obtained from the input lines without using any logic gates. (16)

Or
21

(b) A circuit receives only valid 5211 or 8421 BCD information and provides
two output lines X and Y. Design the circuit such that X will provide an
output anytime a valid 8421 BCD code appears at the input and Y will
provide an output anytime a valid 5211 BCD code appears at the input.
(16)
94

2 13082

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

1
13. (a) Implement the following Boolean function with a 4 X 1 multiplexer and
external gates. Connect inputs A and B to the selection lines. The input

42
requirements for the four data lines will be a function of variables C and
D. these values are obtained by expressing F as a function of C and D for
each of the four cases when AB=00, 01, 10 and 11. These functions may
have to be implemented with external gates.

F(A,B,C,D)= Σ (1,3,4, 11, 12, 13, 14, 15)

19
Or

(b) Design a combinational circuit that compares two 4 bit numbers A and B
to check if they are equal. The circuit has three output x, y, z so that x =1
if A = B and y = 1 if A < B and z = 1 if A > B.

14. (a) (i) Reduce the number of states in the state table and tabulate the

a
reduced state table.
Present
state
X=0
f
42
Next state

X=l
b
X=0
0
Output

X=1
0
(8)

b d c 0 0
19
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
42

(ii) Starting from state a of the state table, find the output sequence
generated with an input sequence 01110010011. (8)

Or

(b) Design the following non binary sequence counters as specified in each
9

case. Treat the unused states as don’t care conditions. Analyze the final
circuit to ensure that it is self correcting. If your design produces a non
self correcting counter, modify the circuit to make itself correcting.

(i) Design a counter with the following repeated binary sequence: 0,1,
21

2, 3, 4, 5, 6. Use JK flipflops. (6)

(ii) Design a counter with the following repeated binary sequence: 0,1,
2, 4, 6. Use D flipflops. (5)

(iii) Design a counter with the following repeated binary sequence: 0,1,
3, 5, 7. Use T flipflops. (5)
94

3 13082

www.Vidyarthiplus.com
 www.Vidyarthiplus.com

1
15. (a) A traffic light is installed at a junction of railroad and road. The traffic
light is controlled by two switches in the rails placed one mile apart on

42
either side of the junction. A switch is turned on when the train is over it
and is turned off otherwise. The train light changes from green (logic -0)
to red (logic - 1) when the beginning of the train is one mile from the
junction. The light changes back to green when the end of the train is one
mile away from the junction. Assume that the length of the train is less
than two miles.

19
(i) Obtain the primitive flow table for the circuit.

(ii) Show that the flow table can be reduced to four rows. (16)

Or

(b) An asynchronous sequential circuit is described by the following

excitation and output functions

Y = x1x 2'+( x1 + x 2' ) y

Z=y

(i)
42
Draw the logic diagram of the circuit.
19
(ii) Derive the transition table and output map.

(iii) Obtain 2 state flow table.

(iv) Describe in words the behavior of the circuit. (16)

—————————
9 42
21
94

4 13082

www.Vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com
www.vidyarthiplus.com

www.vidyarthiplus.com