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Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability
of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low
power technique. Advantage of this method is that clock gating does not require modifications to
RTL description.
What is difference between normal buffer and clock buffer?
Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some
special property like high drive strength and less delay. Clock buffers have equal rise and fall
time. This prevents duty cycle of clock signal from changing when it passes through a chain of
clock buffers.
Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum.
They too are designed for higher drive strength.
What is difference between HFN synthesis and CTS?
HFNs are synthesized in front end also.... but at that moment no placement information of
standard cells are available... hence backend tool collapses synthesized HFNs. It resenthesizes
HFNs based on placement information and appropriately inserts buffer. Target of this synthesis is
to meet delay requirements i.e. setup and hold.
For clock no synthesis is carried out in front end (why.....????..because no placement information
of flip-flops ! So synthesis won't meet true skew targets !!) ... in backend clock tree synthesis tries
to meet "skew" targets...It inserts clock buffers (which have equal rise and fall time, unlike
normal buffers !)... There is no skew information for any HFNs.
Is it possible to have a zero skew in the design?
Theoretically it is possible....!
Practically it is impossible....!!
Practically we cant reduce any delay to zero.... delay will exist... hence we try to make skew
"equal" (or same) rather than "zero"......now with this optimization all flops get the clock edge
with same delay relative to each other.... so virtually we can say they are having "zero skew " or
skew is "balanced".
13. How will you handle bi-directional pins during CTS?
14. Handling of high fan out nets like clock ,scan enable and reset pins
15. How to Build the clock tree for Hard macros ?
16. If you want to synchronize a nonclock pin—such as a combination logic gate’s pin, a macro’s
pin, or a sequential gate’s set/reset pin—you must define it as a synchronous pin explicitly.
17. Explain all CT topology? Which topology will you prefer for ur design?
- H –Tree
- Single Fish born
- Double fish born
