Unit 2

VHDL Basics

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Basic VHDL Concepts

Interfaces
Behavior
Structure
Test Benches
Analysis, elaboration, simulation
Synthesis

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 Design Flow
There are several steps in HDL based
design process called as Design flow;
applicable to all the HDL designs. It is
divided in four groups
ii. Specifications
iii. Verification
iv. Implementation
v. System debug

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Digital Logic Design Ravindra Bhat 4
 Specification
Specifications stage

Verification stage

Verification

Implementation

System Debug
Implementation
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Specification
For a complete set of specifications, it is
necessary to define the general structure of
an initial design of the product.
First the essential features of the product are
identified, and an acceptable method of
evaluating the implemented features in the
final product is established.
Then we draw Schematic diagram or write
VHDL code to start with.
This is provided for synthesis for referring to
specific hardware technology and required
libraries.
Then compilation of the code is carried out for
syntax,
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Verification
It is mainly simulation stage allowing us to
design and apply input to our design and
observe the output.
It can be done manually or with test
bench to verify that designed circuit is
working correctly and as desired.
There are two type of verifications done in
this stage functional verification and
timing verification. In functional the logical
operation of circuit with out time
constraints is verified where as in timing it
is checked w.r.t timing taking into
consideration delay, hold etc.
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 If there are any problems, the designer
has to go back to the specification stage
(simulation/VHDL file) make the changes,
and then return to the simulation.
After verifying the design it is also possible
to simulate directly from the VHDL source
file.
Once the circuit works correctly, we would
need to run the next step in the design
flow Implementation.

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Implementation
We now have a design that completely
describes our circuit using the gates from
a specific vendor/ device family and it has
been fully verified. It is now time to put
this in a chip, referred to as
Implementation.
First step is Translate. Translate consists
of various programs that are used to
import the design constraints and prepare
it for layout.
The translate step usually ends with a
comprehensive report of the results of all
the programs executed. In addition to
warnings and errors, there is usually a
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Fitting
This design step is called Fitting to “Fit”
the design to the target device.
The fitter maps the synthesized primitives
or components on to available device
resources.
It may mean assigning equations for
available gate elements or selecting
micro-cells or laying down individual gates
in pattern and finding out ways to connect
them within the physical constraints.
This is called place and route process.
A Static Timing Analyzer is usually part of
the vendor’s implementation software. It
provides timing information about paths in
the design. This information is very
accurate and can be viewed in many
different ways (e.g.
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display all paths in the10
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 In addition, the user at this point can use
the detailed layout information after
reformatting, and go back to his simulator
of choice with detailed timing information.
This process is called Back-Annotation and
has the advantage of providing the
accurate timing as well as the zeros and
ones operation of his design.
In both cases, the timing reflects delays of
the logic blocks as well as the
interconnect.
final implementation step is the Download
or Program.
Download generally refers to volatile
devices; you download
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the device 11
 The Bitstream that is transferred contains
all the information to define the logic and
interconnect of the design.
Program is used to program all non-
volatile devices.
Programming performs the same function
as download except that the configuration
information is retained after the power is
removed from the device.

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System Debug
At this point in the design flow, the device
is now working but we’re not done yet. We
need to do a System Debug - verify that
our device works in the actual board.
Any major problems here means the
engineer has made a assumption on the
device specification that is incorrect or has
not considered some aspect of the signal
required to/from the device.
If so, he will then collect data on the
problem and go back to the Specification
stage.
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Program Structure
VHDL provides five different types of
primary constructs, called" design units.
They are

1. Entity declaration
 2. Architecture body

 3. Configuration declaration


4. Package declaration
 5. Package body

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Entity
An entity defines the input and output
ports of a design. A design can contain
more than one entity. Each entity has its
own architecture statement.
The syntax follows.
entity entity_name is [ generic
generic_declarations );]
[ port ( port_declarations ) ;]
end [ entity_name ] ;
entity_name is the name of the entity.
generic_declarations determine local
constants used for sizing or timing the
entity.
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 Primary programming abstraction is a
design entity exp. – Register, logic
block, chip, board, or system.
We want to describe – Interface & its
function.
An entity serves as an interface to other
designs
The interface is a collection of ports
– Ports are a new programming object:
signal
– Ports have a type, e.g., bit
– Ports have a mode: in, out, in/out
(bidirectional)
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Example Entity Descriptions
Entity Generic Mode Mode
name _port

Port
name

Mode
_ port
type

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Digital Logic Design Ravindra Bhat 18
Architecture
Architecture body
– describes an implementation of an entity
– may be several per entity
Behavioral architecture
– describes the algorithm performed by the
module
It contains :
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements
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 Structural architecture
– implements the module as a composition
of subsystems
It contains :
• signal declarations, for internal
interconnections
– the entity ports are also treated as
signals
• component instances
– instances of previously declared
entity/architecture pairs
• port maps in component instances
– connect signals to component ports
• wait statements Ravindra Bhat
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 An architecture can contain both
behavioral and structural parts
– process statements and component
instances
collectively called concurrent statements
– processes can read and assign to signals

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Architecture Body
The internal details of an entity are
specified by an architecture body using
any of the following modeling styles:
As a set of interconnected components (to
represent structure). Structural style
2. As a set of concurrent assignment
statements (to represent dataflow).
Dataflow style
3. As a set of sequential assignment
statements (to represent behavior).
Behavioral style
4. Any combination of the above three.
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 In the Structural style of modeling, an entity
is described as a set of interconnected
components.
In Dataflow style, the flow of data through the
entity is expressed primarily using concurrent
signal assignment statements. The structure
of the entity is not explicitly specified in this
modeling style, but it can be implicitly
deduced.
The Behavioral style of modeling specifies the
behavior of an entity as a set of statements
that are executed sequentially in the
specified order. This set of sequential
statements, that are specified inside a
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 Architecture, determines the
implementation of an entity.
The syntax follows.
architecture architecture_name of
entity_name is
{ block_declarative_item }
begin
{ concurrent_statement }
end [ architecture_name ] ;
• architecture_name is the name of the
architecture.
• entity_name is the name of the entity
being implemented.
• block_declarative_item is any of the
following statements.
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- Subprogram Declarations
 - Subprogram Body
- Type Declarations
- Subtype Declarations
- Constant Declarations
- Signal Declarations
- Concurrent Statements
- Components
- Processes

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Subprograms
Subprograms use sequential statements to
define algorithms and are useful for
performing repeated calculations.
Subprograms declared in an architecture
are local to that architecture.
Subprograms cannot directly read or write
signals from the rest of the architecture.
All communication is through the
subprogram’s interface.
Each subprogram call has its own set of
interface signals.

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 There are two types of subprograms,
which can have zero or more parameters.
• Procedure Subprogram
A procedure returns zero or more
values through its interface.
• Function Subprogram
A function returns a single value
directly.
A subprogram has two parts.
• Declaration
• Body
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 Procedure Declaration Syntax
The syntax of a procedure declaration follows.
procedure proc_name [(parameter_declarations)];
• proc_name is the name of the procedure.
• parameter_declarations specify the number and type
of input and output ports.
The syntax follows.
[ parameter_name : mode parameter_type
{ ; parameter_name : mode parameter_type}]
• parameter_name is the name of a parameter.
• mode is procedure parameters that can be any of
the following four modes.
it can only be read out
can only be assigned a value.
in/out can be read and assigned a value.
The value read is that of the port’s incoming value,
not the assigned value (if any) buffer is similar to out
but can be read. The value read is the assigned value.
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The syntax of a function declaration follows.
function func_name [ ( parameter_declarations ) ]
return type_name ;
• func_name is the name of the function
• type_name is the type of the function’s
returned value.
• Signal parameters of type range cannot be passed
to a subprogram.
• parameter_declarations specify the number and
type of input and output ports.
The syntax follows.
[ parameter_name : mode parameter_type
{ ; parameter_name : mode parameter_type}]
• parameter_name is the name of a
parameter.
• mode: Function parameters can only use
the
Digital in mode.
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 Subprogram Body
A subprogram body defines an implementation of a
subprogram’s algorithm.
Procedure Body Syntax
The syntax of a procedure body follows.
procedure procedure_name [ (parameter_declarations) ] is
{ subprogram_declarative_item }
begin
{ sequential_statement }
end [ procedure_name ] ;
• procedure_name is the name of the procedure.
• subprogram_declarative_item can be any of the following
statements.
• use clause
• type declaration
• subtype declaration
• constant declaration
• variable declaration
• attribute declaration
• attribute specification
• subprogram declarationRavindra
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The syntax of a function body follows.
function function_name [ (parameter_declarations) ]
return type_name is
{ subprogram_declarative_item }
begin
{ sequential_statement }
end [ function_name ] ;
• function_name is the name of the function.
• subprogram_declarative_item can be any of the following
statements.
• use clause
• type declaration
• subtype declaration
• constant declaration
• variable declaration
• attribute declaration
• attribute specification
• subprogram declaration (for local, or nested
subprograms)
• subprogram body (for locally declared subprograms)
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 Type Declarations
You declare each signal with a type that
determines the kind of data it carries.
Types declared in an architecture are local
to that architecture.
You can use type declarations in
architectures, packages, entities, blocks,
processes, and subprograms.
Type declarations define the name and
characteristics of a type.
A type is a named set of values, such as
the set of integers or the set (red, green,
blue). An object of a given type, such as a
signal,
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 Subtype Declarations
Use subtype declarations to define the
name and characteristics of a constrained
subset of another type or subtype. A
subtype is fully compatible with its parent
type, but only over the subtype’s range.
You can use subtype declarations
wherever you use type declarations: in
architectures, packages, entities, blocks,
processes, and subprograms.

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 Constant Declarations
Constant declarations create named
values of a given type. The value of a
constant can be read but not changed.
Constant declarations are allowed in
architectures, packages, entities, blocks,
processes, and subprograms. Constants
declared in an architecture are local to
that architecture.
You can use constants in expressions & as
source values in assignment statements.

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 Signal Declarations
Signals connect the separate concurrent
statements of an architecture to each
other, and to other parts of a design,
through interface ports.
Signal declarations create new named
signals (wires) of a given type. Signals can
be given default (initial) values, but these
initial values are ignored for synthesis.
Signals with multiple drivers (signals
driven by wired logic) can have associated
resolution functions

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 Concurrent Statements
Each concurrent statement in an
architecture defines a unit of computation
that does the following.
• Reads signals
• Performs a computation that is based on
the values of
the signals
• Assigns the computed values to the
signals.
Concurrent statements all compute their
values at the same time. Although the
order of concurrent statements has no
effect on the orderRavindra
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 The five kinds of concurrent statements follow.
• Block
Groups a set of concurrent statements.
• Component instantiation
Creates an instance of an entity, connecting
its interface ports to signals or interface ports
of the entity being defined.
• Procedure call
Calls algorithms that compute and assign
values to signals.
• Process
Defines sequential algorithms that read the
values of signals and compute new values to
assign to other signals.
• Signal assignments
Assign computed values to signals or
interface ports.
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 Components
If your design consists only of VHDL entity
statements, every component declaration in the
architecture or package statement has to
correspond to an entity.
Components declared in an architecture are local
to that architecture.
The syntax follows.
component identifier
[ generic( generic_declarations ); ]
[ port( port_declarations ); ]
end component ;
• identifier is the name of the component.
• generic_declaration determines local constants
used for sizing or timing the component.
• port_declartion determines the number and
type of input and output ports.
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 Processes
A process, which is declared within an
architecture, is a concurrent statement. But it is
made up of sequentially executed statements
that define algorithms.
The sequential statements can be any of the
following:
• case statement
• exit statement
• if statement
• loop statement
• next statement
• null statement
• Procedure call
• Signal assignment
• Variable assignment
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 Processes, like all other concurrent
statements, read and write signals and the
values of interface ports to communicate
with the rest of the architecture and with
the enclosing system.
Processes are unique in that they behave
like concurrent statements to the rest of
the design, but they are internally
sequential.
only processes can define variables to hold
intermediate values in a sequence of
computations.
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 Configuration declaration

A design entity can have multiple

alternative architectures.
A configuration specifies the architecture
that is to be used to implement a design
entity.
We are concerned with configuring the
architecture and not the entity.
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 The configuration statement maps
component instantiations to entities.
With this powerful statement, the modeler
can pick and choose which architectures
are used to model an entity at every level
in the design.
Simply change the configuration it
enhances sharing of designs.

NOTE : Not to be discussed!!!!! Just

information!

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 Package declaration
The primary purpose of a package is to
encapsulate elements that can be shared
(globally) among two or more design units.
A package is a common storage area used
to hold data to be shared among a number
of entities.
A package consists of two parts: a
package declaration section and a
package body.
The package declaration defines the
interface for the package, much the same
way that the entity defines the interface
for a model.
Declaration of the functions, procedures,
and types that are available in the
package.
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 package_declaration ::=
package identifier is
package_declarative_part
end [ package ] [ package_simple_name ] ;
package_declarative_part ::=
{ package_declarative_item }
package_declarative_item ::=
subprogram_declaration
| type_declaration
| subtype_declaration
| constant_declaration
| signal_declaration
| shared_variable_declaration
| file_declaration
| alias_declaration
| component_declaration
| attribute_declaration
| attribute_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration
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 Package Body
Implementation of the functions and
procedures declared in the package
header.
Instantiation of constants provided in the
package header.
The main purpose of the package body is
to define the values for deferred constants
and specify the subprogram bodies for any
subprogram declarations from the
package declaration.
All of the declarations in the package
body, except for the constant declaration
that
Digital is specifying the
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 package_body ::=
package body package_simple_name is
package_body_declarative_part
end [ package body ] [ package_simple_name ] ;
package_body_declarative_part ::=
{ package_body_declarative_item }
package_body_declarative_item ::=
subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| shared_variable_declaration
| file_declaration
| alias_declaration
| use_clause
| group_template_declaration
| group_declaration

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 Type, Constants and Array
Type: VHDL is a strongly typed language.
Every constant, signal, variable, function,
and parameter is declared with a type,
such as BOOLEAN or INTEGER, and can
hold or return only a value of that type.
Constants: A constant declaration
declares a constant of the specified type.
An object of constant class can hold a
single value of a given type.
Array : An array type represents a
collection of values all belonging to a
single type
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Type :
This chapter describes VHDL data
types and their uses. Data type
information is included in the
following sections.
• “Enumeration Types”
• “Integer Types”
• “Array Types”
• “Predefined VHDL Data Types”
• “Unsupported Data Types”
• “Express Data Types”
• “Subtypes”
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 Enumeration Types
Enumeration types are called discrete types.
You define an enumeration type by listing
(enumerating) all possible values of that type.
The syntax of an enumeration type definition
is
type type_name is ( enumeration_literal ,
{enumeration_literal} );
type_name : An identifier. An identifier is a
sequence of letters, underscores, and
numbers.
It must start with a letter and cannot be a
VHDL reserved word, such as TYPE.
Each enumeration_literal is either an identifier
(enum_6) or a character
Digital Logic Design
literal (’A’).
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 VHDL reserved words

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 Enumeration Encoding
Examples: Enumeration Type Definitions

Enumeration Literal Overloading

Enumeration types are ordered by

enumeration value. By default, the first
enumeration literal is assigned the value
0, the next enumeration literal is assigned
the value 1, and so forth.
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 Enumeration Encoding Values
The possible encoding values for the
ENUM_ENCODING attribute are ’0’, ’1’, ’D’,
’U’, and ’Z’:
’0’: Bit value ’0’.
’1’ :Bit value ’1’.
’D’ :Don’t care (can be either ’0’ or ’1’). To
use don’t care information.
’U’ : Unknown. If ’U’ appears in the encoding
vector for an enumeration, you cannot use
that enumeration literal except as an operand
to the = and /= operators. You can read an
enumeration literal encoded with a ’U’ from a
variable or signal, but you cannot assign it.
For synthesis, the = operator returns false
and /= returns true when either of the
operands is an enumeration literal whose
encoding contains ’U’.
’Z’ : High impedance.
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 Integer Types
An integer type defines a type whose set
of values fall within a specified integer
range.
The bounds of the range for an integer
type must be constants or locally static
expressions; a locally static expression is
an expression that computes to a constant
value at compile time (a globally static
expression is an expression that computes
to a constant value at elaboration time).
Integer types, floating point types, and
physical types are called numeric types.
Integer literals areRavindra
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 Types declared with the keyword to are
called ascending ranges, and those
declared with the keyword downto are
called descending ranges.
The range of this type is implementation
defined, though it is guaranteed to include
–2147483647 to +2147483647.(- (231-1)
to +(231-1)).
The syntax of an integer type definition
follows.
type type_name is range integer_range ;
type_name is the name of the new integer
type, and integer_range is a subrange of
the anonymous integer
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 Example

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 Array Types
An array is an object that is a collection of
elements of the same type.
Array elements can be of any type. An
array has an index whose value selects
each element.
The index range determines how many
elements are in the array and their
ordering (low to high, or high downto low).
An index can be of any integer type.
In addition, an array type may be
constrained, in which the bounds for an
index are established when the type is
defined,
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 A constrained array’s index range is
explicitly defined.
The syntax of a constrained array type
definition follows.
type array_type_name is array ( integer_range )
of type_name ;
• array_type_name is the name of the new
constrained array type
• integer_range is a subrange of another
integer type
• type_name is the type of each array
element.
An example of a constrained array type
definition follows.
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 You define an unconstrained array’s index range
as a type; for example, INTEGER.
This definition implies that the index range can
consist of any subset of that type’s values.
When you declare an array variable or signal of
this type, you also define its actual index range.
Different declarations can have different index
ranges.
The syntax of an unconstrained array type
definition follows.
type array_type_name is
array (range_type_name range <>) of
element_type_name ;
• array_type_name is the name of the new
unconstrained array type
• range_type_name is the name of an integer
Digital Logic Design Ravindra Bhat 58
type or subtype
 An example of an unconstrained array
type definition and a declaration that uses
it follows.

The advantage of using

unconstrained arrays is that a VHDL
tool can recall the index range of
each declaration.
You can use array attributes to
determine the range (bounds) of a
signal or variable of an
unconstrained array type.
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Array Attributes
attributes for use with arrays.
• left
• right
• high
• low
• length
• range
• reverse_range
The above attributes return a value
corresponding to part of an array’s
range.
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 Array Index Attributes

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 Examples

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 Predefined VHDL Data Types
The predefined enumeration types are
Character, Bit, Boolean, Integer ,Natural,
Positive, String, Bit_Vector
Character:
The predefined type CHARACTER is a
character type whose values are the 256
characters of the character set.
Each of the 191 graphic characters of this
character set is denoted by the corresponding
character literal.
The CHARACTER data type enumerates the
ASCII character set. Nonprinting characters
are represented by a three-letter name, such
as NUL for the null character. Printable
characters are represented by themselves, in
single quotation marks,
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as follows.
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Boolean:
The BOOLEAN data type is actually an
enumerated type with two values, FALSE
and TRUE, where FALSE < TRUE.
Logical functions such as equality (=) and
comparison (<) functions return a
BOOLEAN value.
Convert a BIT value to a BOOLEAN value
as follows.
BOOLEAN_VAR := (BIT_VAR = ’1’);

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Bit:
The BIT data type represents a binary
value as one of two characters, 0 or 1.
Logical operations, such as AND, can take
and return BIT values.
Convert a BOOLEAN value to a BIT value
as follows.
if (BOOLEAN_VAR) then
BIT_VAR := ’1’;
else
BIT_VAR := ’0’;
end if;
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Integer:
The INTEGER data type represents
positive and negative whole numbers.
Natural:
The NATURAL data type is a subtype of
INTEGER that is used to represent natural
(nonnegative) numbers.
Positive:
The POSITIVE data type is a subtype of
INTEGER that is used to represent positive
(nonzero and nonnegative) numbers.
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String:
The STRING data type is an unconstrained
array of CHARACTER data types. A STRING
value is enclosed in double quotation
marks, as follows.
variable STRING_VAR: STRING(1 to 7);
STRING_VAR := "Rosebud";
Bit_vector :
The BIT_VECTOR data type represents an
array of BIT values.

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 Predefined attributes denote values,
functions, types, and ranges associated
with various kinds of named entities.
These attributes are described below. For
each attribute, the following information is
provided:
 The kind of attribute: value, type, range,

function, or signal
 The prefixes for which the attribute is

defined
 A description of the parameters or

argument, if one exists

 The result of evaluating the attribute,

and the result type (if applicable)

Digital  Any
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 Unsupported Data Types
Some data types are either not useful for
synthesis or are not supported. The
following sections list and describe these
unsupported data types.
Physical Types
Some Compilers does not support physical
types, such as units of measure (for
example, ns).
Floating-Point Types
Some Compilers does not support floating-
point types, such as REAL.
Access Types
Some Compilers does not support access
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File Types
Some Compilers does not support file (disk
file) types, such as a hardware file type
RAM or ROM.

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 Express Data Types
With this package, you can perform
arithmetic operations and numeric
comparisons on array data types.
The package also defines two major data
types; UNSIGNED and SIGNED.
These data types, unlike the predefined
INTEGER type, provide access to the
individual bits (wires) of a numeric value.

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Unsigned
The Unsigned data type represents an
unsigned numeric value. The number is
interpreted as a binary representation with
the farthest-left bit being most significant.
For example, the decimal number 8 can be
represented by the following.
Unsigned’("1000").
When you declare variables or signals of
type UNSIGNED, a larger vector holds a
larger number.
By definition, negative numbers cannot be
represented in an UNSIGNED variable.
Digital Logic Design Ravindra Bhat 73
Zero is the smallest value that can be
Signed
The SIGNED data type represents a signed
numeric value. The number is interpreted
as a 2’s complement binary
representation, with the farthest-left bit as
the sign bit. For example, you can
represent decimal 5 and -5 by the
following.
SIGNED’("0101") -- represents +5
SIGNED’("1011") -- represents -5
When you declare SIGNED variables or
signals, a larger vector holds a larger
number.
Digital Logic Design Ravindra Bhat 74
 Subtypes
A subtype is defined as a subset of a
previously defined type or subtype. A
subtype definition can appear anywhere a
type definition is allowed.
Using subtypes is a powerful way to use
VHDL type checking to ensure valid
assignments and meaningful data
handling.
Subtypes inherit all operators and
subprograms defined for their parent
(base) types.
Subtypes are also used for resolved
signals
Digital Logic Design to associate a Bhat
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 Subprograms
Subprograms are independent, named
algorithms. A subprogram is either a
procedure (zero or more in, in/out, or out
parameters) or a function (zero or more in
parameters and one return value).
A procedure call is a statement; a function
call is an expression and returns a value.
Subprograms defines algorithms for
computing values or exhibiting behavior.
They may be used as computational
resources to convert between values of
different types, to define the resolution of
output values driving a common signal, or
to define portions of a process.
Digital Logic Design Ravindra Bhat 76
 There are two versions of procedures and
functions: a concurrent procedure and
concurrent function, and a sequential
procedure and sequential function.
The concurrent procedure and function
exist outside of a process statement or
another subprogram; the sequential
function and procedure exist only in a
process statement or another subprogram
statement.
All statements inside of a subprogram are
sequential. The same statements that
exist in a process statement can be used
in a subprogram.
A procedure existsRavindra
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 Procedures and functions are two kinds of
subprograms.
• Procedures

Can have multiple parameters that use
modes in, in/out, and out Procedures do
not return a value.

Procedures are used when you want to
update some parameters (modes out and
in/out) or when you do not need a return
value. An example might be a procedure
with one in/out bit vector parameter that
inverted each bit in place.
• Functions

Can have multiple parameters, but only
parameters thatRavindra
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Function
Syntax of function
function_name ( [parameter_name =>]
expression
{, [parameter_name =>] expression }) ;
• function_name is the name of a defined
function.
• parameter_name, which is optional, is the
name of a formal parameter as defined by
the function. Each expression provides a
value for its parameter and must evaluate
to a type appropriate for that parameter.
You can specify parameter values in
positional or named notation, as you can
Digital Logic Design Ravindra Bhat 79
aggregate values.
 The example below shows a simple
function definition and two calls to that
function.

Digital Logic Design Ravindra Bhat 80

return Statements
The return statement terminates a
subprogram. A function definition requires
a return statement. In a procedure
definition, a return statement is optional.
The syntax follows.
return expression ; -- Functions
return ; -- Procedures
• expression provides the return value of
the function. Every function must have at
least one return statement. The
expression type must match the declared
function type. Only one return statement
is reached by a given function call.
• procedure can have one or more return
statements, but no expression. A return
statement, if present, is the last statement
executed in a procedure.
Digital Logic Design Ravindra Bhat 81
Procedure Calls
A procedure call executes the named
procedure with the given
parameters. The syntax follows.
procedure_name [ ( [ name => ]
expression
{ , [ name => ] expression } ) ] ;

expression: Each expression is called an
actual parameter; expression is often
just an identifier. If a name is present
(positional notation), it is a formal
parameter name associated with the
actual parameter’s expression.
Digital Logic Design Ravindra Bhat 82
 A procedure call occurs in three steps.
1. Foundation Express assigns the values
of the in and in/out actual parameters to
their associated formal parameters.
2. The procedure executes.
3. Foundation Express assigns the values
of the inout and out formal parameters are
assigned to the actual parameters.

Digital Logic Design Ravindra Bhat 83

Subprogram Overloading
You can overload subprograms which
means that one or more subprograms can
have the same name. Each subprogram
that uses a given name must have a
different parameter profile.
A parameter profile specifies a
subprogram’s number and type of
parameters.
This information determines which
subprogram is called when more than one
subprogram has the same name.
Overloaded functions are also
distinguished
Digital Logic Design by the
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 The following example shows two
subprograms with the same name, but
different parameter profiles.

Digital Logic Design Ravindra Bhat 85

 Library and package
The first two lines,
l i b r a r y ieee;
use ieee. std-logic-1164, a l l ;
invoke the std-logic-1164 package
from the i e e e library. The package
and library allow us to add additional
types, operators, functions, etc. to
VHDL. The two statements are
needed because a special data type
is used in the code.
Digital Logic Design Ravindra Bhat 86
Packages
A package is a collection of declarations that
more than one design can use.
This chapter explains packages and how
compiled design units are stored in design
libraries. It explains how the contents of
design units stored in different libraries may
be shared by several design units.
A package provides a convenient mechanism
to store and share declarations that are
common across many design units. A
package is represented by
 a package declaration, A package
declaration defines the visible contents of a
package and optionally,
 a package body. a package body provides
hidden details. InRavindra
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a package 87
Package declaration
A package declaration defines the
interface to a package. The scope of a
declaration within a package can be
extended to other design units.
It defines the interface to the package,
that is, it defines items that can be made
visible to other design units.
Items declared in a package declaration
can be accessed by other design units by
using the library and use context clauses.
The set of common declarations may also
include function and procedure
declarations
Digital Logic Design and deferred
Ravindra Bhat constant 88
 The syntax of a package declaration is
package package-name is
 package-item-declarations "> These may be:

- subprogram declarations ~ type

declarations
- subtype declarations
- constant declarations
- signal declarations
- file declarations
- alias declarations
- component declarations
- attribute declarations
- attribute specifications
- disconnection specifications
- use clauses
end [ package-name ] ;
Digital Logic Design Ravindra Bhat 89
 Examples:
— A package declaration that needs no package body:

package TimeConstants is
constant tPLH : Time := 10 ns;
constant tPHL : Time := 12 ns;
constant tPLZ : Time := 7 ns;
constant tPZL : Time := 8 ns;
constant tPHZ : Time := 8 ns;
constant tPZH : Time := 9 ns;
end TimeConstants ;
— A package declaration that needs a package body:

package TriState is
type Tri is ('0', '1', 'Z', 'E');
function BitVal (Value: Tri) return Bit ;
function TriVal (Value: Bit) return Tri;
type TriVector is array (Natural range <>) of Tri ;
function Resolve (Sources: TriVector) return Tri ;
end package TriState ;

Digital Logic Design Ravindra Bhat 90

Libraries
It is where the compiler stores information
about particular project along with
intermediate files used in analysis,
synthesis and simulation of the design .
The designer can specify the name of library
to be used under library clause .
A library clause defines logical names for
design libraries in the host environment. A
library clause appears as part of a context
clause at the beginning of a design unit.
There is a certain region of text called the
scope of a library clause; this region,
contained within the root declarative region,
starts immediately after the library clause,
and
Digital it extends to the
Logic Design end
Ravindra Bhat of the root 91
 Libraries represent
– Relationships between design units and
libraries
– Visibility Rules
The library clause makes visible the logical
names of design libraries that can be
referenced within a design unit. The
format of a library clause is
- library list-of-logical-library-names;

Digital Logic Design Ravindra Bhat 92

 • Design units are analyzed (compiled) and
placed in libraries
• Logical library names map to physical
directories
• Libraries STD and WORK are implicitly
declared

Digital Logic Design Ravindra Bhat 93

 When multiple design units are in the
same file visibility of libraries and
packages must be established for each
primary design unit (entity, package
header, configuration) separately!
– Secondary design units derive library
information from associated primary
design unit
The use clause may selectively establish
visibility, e.g., only the function
rising_edge() is visible within entity
design-2
– Secondary design inherit visibility
Digital Logic Design Ravindra Bhat 94
 A design library is an implementation-
dependent storage facility for previously
analyzed design units. A given
implementation is required to support any
number of design libraries.
library_clause ::= library
logical_name_list ;
logical_name_list ::= logical_name { ,
logical_name }
logical_name ::= identifier

Digital Logic Design Ravindra Bhat 95

 A design file may contain a number of
library units. The structure of a design file
can be specified by the syntax:
design_file ::= design_unit { design_unit }
design_unit ::= context_clause library_unit
context_clause ::= { context_item }
context_item ::= library_clause |
use_clause
library_clause ::= library
logical_name_list ;
logical_name_list ::= logical_name { ,
logical_name }
library_unit ::= primary_unit |
secondary_unit
primary_unit ::=
entity_declarationRavindra
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