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Clock Tree Synthesis (CTS) Interview Questions

vlsi4freshers December 30, 2019 Add Comment  CTS , STA , STA Interview Questions

In this post I am writing some frequently asked Clock Tree Synthesis (CTS) Interview Questions
Q1. What is Clock Tree Synthesis (CTS)? Why do we need it?
CTS is insertion of buffers or inverter along the clock path to balance the clock delay to all the clock
inputs of different flops in the same design is called CTS.
Since some amount of delay is associated with every physical wire due to RC factor associated with it,
which results into clock not reaching to the clock pin of all the flops at same time in the design. So by
adding buffers/inverters, we try to maintain Zero skew (ideally impossible).
Selecting a set of particular buffers and inverter's plays a very important role, which decides the
performance of design.

If clock buffers are not selected correctly they may cause the clock pulse width to degrade as the clock propagates
through them.
CTS Goals

Meet the clock tree DRC

Max. Transition
Max. Capacitance
Max. Fan out
Meet the clock tree targets
Minimal skew
Minimum insertion delay

Q2. What are the main concerns for clock design?

1.Skew
Skew is very first concern for clock networks.
For increased clock frequency.

2. Power

Power is also a very important concern, as clock is a major power consumer.

 It switches at every clock cycle.

3. Noise
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Clock is often a very strong aggressor.

May need shielding, double/triple spacing to avoid noise susceptibility.

4. Delay
5. Electromigration

Clock nets may cause Electromigration issue.

Q3. Why clock nets are given priority above other signal nets?

Since a significant fraction of power is consumed by clock network. In the design almost 50% of total
dynamic power is contributed by clock network.
It is intuitive since these buffers have highest toggle rate.
We have lots of clock buffers in the design.
All clock buffers we use are of high drive strengths.
Also, registers which are clocked dissipate some dynamic power even when input data is not changing.

Because all of above reasons, clock nets becomes more sensitive towards crosstalk and noise than normal signal
nets. Clock network works as central processing unit for the design and we need to provide a more robust clock
network to avoid noise crosstalk issues which may lead to unnecessary post CTS violations and in later route stage
(setup and hold time). So we do clock routing before signal routing.

Q4. What is local skew and global skew?

Clock skew is the difference in clock arrival times at the different end points of the clock tree.
Local skew is the difference in the arrival of clock signal at the clock pin of related flops, which are
directly communicating to each other.
Global skew is the difference in the arrival of clock signal at the clock pin of non-related flops, which are
not communicating directly.

Skew can be positive or negative.

Positive Skew: When data and clock are routed in same direction then it is Positive skew i.e. If capture
clock comes late than launch clock. It can lead to hold violation but improves setup time.
Negative Skew: When data and clock are routed in opposite direction then it is negative skew. i.e. if
capture clock comes early than launch clock. It can lead to setup violation but improves hold time.

Q5. Where a clock is defined?

A clock is defined inside SDC file (Synopsys Design Constraint) provided by synthesis team.

Q6. How to define a clock?

Period
Clock source
Duty Cycle
Edge timing
Create_clock –name CLK –period 40 –waveform {0 10} [get_ports CLK]

Q7. What are virtual clocks?

 A virtual clock is a clock that exists but is not associated with any pin or port of the design.
 Physical
It is usedDesign STA in STA
as a reference Frontend Design
analysis to specifyDFT Verification
input and output delays CMOS
relativeBasics
to clock. Linux Basics
A virtual clock can be defined with no specification of the source port or pin.
Virtual clock are required to constraint the input port to register timing path and register to output port
timing path.
Advantage of virtual clock is we can specify the desired latency.

Q8. What are generated clocks?

A generated clock is a clock derived from a master clock by a circuit within the design itself, such as a
clock divider.These are divider/multiplier clocks which get generated from a master clock. Mostly these
are defined at the output of a clock divider like flip flop or mux. When we define a generated clock, its
source clock, the generation point, division ratio and uncertainty value should be provided.
Generated clocks can be also defined at any point, if we need to define some exception with respect to
this clock.

Q9. In which stage will you find the clock gating violations? Why in that stage?

Post CTS stage because before CTS we have ideal clock (with zero insertion delay and skew) so we
cannot have real results. During CTS stage only various clock cells comes into picture and their related
checks too. skew control between the clock gated and no clock gated cells is difficult. Clock gated path
takes more path delay compared to no clock gated path.
After CTS only we will have results with respect to real clock. Clock gating cells type depends on the
positive edge or negative edge triggered flip flop.

Q10. Drawbacks of clock gating technique.

You could get some glitches in the gated clock if clock gating was not done properly.
Skew balancing. In fact gated and not gated circuits are not clocked at the same time because of the
delay overhead introduced by the circuit responsible of gating the clock.
Area increased.

Q11. Can we have latency or insertion delay more than clock period?

No because the data will be missed without capturing.

Q12. What are the inputs given while CTS?

CTS inputs:

placement database
SDC, TLU+,.tf files
CTS constraint
 Clock Spec file: list of clock buffers/inverters, CTS root pin, Max Skew, Max/Min Delay, Sink Max Tran/
Buff Max Tran.
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Clock tree exceptions through which we can control clock tree tracing or excluding particular pins
explicitly. Like LeafPin/Port, ExcludePin/Port, ThroughPin/Port, preservePin.
NDR’s :( Non Default Rules)
Double Width
Double Spacing
Shielding nets.
Delay Variation and OCV.

Q13. Why clock buffers and inverters should have equal rise and fall time?

To maintain minimum clock pulse width.

To have timing margin for the both negative and positive edge triggered flip flops i.e for half cycle path.
To make equal rise and fall time in a clock buffer we make PMOS width nearly 2.5 times the width of
NMOS. Hence it consumes more power.
Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output with
50% duty cycle.

Q14. Why scan reordering is necessary?

Power consumption can be decreased.

To save routing resources.
It provides timing closure for set up time.

Q15. What are the changes between the pre CTS and post CTS?

Clock propagation
Uncertainty values
IO delays
Disable timing constraints, False paths if timing violations occurs.

Q16. How to decrease the clock skew and insertion delay?

For Latency:

Use the minimum clock level with balanced clock branches.

Use high drive strength cells.
Use Inverters instead buffers.
For Skew:
Balance clock tree by cloning
By synthesizing the separate clock tree for the generated clocks.
Widen the wire.
Mix of drive strength cells.

Q17. What are the NDR used for the clock tree?

Double spacing
Double width
Net shielding
Q18. Will you use the buffers or inverters for CTS and why?
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It depends on design requirement.After a series of experiments with different combinations of buffers and
inverters we can decide. In some cases we prefer mix of both buffer and inverter or only inverters in
another case. But if we have to select one among the two,answer will be inverter, because of below
properties of inverter than buffer.
Less area
Less power (dynamic as well as leakage current)
Less prone to OCV (process variation) due to less number transistors
High drive strength
Less delay, skew reduction because on less insertion delay because of the less inverter delay compared
to buffer delay.

Q19. Which metal did you use for the clock tree routing?

Next lower layer to the top two metal layers (global routing layers).
Because it has less resistance hence less RC delay.

Q20. What is OCV? How you control the OCV in clock paths?

OCV stands for on chip variation. Due to difference in PVT conditions (Process, Voltage, and
Temperature) for different devices at different locations over same die cause performance differences
which leads to OCV.
So required derating is applied to overcome this effect, by adding derating factor during skew
calculations.

Transistors located in close proximity on the same chip exhibit variation in their characteristics due to random
manufacturing variations in:

The number and location of doping atom.

The length and width of the transistor channel
The thickness of oxide layers across the die
Fix:
Try to have the more common path than individual path from the divergence clock tree point. So that
CPPR/CRPR will decrease the OCV effect.

Q21. Why are we not checking the hold before CTS?

Set up violations are checked before CTS, while hold violations are checked after CTS because positive
clock skew helps setup. So if setup is cleared before CTS with an estimated skew, then mostly setup will
be clear with the actual value of skew calculated after CTS.
However in hold analysis skew increases the minimum logic delay required in the path. Since its work
against hold, hold analysis is performed after CTS when an accurate value of skew is known.
Fixing hold is easy compared to set up. Cell density may increases if we keep fixing from pre CTS stage
itself.

Click here for more detail about CTS.

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