ECE- SEMICONDUCTOR CHIP DESIGN AND TESTING
CEC370 LOW POWER IC DESIGN LT PC
2 02 3
COURSE OBJECTIVES:
• To learn the fundamentals of low power low voltage VLSI design.
• To understand the impact of power on system performances.
• To understand the different design approaches.
• To develop the low power low voltage memories
UNIT I FUNDAMENTALS OF LOW POWER CIRCUITS 6
Need for Low Power Circuit Design, Sources of Power Dissipation – Switching Power Dissipation, Short
Circuit Power Dissipation, Leakage Power Dissipation, Glitching Power Dissipation, Short Channel Effects –
Drain Induced Barrier Lowering and Punch Through, Surface Scattering, Velocity Saturation, Impact
Ionization, Hot Electron Effect.
UNIT II LOW-POWER DESIGN APPROACHES 6
Low-Power Design through Voltage Scaling: VTCMOS circuits, MTCMOS circuits, Architectural Level
Approach –Pipelining and Parallel Processing Approaches. Switched Capacitance Minimization
Approaches: System Level Measures, Circuit Level Measures, Mask level Measures.
UNIT III LOW-VOLTAGE LOW-POWER ADDERS 6
Introduction, Standard Adder Cells, CMOS Adder’s Architectures – Ripple Carry Adders, Carry Look-Ahead
Adders, Carry Select Adders, Carry Save Adders, LowVoltage Low Power Design Techniques –Trends of
Technology and Power Supply Voltage, LowVoltage Low-Power Logic Styles.
UNIT IV LOW-VOLTAGE LOW-POWER MULTIPLIERS 6
Introduction, Overview of Multiplication, Types of Multiplier Architectures, Braun Multiplier, Baugh-Wooley
Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier
UNIT V LOW-VOLTAGE LOW-POWER MEMORIES 6
Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM,
Memory Cell, Precharge and Equalization Circuit, LowPower SRAM Technologies, Basics of DRAM, Self-
Refres Circuit, Future Trend and Development of DRAM.
30 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Modeling and sources of power consumption
2. Power estimation at different design levels (mainly circuit, transistor, and gate)
3. Power optimization for combinational circuits
[Link] optimization for sequential circuits
[Link] optimization for RT and algorithmic levels.
TOTAL:60 PERIODS
COURSE OUTCOMES:
Upon successful completion of the course the student will be able to
CO1: Understand the fundamentals of Low power circuit design.
CO2: Attain the knowledge of architectural approaches.
CO3: Analyze and design Low-Voltage Low-Power combinational circuits.
CO4: Learn the design of Low-Voltage Low-Power Memories
CO5: Design and develop Low Power, Low Voltage Circuits
TEXT BOOKS:
1. Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits – Analysis and Design”, TMH,
2011.
2. Kiat-Seng Yeo, Kaushik Roy, “Low-Voltage, Low-Power VLSI Subsystems”, TMH Professional
Engineering, 2004.
REFERENCES
1. Ming-BO Lin, “Introduction to VLSI Systems: A Logic, Circuit and System Perspective”, CRC Press,
2012.
2. Anantha Chandrakasan, “Low Power CMOS Design”, IEEE Press, /Wiley International, 1998
3. Kaushik Roy, Sharat C. Prasad, “Low Power CMOS VLSI Circuit Design”, John Wiley, & Sons,
2000.
4. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Press, 2002
5. Bellamour, M. I. Elamasri, “Low Power CMOS VLSI Circuit Design”, A Kluwer Academic Press,
1995.
6. Siva G. Narendran, Anatha Chandrakasan, “Leakage in Nanometer CMOS Technologies”, Springer,
2005
CO’s-PO’s & PSO’s MAPPING
C PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO PSO
O 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3
1 3 3 2 3 2 - - - - - - 2 2 2 2
2 3 2 1 2 3 - - - - - 1 2 2 1
3 3 3 3 2 2 - - - - - - 1 2 2 2
4 2 3 3 3 3 - - - - - 1 2 3 3
5 3 3 3 2 2 - - - - - - 2 2 2 3
C -
2.8 2.8 2.4 2.4 2.4 - - - - 1.8 2 2 2
O
1 - low, 2 - medium, 3 - high, ‘-' - no correlation
