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FPGA Mini Project

This document describes a project to design a digital system that calculates the factorial of a given number using Verilog and tests it using Xilinx Vivado and ModelSim simulation tools. The project involves writing Verilog code for a module that takes a number input and outputs its factorial. The code is synthesized using Vivado and simulated using ModelSim to verify correctness before being implemented on an FPGA board. The project demonstrates applying digital design concepts and FPGA technology to accelerate mathematical calculations compared to a software approach.

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298 views3 pages

FPGA Mini Project

This document describes a project to design a digital system that calculates the factorial of a given number using Verilog and tests it using Xilinx Vivado and ModelSim simulation tools. The project involves writing Verilog code for a module that takes a number input and outputs its factorial. The code is synthesized using Vivado and simulated using ModelSim to verify correctness before being implemented on an FPGA board. The project demonstrates applying digital design concepts and FPGA technology to accelerate mathematical calculations compared to a software approach.

Uploaded by

xajanam42
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Mini Project Report

Finding the Factorial of a Number using


Verilog with Xilinx and ModelSim

Abstract
The project's aim is to design and implement a digital system to calculate the factorial of a
given number using Verilog, a hardware description language, and validate it using Xilinx
Vivado and ModelSim simulation tools. The project highlights the application of digital
design concepts in solving mathematical problems. It provides a hands-on experience in
FPGA design and simulation.

Introduction
Calculating the factorial of a number is a common mathematical operation that involves
multiplying a given number by all positive integers less than or equal to it. This project
presents a hardware-based approach to calculate factorials using Verilog for digital logic
design and simulation tools such as Xilinx Vivado and ModelSim.

Software Required
 Xilinx ISE 7.1i
 ModelSim-Altera 6.4a

Methodology
The project can be divided into the following key steps:

1. Verilog Design
Design the Verilog module for calculating the factorial of a number. This module will take an
input value (the number for which the factorial is to be calculated) and provide the factorial
as an output. The design will consist of registers, adders, and multipliers to perform the
necessary arithmetic operations.

VERILOG CODE

module factorial(fact,n);
output [31:0]fact;
input [2:0]n;
reg [31:0]fact;
integer i;
always@(n)
begin
fact=1;
i=0;
while(i<n)
begin
i=i+1;
fact=i*fact;
$display("fact =%d",fact);
end
end
endmodule

2. Synthesis using Xilinx Vivado


After verifying the design in simulation, proceed to synthesize the Verilog code using Xilinx
Vivado. Synthesis is the process of converting the high-level description into a gate-level
netlist that can be loaded onto an FPGA.

3. Simulation using ModelSim


Simulate the Verilog design using ModelSim to verify its correctness. This involves creating
test benches with various test cases, including positive and edge cases, to ensure that the
factorial calculator works as expected.
4. Implementation on FPGA
Once the synthesis is successful, load the design onto a Xilinx FPGA. Connect the input and
output interfaces to the FPGA board, and then run the design to calculate factorials in real-
time.

Results and Discussion


The project aims to successfully calculate the factorial of a given number using hardware
acceleration and FPGA technology. After the implementation, the system can calculate
factorials much faster than a software-based approach.

The simulation results from ModelSim provide confidence in the correctness of the Verilog
design, while the implementation on the FPGA board allows real-time factorial calculations.

Conclusion
This project demonstrates the application of Verilog, Xilinx Vivado, and ModelSim in
designing and implementing a factorial calculator. The integration of digital logic design and
FPGA technology has enabled faster and efficient factorial calculations. Such hardware-
based approaches can be extended to optimize other mathematical operations and
computational tasks.

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