Course code 19EC314L Semester VI

Category Professional core course(PCC) L T P C

Course Title VLSI DESIGN LAB 0 0 2 1
COURSE OBJECTIVE
● To expose the fundamental principles of VLSI design in analog and digital circuits.
● To develop familiarity and confidence with designing, building and testing digital
circuits, using CAD tools.
● To familiarize fusing of logical modules on FPGAs.
● To understand the different performance parameters of the circuit.
PREREQUISITE
● Principles of Digital Electronics
● Basic Programming Skills
COURSE OUTCOMES
At the end of the course students will be able to
CO. No. Course Outcome
Blooms
level
CO 1 Write Verilog Hardware Description Language for Combinational
and Sequential Logic Circuits
C2
CO 2 Design and simulate combinational and sequential logic circuits C3
CO 3 Synthesize Place and Route the digital IPs C3
CO 4 Design and Import the logic modules into FPGA Boards C3
CO 5
To construct the layout and extract the SPICE code of Analog
/Digital circuits using EDA tools
C3
Part I: Digital System Design using HDL & FPGA

1. Design a 4 Bit Adder using HDL. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
2. Design a 4 Bit Multiplier using HDL. Simulate it using Xilinx/Altera Software and
Implement by Xilinx/Altera FPGA
3. Design a Counter using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
4. Design a Register -SISO, SIPO, PISO, PIPO and USR using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
5. Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
6. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA Compare pre-synthesis and post synthesis simulation for experiments 1 to 5.

Requirements: Xilinx ISE/Altera Quartus/ equivalent EDA Tools along with

Xilinx/Altera/equivalent FPGA Boards
Part-II Analog and Digital Circuit Design using Tanner
7. Design and simulate a CMOS inverter using digital flow
8. Design and simulate a CMOS Basic Gates & Flip-Flops
9. Design and simulate simple 5 transistor differential amplifier
.

TOTAL: 45 PERIODS

TOTAL :60 PERIODS

OUTCOMES:
At the end of the course, the student should be able to:
 Write HDL code for basic as well as advanced digital integratedcircuit
 Import the logic modules into FPGABoards
 Synthesize Place and Route the digitalIPs
 Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDA
tools

LIST OF EQUIPMENTS FOR A BATCH OF 30 STUDENTS

S.NO EQUIPMENT REQUIRED

Xilinx ISE/Altera Quartus/ equivalent
1 EDA Tools 10 User License

2 Xilinx/Altera/equivalent FPGA Boards 10 no

Cadence/Synopsis/ Mentor
3 10 User License
Graphics/Tanner/equivalent EDA Tools

4 Personal Computer 30 no
 LIST OF EXPERIMENTS

1. Study of simulation and FPGA implementation of Xilinxtool

2. Design & FPGA Implementation of 4-bit ripple carry adder

3. Design & FPGA Implementation of 4-bit Multiplier

4. Design & FPGA Implementation of 4-bit Counter
5. Design & FPGA Implementation of Register-SISO, PISO, SIPO, PIPO and USR

6. Design & FPGA Implementation of ALU

7. Design & FPGA Implementation of Memories

8. Design of CMOS INVERTER usingTanner

9. Design of CMOS NAND AND NOR usingTanner

10. Design of DIFFERENTIAL AMPLIFIER usingTanner

Content Beyond Syllabus

11. Design and Analysis of KOGGE STONE ADDER using Tanner

 STUDY OF SIMULATION AND IMPLEMENTATION OF
XILINXTOOL
AIM:

To study the simulation and implementation procedures of Xilinx tool and FPGA

STEP1:

Click Xilinx ISE9.1

STEP2:

File ->New project and type the project name and check the top level source type as HDL

STEP3: Check the device properties and click Next

STEP4:Click New Source And Select the Verilog Module and then give the file name

STEP5:

Select the Input,Output port names and click finish.

STEP6:

Type the program and save it

STEP7: Check the synthesize XST and check syntax

STEP8: Select user constraints->assign package pins,setport numbers and save it then select IO
Bus delimiter as XST default<>->clickok

STEP9:

Double click implement design and click generate programming file-

>configure device(impact)->finish then select bit file
STEP10:

Right click on the xc3s400 figure->program->filename then click

finish andFinally check the functionality inhardware

Result:

Thus the simulation and implementation procedure of Xilinx and FPGA is studied
 Design & FPGA Implementation of 4-bit ripple carry adder
Ex.No.1
AIM:
To write a verilog program
a) To simulate a ripple carry adder and verify the code using test bench.
b) To synthesis a ripple carry adder and verify the code
c) To implement a ripple carry adder and verify the code

APPARATUS REQUIRED:

 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

PROGRAM
adder_8bit.v

module rca_4( a, b, cin , sum, cout);

input [3:0] a;
input [3:0] b;
input cin;
output [3:0] sum;
output cout;
wire c1,c2,c3;
rca_1 a1 ( a[0] , b[0] , cin , sum[0] , c1);
rca_1 a2 ( a[1] , b[1] , c1 , sum[1] , c2);
rca_1 a3 ( a[2] , b[2] , c2 , sum[2] , c3);
rca_1 a4( a[7] , b[7] , c7 , sum[3] , cout);
endmodule
adder_1bit.v
module rca_1 ( a , b, cin , sum, cout );
input a , b , cin;
output sum, cout;
assign sum = a ^ b ^cin;
assign cout = (a & b) | (b &cin) | (cin& a);
endmodule
test_adder.v
// test bench for 4-bit adder
module test_adder;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire [3:0] cout;

rca_8 dut( a, b, cin , sum, cout);

initial begin
a = 4'b0000;
b = 4'b0000;
cin = 1'b0;
#10 a = 4'b1111 ; b = 4'b0000; cin = 1'b1;
#20 a = 4'b1100; b = 4'b0111; cin = 1'b1;
#30 a = 4'b0111; b = 4'b1100; cin = 1'b0;
#200 $finish;
end
endmodule

Simulation Results:

Figure 1: Simulation Results of RCA

Synthesis Results:

Figure 1: RTL Technology Schematic for RCA

Implementation Results:

Figure 1: Implementation Results for RCA

RESULT:

Thus the verilog program is written to simulate and synthesis an 4 bit adder circuits and
implementation of a ripple carry adder was also obtained.
 Design & FPGA Implementation of 4-bit Multiplier
Ex.No.2
AIM:
To write a verilog program
a) To simulate a 4-bit multiplier.
b) To Synthesis
c) To implement
APPARATUS REQUIRED:

 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

Block Diagram

Program
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule

Simulation results:

Figure 1: Simulation results of Multiplier

Synthesis results:

Figure 1: RTL Schematic results of Multiplier

 Figure 2: RTL Technology Schematic results of Multiplier

Implementation results:

Figure 1: Implementation results of Multiplier

 Figure 2: Implementation results of Multiplier

RESULT:

Thus the verilog program is written to implement, synthesis a 4-bit multiplier and implementation
was obtained, and also the code was verified using test bench.
 Design & FPGA Implementation of COUNTER
Ex.No : 3

AIM:
To write a verilog program to implement an Up, Down & UP-Down counter.
APPARATUS REQUIRED:
 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

PROGRAM
UP-Counter

module up_count (out, enable, clk, reset);

output [7:0] out;
input enable, clk, reset;
reg [7:0] out;
always @(posedge clk)
begin
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
end

endmodule
Test bench for up counter
module test_upcounter;
reg clk, reset,enable ;
wire [7:0] out;

up_countdut (out, enable, clk ,reset);

initial begin
clk = 0;
forever # clk = ~ clk;
end
end
initial begin
reset = 1;
#20
reset = 0;enable = 1;
#100
enable = 0;
#150
reset = 0;
end
endmodule

Simulation results of up counter

 Synthesis results RTL Schematic

Synthesis results of Technology Schematic

Down-Counter

module down_count (out, enable, clk, reset);

output [7:0] out;
input enable, clk, reset;
reg [7:0] out;
always @(posedge clk)
begin
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out - 1;
end
end
endmodule

Test bench for Down counter

module test_downcounter;
reg clk, reset,enable ;
wire [7:0] out;

down_count dut1 (out, enable, clk ,reset);

initial begin
clk = 0;
forever # clk = ~ clk;
end
end
initial begin
reset = 1;
#20
reset = 0;enable = 1;
#100
enable = 0;
#150
reset = 0;
end
endmodule
Simulation Results of Down counter

Synthesis results of RTL Schematic

 Synthesis results of Technology Schematic

UP-Down -Counter

module up-down (out, ud, clk, reset);

output [7:0] out;
input clk, reset;
input ud;
reg [7:0] out;
always @(posedge clk)

begin
if (reset) begin
out <= 8'b0 ;
end else if (ud) begin
out <= out + 1;
end else begin
out <= out -1;
end
end
endmodule

Test bench for up_down counter

module test_updown;
wire [7:0] out;
reg clk, reset;
reg [7:0] data;

up-down dut3 (out, enable, clk ,reset);

initial begin
clk = 0;
forever # clk = ~ clk;
end
end
initial begin
reset = 1;
#20
reset = 0; up_down = 1;
#75
up_down = 0;
#150
reset = 0;
end
endmodule

Simulation results of updown counter

 Synthesis results of RTL Schematic

Synthesis results of Technology schematic

RESULT:

Thus the verilog program is written and simulation, synthesis and implementation of counter is obtained.
 Design & FPGA Implementation of REGISTER
Ex.No : 4

AIM:
To write a verilog program to implement SISO, SIPO, PISO, PIPO & USR
APPARATUS REQUIRED:
 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

PROGRAM
SISO

PROGRAM
module dff(d,clk,q);
input d,clk;
output q;
reg q=0;
always @ (posedge clk)
begin
q<=d;
end
endmodule

module siso(d, clk, q);

input d,clk;
output q;
wire q1,q2,q3;
dff a(d, clk, q1);
dff b(q1, clk, q2);
dff c(q2, clk, q3);
dff d1(q3, clk, q);
endmodule
TEST BENCH

module testbench()
reg d,clk;
wire q;
siso a(d, clk, q);
initial
begin
$monitor($time,"d=%b,clk=%b,q=%b",d,clk,q);
end
initial
begin
clk=1'b0;
forever #5 clk=~clk;
end
initial
begin
d=1;
#10 d=0;
#10 d=1;
#10 d=1;
#40 $finish;
end
endmodule
 Simulation Results of SISO

Synthesis results of SISO RTL Schematic

Synthesis results of SISO Technology Schematic

SIPO

PROGRAM:
module ShiftRegister_SIPO(C, SI, PO);
input C,SI;
output [7:0] PO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = {tmp[6:0], SI};
end
assign PO = tmp;
endmodule
 Simulation results of SIPO

Synthesis results of SIPO RTL Schematic

Synthesis results of SIPO Technology schematic

PISO

PROGRAM
module piso(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
begin
q<=1'b0;
temp<=a;
end
else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule
TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1; a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial
#1000 $stop;
endmodule

Simulation results of PISO

Synthesis results of PISO RTL Schematic

Synthesis results of PISO Technology Schematic
PIPO

PROGRAM
module pipomod(clk,clear, pi, po);
input clk,clear;
input [3:0] pi;
output [3:0] po;
wire [3:0] pi;
reg [3:0] po;
always @(posedge clk)
begin
if (clear)
po<= 4’b0000;
else
 po <= pi;
end
endmodule
 
TEST BENCH
module pipot_v;
reg clk;
reg clear;
reg [3:0] pi;
wire [3:0] po;
pipomoduut(.clk(clk),.clear(clear),.pi(pi),.po(po) );
 initial begin
clk = 0;
clear = 0;
pi = 0;
#5 clear=1’b1;
#5 clear=1’b0;
#10 pi=4’b1001;
#10 pi=4’b1010;
#10 pi=4’b1011;
#10 pi=4’b1110;
#10 pi=4’b1111;
#10 pi=4’b0000;
end
always #5 clk = ~clk;
initial #150 $stop;
endmodule
 Simulation Results of PIPO

Synthesis results of PIPO RTL Schematic

 Synthesis results of PIPO Technology Schematic

UNIVERSAL SHIFT REGISTER

module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
output reg [7:0] op;
input load;
input [1:0] sh_ro_lt_rt;
input [7:0] ip;
input clk, rst_a;
reg [7:0]temp;
always @(posedge clk or posedgerst_a)
begin
if (rst_a)
op = 0;
else
case(load)
1'b1:
begin //Load Input
temp = ip;
end
 1'b0: //Operation
case (sh_ro_lt_rt)
2'b00: op = temp<<1; //Left Shift
2'b01: op = temp>>1; //Right Shift
2'b10: op = {temp[6:0],temp[7]}; //Rotate Left
2'b11: op = {temp[0], temp[7:1]}; //Rotate Right
default: $display("Invalid Shift Control Input");
endcase

default: $display("Invalid Load Control Input");

endcase
end
endmodule

SYNTHESIS RTL SCHEMATIC

Synthesis Results
RESULT:

Thus the verilog program is written to simulate register, synthesis and implementation also
obtained.
Design & FPGA Implementation of ALU
Ex.No : 5
AIM:
To write a verilog program to simulate ALU, synthesis RTL Schematic , and implement .

APPARATUS REQUIRED:

 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

Program

modulealu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
outputCarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assignALU_Out = ALU_Result; // ALU out
assigntmp = {1'b0,A} + {1'b0,B};
assignCarryOut = tmp[8]; // Carryout flag
always@(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A&B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logicalxor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A&B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule

Testbench Verilog code for the ALU:

moduletb_alu;
//Inputs
reg[7:0] A,B;
reg[3:0] ALU_Sel;
//Outputs
wire[7:0] ALU_Out;
wireCarryOut;
// Verilog code for ALU
integeri;
alutest_unit(
A,B, // ALU 8-bit Inputs
ALU_Sel,// ALU Selection
ALU_Out, // ALU 8-bit Output
CarryOut // Carry Out Flag
);
initialbegin
// hold reset state for 100 ns.
A = 8'h0A;
B = 4'h02;
ALU_Sel = 4'h0;
for (i=0;i<=15;i=i+1)
begin
ALU_Sel = ALU_Sel + 8'h01;
#10;
end;

A = 8'hF6;
B = 8'h0A;
end
endmodule

Simulation result:

SYNTHESIS RTL SCHEMATIC

RESULT:

Thus the verilog program is written to simulate, synthesis ALU and implementation also obtained.
 Design & FPGA Implementation of Memories

Ex.No:6

Aim: To compile and to simulate the Verilog code for the successive approximation
register.
APPARATUS REQUIRED:

 PC with WindowsXP.
 XILINX9.2i
 FPGA-SPARTAN-3KIT
 PARALLEL TO JTAGCABLE

PROGRAM
module mem_ram_sync(
clk,
rst,
read_rq,
write_rq,
rw_address,
write_data,
read_data
);
input clk;
input rst;
input read_rq;
input write_rq;
input[5:0] rw_address;
input[7:0] write_data;
output[7:0] read_data;

reg[7:0] read_data;

integer i;

// Declare memory 64x8 bits = 512 bits or 64 bytes

reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];

// Use positive edge of clock to read the memory

// Implement cyclic shift right
always @(posedge clk or
negedge rst)
begin
 if (!rst)
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= 0;
end
else
begin
for (i=0;i<64; i=i+1)
memory_ram_q[i] <= memory_ram_d[i];
end
end

always @(*)
begin
for (i=0;i<64; i=i+1)
memory_ram_d[i] = memory_ram_q[i];
if (write_rq&& !read_rq)
memory_ram_d[rw_address] = write_data;
if (!write_rq&&read_rq)
read_data = memory_ram_q[rw_address];
end
endmodule

Simulation results of Memories

 Synthesis results of Memories RTL Schematic

Synthesis results of Memories Technology Schematic

RESULT:

Thus the verilog program is written to simulate, synthesis Memories and implementation also obtained.
 PART-II

Ex.No. 7
DESIGN OF CMOS INVERTER USING TANNER
AIM
To design a CMOS inverter using the Schematic entry tool, Tanner
and verify itsfunctioning.

Apparatus Required
1. Tannertool
2. PC

THEORY

CMOS Inverter consists of nMOSand pMOStransistor in series connectedbetween VDD

and GND. The gate of the twotransistors are shorted and connected to the input. When the
input to the inverter A = 0, nMOStransistor isOFF and pMOStransistor is ON. The output is
pull-up toVDD. When the inputA = 1, nMOStransistor is ON and pMOStransistor is OFF. The
Output is Pull-down toGND.

Algorithm
1. Draw the schematic of CMOS Inverter usingS-edit.

2. Perform Transient Analysis of the CMOSInverter.

3. Obtain the output waveform fromW-edit.

4. Obtain the spice code usingT-edit.

CMOS Inverter
 ]
WAVEFORM

Transient Analysis

Dc analysis
OUTPUT

TSPICE - Tanner SPICE

Version7.10
Copyright (c) 1993-2001 Tanner Research,

Inc. Parsing "C:\Tanner\S-Edit\Module011.sp"

Including "C:\Tanner\TSpice70\models\

ml2_125.md" Device and node counts:

MOSFETs - 2 BJTs - 0 MESFETs - 0 Capacitors - Inductors - 0

MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors
- 0 Voltage
sources - 2 VCVS
-0
CCVS -0
V-control switch -
0 Macro devices -
0 Subcircuits - 0
Independent
nodes - 1 Total
nodes - 4

Current sources

- 0 VCCS -0

CCCS -0

I- control switch -0

Functional model instances

- 0 Subcircuit instances - 0

Boundary nodes - 3

Parsing 0.01 seconds

Setup 0.00 seconds

 DCoperating point 0.00

seconds Transient Analysis

0.04seconds

-----------------------------------------

Total 0.05 seconds

RESULTS

Thus the design & simulation of a CMOS inverter has been carried out using S-Edit of
Tanner EDA Tools.
Ex.no :8 DESIGN OF CMOS NAND GATE AND NOR GATE USING TANNER
AIM

To design a CMOS NAND and NOR gates using the Schematic entry tool,
Tannerand verify itsfunctioning.
Apparatus Required

1. Tannertool
2. PC

Theory

NAND and NOR gates are known as universal gates as anyfunction can be implemented
withthem

NAND functionality can be implemented by parallel combination of PMOS and series

combination of NMOS transistor. When any one of the inputs iszero, then the output will be
one and when both the inputs are one the output will below.

NOR functionality can be implemented by parallel combination of NMOS and series

combination of PMOS transistor. When any one of the inputs is one, then the output will be
one and when both the inputs are zero the output will below.

Algorithm

CMOS NAND

1. Draw the schematic of CMOS NAND usingS-edit.

2. Perform Transient Analysis of the CMOSNAND.
3. Obtain the output waveform fromW-edit.
4. Obtain the spice code usingT-edit.

CMOS NOR

1. Draw the schematic of CMOS NOR usingS-edit.

2. Perform Transient Analysis of the CMOSNOR.
3. Obtain the output waveform fromW-edit.
4. Obtain the spice code usingT-edit.
CMOS NAND Ciruit:

WAVEFORM NAND
OUTPUT - NAND

TSPICE - Tanner SPICE

Version7.10

Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "F:\tanner\TSpice70\Module0.sp"

Including "F:\tanner\S-Edit\models\

ml2_125.md"

Warning T-SPICE : DC sources have non-unique names. "vin".

Device and node counts:

MOSFETs - 4 MOSFET geometries -
2 BJTs-0 JFETs -0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors-0 Mutual inductors
-0
Transmission lines - 0 Coupled transmission lines -
0 Voltage sources-3 Current sources -0
VCVS-0 VCCS -0
CCVS-0 CCCS -0
V-control switch-0 I-control switch -0
Macro devices-0 Functional model instances -
0 Subcircuits - 0 Subcircuit instances -0
Independent nodes - 2 Boundary nodes - 4
Total nodes - 6

*** 1 WARNING MESSAGES GENERATED

Parsing 0.00 seconds

Setup 0.00 seconds
DCoperating point 0.01
seconds Transient Analysis

0.03seconds
-----------------------------------------
Total 0.04 seconds
 CMOS NOR Circuit

OUTPUT – NOR

TSPICE - Tanner SPICE

Version7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "F:\tanner\TSpice70\Module0.sp"
Including "F:\tanner\S-Edit\models\
ml2_125.md"
Warning T-SPICE : DC sources have non-unique names. "vin".

Device and node counts:

MOSFETs - 4 MOSFET geometries -
2 BJTs-0 JFETs -0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors-0 Mutual
inductors -0
Transmission lines - 0 Coupled transmission lines -
0 Voltage sources-3 Current sources -0
VCVS-0 VCCS -0
CCVS-0 CCCS -0
V- control switch-0 I-control switch -0
Macro devices-0 Functional model instances -
0 Subcircuits - 0 Subcircuit instances -0
Independent nodes - 3 Boundary nodes - 4
Total nodes - 7
 *** 1 WARNING MESSAGES GENERATED

Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.

Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been
exceeded.

Warning T-SPICE : The vrange voltage range limit should be set to at least 7.11984 for best
accuracy and performance.

Parsing 0.00 seconds

Setup 0.01 seconds
DCoperating point 0.00
seconds Transient Analysis

0.06seconds
-----------------------------------------
Total 0.07 seconds

Results
Thus the design &simulation of a CMOS NAND and NOR gates have been carried
out using S-Edit of Tanner EDATools

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50
 DIFFERENTIAL AMPLIFIER
Ex.No.9
AIM:
To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic entry.
APPARATUS REQUIRED:
S-Edit using Tanner Tool.
Theory :
A differential amplifier is a type of electronic amplifier that multiplies the difference between two inputs by
some constant factor (the differential gain).
Many electronic devices use differential amplifiers internally. The output of an ideal differential amplifier is
given by:

Where   and   are the input voltages and Ad is the differential gain.
In practice, however, the gain is not quite equal for the two inputs. This means that if   and   are equal,
the output will not be zero, as it would be in the ideal case. A more realistic expression for the output of a
differential amplifier thus includes a second term.

Ac is called the common-mode gain of the amplifier.

As differential amplifiers are often used when it is desired to null out noise or bias-voltages that appear at
both inputs, a low common-mode gain is usually considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-mode gain and common-
mode gain, indicates the ability of the amplifier to accurately cancel voltages that are common to both inputs.
Common-mode rejection ratio (CMRR):

PROCEDURE
1. Draw the schematic of differential amplifier using S-edit and generate the symbol
2. Draw the schematic of differential amplifier circuit using the generated symbol.
3. Perform AC Analysis of the differential amplifier.
4. Obtain the frequency response from W-edit.
5. Obtain the spice code using T-edit.

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51
RESULT:
The gain, bandwidth of the differential amplifier was obtained using AC analysis.

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52
 CONTENT BEYOND SYLLABUS
KOGGE STONE ADDER
Ex.No.10
AIM:
To write a verilog program to optimize the results of Kogge Stone Adder.

APPARATUS REQUIRED:
Xilinx ISE Design Suite

Block Diagram:

Inputs

a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 cin

Pre computing

g7 p7 g6 p6 g5 p5 g4 p4 g3 p3 g2 p2 g1 p1 g0 p0

Prefix stage

c6 c5 c4 c3 c2 c1 c0

c7

Final computing

cout s7 s6 s5 s4 s3 s2 s1 s0

Figure 1: Block Diagram of Kogge Stone Adder

Program:

Module normalksa(a0,a1,a2,a3,b0,b1,b2,b3,c0,c1,c2,c3,g0,g1,g2,g3,g11,g21,g31,
g22,g32,p0,p1,p2,p3,p11,p21,p31,p22,p32);
input a0,a1,a2,a3,b0,b1,b2,b3;
output c0,c1,c2,c3,g0,g1,g2,g3,g11,g21,g31, g22,g32,p0,p1,p2,p3,p11,p21,p31,p22,p32;
assign g0=a0&b0;
assign p0=a0^b0;

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53
assign g1=a1&b1;
assign p1=a1^b1;
assign g2=a2&b2;
assign p2=a2^b2;
assign g3=a3&b3;
assign p3=a3^b3;
assign p11=p1&p0;
assign g11=(p1&g0)|g1;
assign p21=p1&p2;
assign g21=(p2&g1)|g2;
assign p31=p3&p2;
assign g31=(p3&g2)|g3;
assign c0=g0;
assign c1=g11;
assign p22=p21&p0;
assign g22=(p21&g0)|g21;
assign p32=p31&p11;
assign g32=(p31&g11)|g31;
assign c2=g22;
assign c3=g32;
endmodule

Output

Figure 2. Simulation Results of Kogge Stone Adder

RESULT:

Thus the verilog program is written to simulate, synthesis Kogge stone adder and implementation also
obtained.

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54