U18ECI6203 -

VLSI & HDL

Programming

Module 1 – Verilog HDL

Part 2 – Lexical conventions

Assistant Professor,
Department of Electronics & Communication Engineering,
Kumaraguru College of Technology.
Contents
• Lexical Conventions
• Data Types
• System Tasks and Compiler Directives

07/28/2023 Verilog HDL 2

Lexical Conventions
• Very similar to C
• Verilog is case-sensitive
• All keywords are in lowercase
• A Verilog program is a string of tokens
• Whitespace
• Comments
• Delimiters
• Numbers
• Strings
• Identifiers
• Keywords

07/28/2023 Verilog HDL 3

Lexical Conventions (cont’d)
• Whitespace • Comments
• Used for readability and
• Blank space (\b)
documentation
• Tab (\t)
• Just like C:
• Newline (\n) • // single line comment
• Whitespace is ignored in • /* multi-line
Verilog except comment
*/
• In strings
/* Nested comments
• When separating tokens /* like this */ may not be
acceptable (depends on
Verilog compiler) */

07/28/2023 Verilog HDL 4

Lexical Conventions (cont’d)
• Operators
• Unary
a = ~b;
• Binary
a = b && c;
• Ternary
a = b ? c : d; // the only ternary operator

07/28/2023 Verilog HDL 5

Lexical Conventions (cont’d)
• Number Specification
• Sized numbers
• Unsized numbers
• Unknown and high-impedance values
• Negative numbers

07/28/2023 Verilog HDL 6

Lexical Conventions (cont’d)
• Sized numbers
• Unsized numbers
• General syntax:
<size>’<base><number> • Default base is decimal
• <size> number of bits (in decimal) • Default size is at least 32
• <number> is the number in radix (depends on Verilog
<base>
• <base> :
compiler)
• d or D for decimal (radix 10) • Examples
• b or B for binary (radix 2) • 23232
• o or O for octal (radix 8)
• ’habc
• h or H for hexadecimal (radix 16)
• ’o234
• Examples:
• 4’b1111
• 12’habc
• 16’d255

07/28/2023 Verilog HDL 7

Lexical Conventions (cont’d)
• X or Z values
• Unknown value: lowercase x
• 4 bits in hex, 3 bits in octal, 1 bit in binary
• High-impedance value: lowercase z
• 4 bits in hex, 3 bits in octal, 1 bit in binary
• Examples
• 12’h13x
• 6’hx
• 32’bz
• Extending the most-significant part
• Applied when <size> is bigger than the specified value
• Filled with x if the specified MSB is x
• Filled with z if the specified MSB is z
• Zero-extended otherwise
• Examples:
• 6’hx

07/28/2023 Verilog HDL 8

Lexical Conventions (cont’d)
• Negative numbers
• Put the sign before the <size>
• Examples:
• -6’d3
• 4’d-2 // illegal
• Two’s complement is used to store the value
• Underscore character and question marks
• Use ‘_’ to improve readability
• 12’b1111_0000_1010
• Not allowed as the first character
• ‘?’ is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz

07/28/2023 Verilog HDL 9

Lexical Conventions (cont’d)
• Strings
• As in C, use double-quotes
• Examples:
• “Hello world!”
• “a / b”
• “text\tcolumn1\bcolumn2\n”
• Identifiers and keywords
• identifiers: alphanumeric characters, ‘_’, and ‘$’
• Should start with an alphabetic character or ‘_’
• Only system tasks can start with ‘$’
• Keywords: identifiers reserved by Verilog
• Examples:
• reg value;
• input clk;

07/28/2023 Verilog HDL 10

Lexical Conventions (cont’d)
• Escaped identifiers
• Start with ‘\’
• End with whitespace (space, tab, newline)
• Can have any printable character between start and end
• The ‘\’ and whitespace are not part of the identifier
• Examples:
• \a+b-c // a+b-c is the identifier
• \**my_name** // **my_name** is the identifier
• Used as name of modules

07/28/2023 Verilog HDL 11

Data Types
• Value set and strengths
• Nets and Registers
• Vectors
• Integer, Real, and Time Register Data Types
• Arrays
• Memories
• Parameters
• Strings

07/28/2023 Verilog HDL 12

Value Set
Value level HW Strength level Type
Condition supply Driving
0 Logic zero, false strong Driving
1 Logic one, true pull Driving
x Unknown large Storage

z High imp., weak Driving

floating medium Storage
small Storage
highz High
Impedance

07/28/2023 Verilog HDL 13

Nets
• Used to represent connections between HW elements
• Values continuously driven on nets
• Keyword: wire
• Default: One-bit values
• unless declared as vectors
• Default value: z
• For trireg, default is x
• Examples
• wire a;
• wire b, c;
• wire d=1’b0;

07/28/2023 Verilog HDL 14

Registers
• Registers represent data storage elements
• Retain value until next assignment
• NOTE: this is not a hardware register or flipflop
• Keyword: reg
• Default value: x
• Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
end

07/28/2023 Verilog HDL 15

Vectors
• Net and register data types can be declared as vectors (multiple
bit widths)
• Syntax:
• wire/reg [msb_index : lsb_index] data_id;
• Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

07/28/2023 Verilog HDL 16

Integer, Real, and Time
Register Data Types
• Integer
• Keyword: integer
• Very similar to a vector of reg
• integer variables are signed numbers
• reg vectors are unsigned numbers
• Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width:
integer [7:0] tmp;
• Examples:
integer counter;
initial
counter = -1;

07/28/2023 Verilog HDL 17

Integer, Real, and Time
Register Data Types (cont’d)
• Real
• Keyword: real
• Values:
• Default value: 0
• Scientific notation: 3e6 (=3x106)

07/28/2023 Verilog HDL 18

Integer, Real, and Time
Register Data Types (cont’d)
• Time
• Used to store values of simulation time
• Keyword: time
• Bit width: implementation-dependent (at least 64)
• $time system function gives current simulation time
• Example:
time save_sim_time;
initial
save_sim_time = $time;

07/28/2023 Verilog HDL 19

Arrays
• Only one-dimensional arrays supported
• Allowed for reg, integer, time
• Not allowed for real data type
• Syntax:
<data_type> <var_name>[start_idx : end_idx];
• Examples:
integer count[0:7];
reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][4:0]; // illegal

count[5]
chk_point[100]
port_id[3]
• Note the difference between vectors and arrays
07/28/2023 Verilog HDL 20
Memories
• RAM, ROM, and register-files used many times in digital systems
• Memory = array of registers in Verilog
• Word = an element of the array
• Can be one or more bits
• Examples:
reg membit[0:1023];
reg [7:0] membyte[0:1023];
membyte[511]
• Note the difference (as in arrays):
reg membit[0:127];
reg [0:127] register;

07/28/2023 Verilog HDL 21

Parameters
• Similar to const in C
• But can be overridden for each module at compile-time
• Syntax:
parameter <const_id>=<value>;
• Gives flexibility
• Allows to customize the module
• Example:
parameter port_id=5;
parameter cache_line_width=256;
parameter bus_width=8;
wire [bus_width-1:0] bus;

07/28/2023 Verilog HDL 22

System Tasks
• System Tasks: standard routine operations provided by Verilog
• Displaying on screen, monitoring values, stopping and finishing
simulation, etc.
• All start with $

07/28/2023 Verilog HDL 23

System Tasks (cont’d)
• $display: displays values of variables, strings, expressions.
• Syntax: $display(p1, p2, p3, …, pn);
• p1,…, pn can be quoted string, variable, or expression
• Adds a new-line after displaying pn by default
• Format specifiers:
• %d, %b, %h, %o: display variable respectively in decimal, binary, hex, octal
• %c, %s: display character, string
• %e, %f, %g: display real variable in scientific, decimal, or whichever smaller notation
• %v: display strength
• %t: display in current time format
• %m: display hierarchical name of this module

07/28/2023 Verilog HDL 24

System Tasks (cont’d)
• $display examples:
• $display(“Hello Verilog World!”);
Output: Hello Verilog World!

• $display($time);
Output: 230

• reg [0:40] virtual_addr;

• $display(“At time %d virtual address is %h”, $time,
virtual_addr);
Output: At time 200 virtual address is 1fe000001c

07/28/2023 Verilog HDL 25

System Tasks (cont’d)
• $monitor: monitors a signal when its value changes
• Syntax: $monitor(p1, p2, p3, …, pn);
• p1,…, pn can be quoted string, variable, or signal names
• Format specifiers just as $display
• Continuously monitors the values of the specified variables or
signals, and displays the entire list whenever any of them changes.
• $monitor needs to be invoked only once (unlike $display)
• Only one $monitor (the latest one) can be active at any time
• $monitoroff to temporarily turn off monitoring
• $monitoron to turn monitoring on again

07/28/2023 Verilog HDL 26

System Tasks (cont’d)
• $monitor Examples:
initial
begin
$monitor($time, “Value of signals clock=%b, reset=
%b”, clock, reset);
end

• Output:
0 value of signals clock=0, reset=1
5 value of signals clock=1, reset=1
10 value of signals clock=0, reset=0

07/28/2023 Verilog HDL 27

System Tasks (cont’d)
• $stop: stops simulation
• Simulation enters interactive mode when reaching a $stop system task
• Most useful for debugging
• $finish: terminates simulation
• Examples:
initial
begin
clock=0;
reset=1;
#100 $stop;
#900 $finish;
end

07/28/2023 Verilog HDL 28

Compiler Directives
• General syntax:
`<keyword>
• `define: similar to #define in C, used to define macros
• `<macro_name> to use the macro defined by `define
• Examples:
`define WORD_SIZE 32
`define S $stop

`define WORD_REG reg [31:0]

`WORD_REG a_32_bit_reg;

07/28/2023 Verilog HDL 29

Compiler Directives (cont’d)
• `include: Similar to #include in C, includes entire contents
of another file in your Verilog source file
• Example:
`include header.v
...
<Verilog code in file design.v>
...

07/28/2023 Verilog HDL 30

Reference book
• Samir Palnitkar, “Verilog HDL – Guide to Digital Design and
Synthesis”, Pearson Education, 3rd Edition, 2003.