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Add vector instructions to RISC-V emitter #16829

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merged 11 commits into from
Jan 22, 2023
Merged

Add vector instructions to RISC-V emitter #16829

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bfd60a6
riscv: Add vector load/store ops.
unknownbrackets Jan 21, 2023
6fa50ea
riscv: Add vector int add/sub and many encodings.
unknownbrackets Jan 22, 2023
b3be901
riscv: Add vector bitwise/compare funcs.
unknownbrackets Jan 22, 2023
6f78f2a
riscv: Add vector integer muliplies.
unknownbrackets Jan 22, 2023
a313e44
riscv: Add vector integer move/broadcast.
unknownbrackets Jan 22, 2023
a1ca291
riscv: Add vector fixed-point arith instructions.
unknownbrackets Jan 22, 2023
f079667
riscv: Add vector float arith/mul funcs.
unknownbrackets Jan 22, 2023
2a7bdbf
riscv: Add vector float move/compare/unary.
unknownbrackets Jan 22, 2023
88de043
riscv: Add vector reduce instructions.
unknownbrackets Jan 22, 2023
c99eb18
riscv: Add vector mask instructions.
unknownbrackets Jan 22, 2023
2aeee83
riscv: Add vector transfer instructions.
unknownbrackets Jan 22, 2023
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riscv: Add vector integer move/broadcast.
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@unknownbrackets
unknownbrackets committed Jan 22, 2023
commit a313e440b49051e2b2e98a63ca67006d3411a983
27 changes: 27 additions & 0 deletions Common/RiscVEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2719,6 +2719,33 @@ void RiscVEmitter::VWMACCUS_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMACCUS));
}

void RiscVEmitter::VMERGE_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask) {
_assert_msg_(vmask == V0, "vmask must be V0");
Write32(EncodeIVV(vd, vs1, vs2, VUseMask::V0_T, Funct6::VMV));
}

void RiscVEmitter::VMERGE_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask) {
_assert_msg_(vmask == V0, "vmask must be V0");
Write32(EncodeIVX(vd, rs1, vs2, VUseMask::V0_T, Funct6::VMV));
}

void RiscVEmitter::VMERGE_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask) {
_assert_msg_(vmask == V0, "vmask must be V0");
Write32(EncodeIVI(vd, simm5, vs2, VUseMask::V0_T, Funct6::VMV));
}

void RiscVEmitter::VMV_VV(RiscVReg vd, RiscVReg vs1) {
Write32(EncodeIVV(vd, vs1, V0, VUseMask::NONE, Funct6::VMV));
}

void RiscVEmitter::VMV_VX(RiscVReg vd, RiscVReg rs1) {
Write32(EncodeIVX(vd, rs1, V0, VUseMask::NONE, Funct6::VMV));
}

void RiscVEmitter::VMV_VI(RiscVReg vd, s8 simm5) {
Write32(EncodeIVI(vd, simm5, V0, VUseMask::NONE, Funct6::VMV));
}

bool RiscVEmitter::AutoCompress() const {
return SupportsCompressed() && autoCompress_;
}
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11 changes: 11 additions & 0 deletions Common/RiscVEmitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -629,6 +629,17 @@ class RiscVEmitter {
// Widening multiply and add - vd(wide) += U(rs1) * S(vs2).
void VWMACCUS_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);

// Masked bits (1) take vs1/rs1/simm5, vmask must be V0.
void VMERGE_VVM(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, RiscVReg vmask);
void VMERGE_VXM(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, RiscVReg vmask);
void VMERGE_VIM(RiscVReg vd, RiscVReg vs2, s8 simm5, RiscVReg vmask);

// Simple register copy, can be used as a hint to internally prepare size if vd == vs1.
void VMV_VV(RiscVReg vd, RiscVReg vs1);
// These broadcast a value to all lanes of vd.
void VMV_VX(RiscVReg vd, RiscVReg rs1);
void VMV_VI(RiscVReg vd, s8 simm5);

// Compressed instructions.
void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);
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