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Add vector instructions to RISC-V emitter #16829

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merged 11 commits into from
Jan 22, 2023
Merged

Add vector instructions to RISC-V emitter #16829

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bfd60a6
riscv: Add vector load/store ops.
unknownbrackets Jan 21, 2023
6fa50ea
riscv: Add vector int add/sub and many encodings.
unknownbrackets Jan 22, 2023
b3be901
riscv: Add vector bitwise/compare funcs.
unknownbrackets Jan 22, 2023
6f78f2a
riscv: Add vector integer muliplies.
unknownbrackets Jan 22, 2023
a313e44
riscv: Add vector integer move/broadcast.
unknownbrackets Jan 22, 2023
a1ca291
riscv: Add vector fixed-point arith instructions.
unknownbrackets Jan 22, 2023
f079667
riscv: Add vector float arith/mul funcs.
unknownbrackets Jan 22, 2023
2a7bdbf
riscv: Add vector float move/compare/unary.
unknownbrackets Jan 22, 2023
88de043
riscv: Add vector reduce instructions.
unknownbrackets Jan 22, 2023
c99eb18
riscv: Add vector mask instructions.
unknownbrackets Jan 22, 2023
2aeee83
riscv: Add vector transfer instructions.
unknownbrackets Jan 22, 2023
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riscv: Add vector integer muliplies.
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@unknownbrackets
unknownbrackets committed Jan 22, 2023
commit 6f78f2a2d241635cf5dd17775327fc2e40bc2911
152 changes: 150 additions & 2 deletions Common/RiscVEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -363,9 +363,9 @@ enum class Funct6 {
VMULHSU = 0b100110,
VMULH = 0b100111,
VMADD = 0b101001,
VMMSUB = 0b101011,
VNMSUB = 0b101011,
VMACC = 0b101101,
VMMSAC = 0b101111,
VNMSAC = 0b101111,

VFDIV = 0b100000,
VFRDIV = 0b100001,
Expand Down Expand Up @@ -2571,6 +2571,154 @@ void RiscVEmitter::VMAX_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm)
Write32(EncodeIVV(vd, rs1, vs2, vm, Funct6::VMAX));
}

void RiscVEmitter::VMUL_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMUL));
}

void RiscVEmitter::VMUL_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMUL));
}

void RiscVEmitter::VMULH_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMULH));
}

void RiscVEmitter::VMULH_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMULH));
}

void RiscVEmitter::VMULHU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMULHU));
}

void RiscVEmitter::VMULHU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMULHU));
}

void RiscVEmitter::VMULHSU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMULHSU));
}

void RiscVEmitter::VMULHSU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMULHSU));
}

void RiscVEmitter::VDIVU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VDIVU));
}

void RiscVEmitter::VDIVU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VDIVU));
}

void RiscVEmitter::VDIV_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VDIV));
}

void RiscVEmitter::VDIV_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VDIV));
}

void RiscVEmitter::VREMU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREMU));
}

void RiscVEmitter::VREMU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VREMU));
}

void RiscVEmitter::VREM_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VREM));
}

void RiscVEmitter::VREM_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VREM));
}

void RiscVEmitter::VWMUL_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMUL));
}

void RiscVEmitter::VWMUL_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMUL));
}

void RiscVEmitter::VWMULU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMULU));
}

void RiscVEmitter::VWMULU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMULU));
}

void RiscVEmitter::VWMULSU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMULSU));
}

void RiscVEmitter::VWMULSU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMULSU));
}

void RiscVEmitter::VMACC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMACC));
}

void RiscVEmitter::VMACC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMACC));
}

void RiscVEmitter::VNMSAC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VNMSAC));
}

void RiscVEmitter::VNMSAC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VNMSAC));
}

void RiscVEmitter::VMADD_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VMADD));
}

void RiscVEmitter::VMADD_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VMADD));
}

void RiscVEmitter::VNMSUB_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VNMSUB));
}

void RiscVEmitter::VNMSUB_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VNMSUB));
}

void RiscVEmitter::VWMACCU_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMACCU));
}

void RiscVEmitter::VWMACCU_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMACCU));
}

void RiscVEmitter::VWMACC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMACC));
}

void RiscVEmitter::VWMACC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMACC));
}

void RiscVEmitter::VWMACCSU_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVV(vd, vs1, vs2, vm, Funct6::VWMACCSU));
}

void RiscVEmitter::VWMACCSU_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMACCSU));
}

void RiscVEmitter::VWMACCUS_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm) {
Write32(EncodeMVX(vd, rs1, vs2, vm, Funct6::VWMACCUS));
}

bool RiscVEmitter::AutoCompress() const {
return SupportsCompressed() && autoCompress_;
}
Expand Down
50 changes: 50 additions & 0 deletions Common/RiscVEmitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -579,6 +579,56 @@ class RiscVEmitter {
void VMAX_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VMAX_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);

void VMUL_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VMUL_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VMULH_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VMULH_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VMULHU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VMULHU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
// Takes vs2 as signed, vs1 as unsigned.
void VMULHSU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VMULHSU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);

void VDIVU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VDIVU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VDIV_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VDIV_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VREMU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREMU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VREM_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VREM_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);

void VWMUL_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VWMUL_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VWMULU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VWMULU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);
void VWMULSU_VV(RiscVReg vd, RiscVReg vs2, RiscVReg vs1, VUseMask vm = VUseMask::NONE);
void VWMULSU_VX(RiscVReg vd, RiscVReg vs2, RiscVReg rs1, VUseMask vm = VUseMask::NONE);

// Multiply and add - vd += vs1 * vs2.
void VMACC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VMACC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Multiply and sub - vd -= vs1 * vs2.
void VNMSAC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VNMSAC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Multiply and add - vd = vd * vs1 + vs2.
void VMADD_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VMADD_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Multiply and sub - vd = -(vd * vs1) + vs2.
void VNMSUB_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VNMSUB_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Widening multiply and add - vd(wide) += vs1 * vs2.
void VWMACCU_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VWMACCU_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Widening multiply and add - vd(wide) += vs1 * vs2.
void VWMACC_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VWMACC_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Widening multiply and add - vd(wide) += S(vs1) * U(vs2).
void VWMACCSU_VV(RiscVReg vd, RiscVReg vs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
void VWMACCSU_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);
// Widening multiply and add - vd(wide) += U(rs1) * S(vs2).
void VWMACCUS_VX(RiscVReg vd, RiscVReg rs1, RiscVReg vs2, VUseMask vm = VUseMask::NONE);

// Compressed instructions.
void C_ADDI4SPN(RiscVReg rd, u32 nzuimm10);
void C_FLD(RiscVReg rd, RiscVReg addr, u8 uimm8);
Expand Down