CMOS Inverter: DC Analysis

• Analyze DC Characteristics of CMOS

Gates by studying an Inverter

• DC Analysis
– DC value of a signal in static conditions

• DC Analysis of CMOS Inverter

– Vin, input voltage
– Vout, output voltage
– single power supply, VDD
– Ground reference
– find Vout = f(Vin)

• Voltage Transfer Characteristic (VTC)

– plot of Vout as a function of Vin
– vary Vin from 0 to VDD
– find Vout at each value of Vin
Inverter Voltage Transfer Characteristics
• Output High Voltage, VOH
– maximum output voltage
• occurs when input is low (Vin =
0V)
• pMOS is ON, nMOS is OFF
• pMOS pulls Vout to VDD
– VOH = VDD
• Output Low Voltage, VOL
– minimum output voltage
• occurs when input is high (Vin =
VDD)
• pMOS is OFF, nMOS is ON
• nMOS pulls Vout to Ground
– VOL = 0 V
• Logic Swing
– Max swing of output signal
• VLS = VOH - VOL
•
Inverter Voltage Transfer Characteristics
• Gate Voltage, f(Vin) •Drain Voltage, f(Vout)
VGSn=Vin, VDSn=Vout, VSDp=VDD-
VSGp=VDD-Vin Vout +
• Transition Region (between VOH and
VSGp
VOL) -
– Vin low +
• Vin < Vtn
VGSn
– Mn in Cutoff, OFF -
– Mp in Triode, Vout pulled to VDD
• Vin >Vtn & Vin < Vout
– Mn in Saturation, strong current
– Mp in Triode, VSG & current reducing
– Vout decreases via current through Mn
– Vin = Vout (mid point) ≈ ½ VDD
– maximum current Vin < VIL
– Mn
at Vin and Mp both in Saturation
= Vout input logic
– Vin high LOW
• Vin > ~Vout, Vin < VDD - |
Vin > VIH
Vtp|
– Mn in Triode, Mp in input logic
Saturation HIGH
• Vin > VDD - |Vtp|
Inverter Voltage Transfer Characteristics
Vin0 Vin1
VDD Vin2
A B

Vout
C

Vin3
D Vin4 Vin5
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
 Noise margin

•Noise margin is a measure of the

robustness of an inverter

Models a chain of inverters.

Example:
• First inverter output is VOH
• Second inverter recognizes
input > VIH as logic ‘1’
• Difference VOH-VIH is “safety
zone” for noise
 Noise margin

This parameter allows you to determine the

allowable noise voltage on the input of a gate
so that the output will not be corrupted.

The specification most commonly used to

describe noise margin (or noise immunity) uses
two parameters: the LOW noise margin, NML,
and the HIGH noise margin, NMH
 Noise margin

VOH: Maximum output voltage when the output level is logic " 1“

VOL Minimum output voltage when the output level is logic "0“

VIL: Maximum input voltage which can be interpreted as logic "0“

VIH: Minimum input voltage which can be interpreted as logic " 1"
 Noise Margin
• Input Low Voltage, VIL
– Vin such that Vin < VIL =
logic 0
• where
– point ‘a’ on the Vin
plot
slope, Vout  1
• Input High Voltage, VIH
– Vin such that Vin > VIH = logic 1
– point ‘b’ on the plot
• where slope =-1
• Voltage Noise Margins
– measure of how stable inputs are with respect to signal
VNMH = VOH - VIH
– interference = VDD -
– VNML = VIL - VOL VIHVIL
=
– desire large VNMH and VNML for best noise
immunity
CMOS Inverter: VIL Calculation

At point a NMOS saturation, PMOS linear

• Differentiate and set dVout/dVin to –1

CMOS Inverter: VIH Calculation
At point b NMOS linear, PMOS saturation

• Differentiate and set dVout/dVin to –1

 Switching Threshold
• Switching threshold = point on VTC where Vout
= Vin
– also called midpoint voltage, VM
– here, Vin = Vout = VM
• Calculating VM
– at VM, both nMOS and pMOS in Saturation
– in an inverter, IDn = IDp, always!
nC OX W  (V  V )2 
I Dn– solve equation
(VGSn V tn) 2 forn V
(VMGSn V tn) 2 p
 2 L 2 2 I
Dp
   SGp tp
– express in terms of
n V
(VM  V2 ) p (V  V  V 2 n
M
)tn DD M tp
  (VM  V tn ) 
p V
DD  V M  V tp
2 2
– solve for VDD  V tp 
n
tn
VM V p
VM
 n
1
 p
 Effect of Transistor Size on VTC
• Recall W n
k' n  VDD  V tp 
W n L n
tn
p
n  k  VM V
L p   W  n
'n k' p    1
 Lp  p
• If nMOS and pMOS are same
size
– (W/L)n = (W/L)p  C  W  n oxn
  L n   n 
– Coxn = Coxp n
p  p
 pC oxp  W  2or3
(always)
W   L 
 
• If n

 L p 
,then  np 
p
since L normally min. size for all tx,
p W  can get betas equal by making Wp larger
1  
L n than Wn
• Effect on switching threshold
– if n  p and Vtn = |Vtp|, VM = VDD/2, exactly in the
middle

• Effect on noise margin

– if n  p, VIH and VIL both close to VM and noise margin is
good
 Example
• Given
– k’n = 140uA/V2, Vtn = 0.7V,
VDD = 3V
– k’p = 60uA/V2, Vtp = -0.7V
• Find
– a) tx size ratio so that VM= 1.5V
– b) VM if tx are same size

transition pushed
lower as beta ratio
increases
 CMOS Inverter: Transient Analysis
• Analyze Transient Characteristics
of CMOS Gates by studying an
Inverter

• Transient Analysis
– signal value as a function of time

• Transient Analysis of CMOS

Inverter
– Vin(t), input voltage, function of time
– Vout(t), output voltage, function of
time
– VDD and Ground, DC (not function of
time)
– find Vout(t) = f(Vin(t))

• Transient Parameters
 Transient Response
• Response to step change in
input
– delays in output due to parasitic R
&C
• Inverter RC=Model
– Rn 1/[n(VDD-
+
Vtn)]
– Resistances
– Rp = 1/[n(VDD-| Vout
– OutputVtp|)]
Cap. (only output is CL -
important)
• CDn (nMOS drain capacitance)
–
CDn = ½ Cox Wn L + Cj ADnbot + Cjsw
• CDp (pMOS drain
P
capacitance)
– CDnsw
Dp = ½ Cox Wp L + Cj ADpbot + Cjsw

• LoadPDpsw
capacitance, due to gates attached at the
output
– CL = 3 Cin = 3 (CGn + 3 is a “typical”
• TotalCGp ),
Output load
Capacitance
– Cout = CDn + CDp + term “fan-out”
describes # gates
CL
attached at output
 Fall Time
• Fall Time, tf
– time for output to fall from
‘1’ to ‘0’
–
i  Cout Vout  Vout
derivation: t Rn
• initial condition, Vout(0) =
• VDD
solutio time
t constant
n  VDD e  n n = RnCout

Vout(t)
 VDD 
t  n ln
 
Vout 
– definition
• tf is time to fall from
90% value [V1,tx] to 10% value
[V0,ty]
  
t  n  ln VDD   ln VDD 
  0.1 DD   0.9V DD 
V
• tf = 2.2 n
 Rise Time
• Rise Time, tr
– time for output to rise from
‘0’ to ‘1’
–
i Vout VDD  Vout
derivation: C out t  Rp
• initial condition, Vout(0) =
0V
• solution time

Vout(t)  DD 1  e   p  constant
t
p = RpCout
V  
– definition
• tf is time to rise from
10% value [V0,tu] to 90% value
•[V t,tr ]= 2.2 p
1 v

• Maximum Signal
Frequency
– fmax = 1/(tr +
tf)• faster than this and the output can’t
settle
 Propagation Delay
• Propagation Delay, tp
– measures speed of output reaction to input
change
– tp = ½ (tpf + tpr)
• Fall propagation delay, tpf
– time for output to fall by 50%
• reference to input change by 50%
• Rise propagation delay, tpr
– time for output to rise by 50%
• reference to input change by 50%
• Ideal expression (if input is step Propagation
change) delay
– ttpr =
– = ln(2)
ln(2) p
pf n measurement:
• Total
 Propagation - from time input reaches 50%
Delay
– tp = 0.35(n + value
- to
Add rise and fall propagation
time delays50%
output reaches for
p)
total value value
 Switching Speed -Resistance
• Rise & Fall
n = RnCout p = RpCout
Time
– tf = 2.2 n , tr = 2.2 
• Propagation
, p
Rn = 1/[n(VDD-Vtn)] = Cox (W/L)
Delay Rp = 1/[p(VDD-|Vtp|)]
– tp = 0.35(n
Cout = CDn + CDp +
+ p)
– delay  n + CL
• In
– n + p = Cout
p General
• Define
(Rn+Rp)delay in terms Beta Matched if n=p=,
of design parameters Rn+Rp = 2 = 2L
– Rn+Rp = (VDD-Vt)(n
+p) n p(VDD-Vt)2  (VDD-Vt) Cox
and
W (VDD-Vt) if
Width Matched L=Ln=Lp
– Rn+Rp =n + p
n p(VDD-Vt) = (VDD-Vt)
( p) Cox W
Wn=Wp=W,n Rn+Rp
• if Vt = Vtn = |Vtp| To decrease R’s,
L L,
(n+W,
p) VDD, ( p,
Cox )
 Switching Speed -Capacitance
• From Resistance we Cout = CDn + CDp +
have CL if L=L =L
n p estimate
– L, W, VDD, ( p, CL = 3 (CGn + CGp) = 3 Cox
Cox
– ) 
W increases (WnL+WpL)
–Cout but  VDD increases CDn = ½ Cox Wn L + Cj ADnbot + Cjsw
• Cou
power PDnsw
C Dp = ½ Cox Wp L + Cj ADpbot + Cjsw
t– Cout = ½ Cox L (W +W ) +
n p PDpsw
~2
Cj 2L (Wn+Wp) + 3 Cox L
L
(Wn+Wp) W
• assuming junction area
~W•2L L
• neglecting sidewall
capacitance
To decrease Cout, L, W, (Cj, Cox )
– Cout  L (Wn+Wp) [3½ Cox
• Delay ] Cout(Rn+Rp)  L W
+2 Cj = L2
L– Cout  L (Wn+Wp)
VDD
Wsize)
Decreasing L (reducing feature VDDis best way to improve
speed!
 Switching Speed -Local Modification
• Previous analysis applies to the overall design
– shows that reducing feature size is critical for higher speed
– general result useful for creating cell libraries

• How do you improve speed within a specific gate?

– increasing W in one gate will not increase CG of the load
gates
• Cout = CDn + CDp + CL
• increasing W in one logic gate will increase CDn/p but not CL
– CL depends on the size of the tx gates at the output
– as long as they keep minimum W, CL will be constant
– thus, increasing W is a good way to improve the speed
within a local point
– But, increasing W increases chip area needed, which is
bad
• fast circuits need more chip area (chip “real estate”)

• Increasing VDD is not a good choice because it

 CMOS Power
• P = PDC + Consumption
Pdyn
– PDC: DC (static) term
– Pdyn: dynamic (signal changing) term
• PDC
– P = IDD VDD
• IDD DC current from power supply
•• ideally, IDD = 0 in CMOS: ideally only current during switching
leakage currents cause IDD > 0, define quiescent leakage
action
IDDQ (due largely to leakage at substrate junctions)
current,
– PDC = IDDQ VDD
• Pdyn, power required to switch the state of a gate
– charge transferred during transition, Qe = Cout VDD
– assume each gate must transfer this charge 1x/clock
– cycle
Paverage = VDD Qe f = CoutDDV
2 f, f = frequency of

signal change Power increases with Cout

• Total P = IDDQ VDD + Cout VDD2 f and frequency, and
Power, strongly with VDD (second
order).
 Multi-Input Gate Signal Transitions
• In multi-input gates multiple signal transitions
produce output changes
• What signal transitions need to be analyzed?
– for a general N-input gate with M0 low output states and M1
high output states
• # high-to-low output transitions = M0M1
• # low-to-high output transitions = M1M0
• total transitions to be characterized = 2M0M1
• example: NAND has M0 = 1, M1 = 3
– don’t test/characterize cases without output transitions
• Worst-case delay is the slowest of all possible cases
– worst-case high-to-low
– worst-case low-to-high
– often different input transitions for each of these cases
 Series/Parallel Equivalent Circuits
• Scale both W and L
– no effective change in
W/L
 = Cox
– increases gate
(W/L)
capacitance
inputs must be at same value/voltage
• Series Transistors
effective
– increases effective L
 ½ 

• Parallel Transistors
– increases
effective W
effective
  2
 NAND: DC Analysis
• Multiple Inputs
• Multiple Transitions
• Multiple VTCs
– VTC varies with transition
• transition from 0,0 to 1,1 pushed right of
others
• why?
– VM varies with transition
• assume all tx have same L
• VM = VA = VB = Vout
– can merge transistors at this point
• if WpA=WpB and WnA=WnB
– series nMOS, N  ½ n
– parallel pMOS, P  2 p
– can now calculate the NAND VM
 NAND Switching Point
• Calculate VM for NAND
– 0,0 to 1,1 transition
• all tx change states (on, off)
• in other transitions, only 2
change
–– V M =
set IDnVA==IDpV,Bsolve
= Vout
for
series nMOS
VM VDD  V  1  n
means more
tp tn p
VM V 2 resistance to
 1 n output falling,
1
2 p
– denominator reduced shifts VTC to right
more
• VTC shifts right to balance this
effect and set VM
• For NAND with N
to VDD/2, can
inputs
VDD  V 
1  n increasing
increase  by
p Wn n > , V
but, since
tp tn
VM V N
 1 n
1
N 
V p /2
p
M
 NOR: DC Analysis
• Similar Analysis to NAND
• Critical Transition
– 0,0 to 1,1
– when all transistors change
• VM for NOR2 critical transition
– if WpA=WpB and WnA=WnB
• parallel nMOS, n  2 n
• series pMOS, p  ½ p
VDD  Vtp  2Vtn n VDD  V tp  NVtn n
p p
VM VM
 n  n
1 1 N
p p
2
for NOR2 for NOR-N
– series pMOS resistance means slower
rise
– VTC shifted to the left
– to set VM to VDD/2, increase Wp
• this will increase p
 NAND: Transient Analysis
• NAND RC Circuit
– R: standard channel
resistance
– C: Cout = CL + CDn + 2CDp
• Rise Time, tr
– Worst case charge circuit
– tr •=12.2 p ON
pMOS
• p = Rp
– bestCout
case charge circuit
• 2 pMOS ON, Rp  Rp/2
• Fall Time, tf
– Discharge Circuit
• 2 series nMOS, Rn  2Rn
• must account for internal cap,
– tf =Cx
2.2 n
Cx = CSn + D
• n = Cout (2 Rn ) + Cx
C n
Rn
 NOR: Transient Analysis
• NOR RC Circuit
– R: standard channel
resistance
– C: Cout = CL + 2CDn + CDp
• Fall Time, tf
– Worst case discharge circuit
– tf •=12.2 n ON
nMOS
• n = Rn
– bestCout
case discharge circuit
• 2 nMOS ON, Rn  Rn/2
• Rise Time, tr
– Charge Circuit
• 2 series pMOS, Rp  2Rp Cy = CSp +
• must account for internal cap,
CDp
– tr =Cy
2.2 p
• p = Cout (2 Rp ) + Cy
Rp
 NAND/NOR Performance
• Inverter: symmetry (VM=VDD/2), n = p
– (W/L)p = n/p (W/L)n
• Match INV performance with NAND  is adjusted by
– pMOS, P = p, same as inverter changing
– nMOS, N = 2n, to balance for 2 series transistor size
nMOS (width)
• Match INV performance with NOR
– pMOS, P = 2 p, to balance for 2 series
pMOS
– nMOS,
be slower N to
due = larger
n, same as inverter
Cout
• NAND and NOR will still

•This can be extended

to 3, 4, … N input
NAND/NOR gates
 NAND/NOR Transient Summary
• Critical Delay Path
– paths through series transistors will be
slower
– more series transistors means worse
delays

• Tx Sizing Considerations
– increase W in series transistors
– balance n/p for each cell

• Worst Case Transition

– when all series transistor go from OFF to
ON
– and all internal caps have to be
• charged (NOR)
 Performance Considerations
• Speed based on n, p and parasitic caps
• DC performance (VM, noise) based on n/p
• Design for speed not necessarily provide
good DC performance
• Generally set tx size to optimize speed and then
test DC characteristics to ensure adequate noise
immunity
• Review Inverter: Our performance reference
point – for symmetry (VM=VDD/2), n = p
• which requires (W/L)p = n/p (W/L)n
• Use inverter as reference point for more
outp
output
complex gates slower ut
• Apply
– let faster signals
slowest inputs to series lsigna
begin to
arriving
charge/discharge
node closest to nodes closer to VDD faste power
and Ground r supply
signa
 Timing in Complex Logic Gates
• Critical delay path is due to series-connected
transistors
• Example:
– f =all
assume x tx
(y+z)
are same
size
• Fall time critical delay
– worst case, x ON, and y or z
ON
– tf = 2.2 n
• n = Rn Cn + 2 Rn Cout
– Cout = 2CDp + CDn + CL
– Cn = 2CDn + CSn size vs. tx speed
considerations
• Rise time critical delay Wnx  Rn but Cout and
– worst case, y and z ON, x OFF Cn
– tr = 2.2 p Wpz Cn but Cout
Wny  Rp Rn and
Cp
• p = Rp Cp + 2 Rp Cout
Wpx  no effect on critical
– Cout = 2CDp + CDn + CL
path
 Sizing in Complex Logic Gates
• Improving speed within a single logic gate
• An Example: f=(a b+c d) x
• nMOS
– discharge through 3 series nMOS
– set N = 3n
• pMOS
– charge through 2 series pMOS
– set P = 2p
– but, Mp-x is alone so P1 = p
• but setting P1 = 2p might make layout easier
• These large transistors will increase capacitance
and layout area and may only give a small
increase in speed
• Advanced logic structures are best way to improve speed
 Timing in Multi-Gate Circuits
• What is the worst-case delay in multi-gate
circuits?
A A B C D F C
B F 0 0 0 0 0
C 0 0 0 1 0
D CD
0 0 1 0 1

– too many transitions to test 1 0 0 0 0 B

manually 1 1 0 0 1
• Critical Path 1 1 1 1
– longest delay through a circuit block 1

– intuitive
– largest sum of delays,
analysis: from
signal thatinput to through most
passes
output
gates
• not always true. can be slower path through fewer
A
B gates F path through most
C gates
D
critical path if delay
due to D input is very
slow
 Power in Multi-Input Logic Gates
• Inverter Power
Consumption f
– P = PDC + Pdyn = VDDIDDQ +
• assumes gates switches output state once per clock
CoutVcycle,
2
DD f
• Multi-Input Gates
– same DC component as inverter, PDC = VDDIDDQ
– for dynamic power, need to estimate “activity” of
the gate, howf,often will the output be switching
a = activity NOR
– Pdyn = NAND
coefficient
– estimate activity from truth
aCtable
outV DD
2

• a –=pp00=
p1prob. output is at 0
– p1 = prob. of transition p0=0.7 p0=0.2
to 1 5 5
p1=0.2 p1=0.7
5 5
a=3/16 a=3/16
 Timing Analysis of Transmission Gates
• TG = parallel nMOS and pMOS

• RC Model
– in general, only one tx active at same time
• nMOS pulls output low
• pMOS pushes output high
– RTG = max (Rn, Rp)
– Cin = CSn + CDp
• if output at higher voltage than input
– larger W will decrease R but increase Cin

• Note: no connections to VDD-Ground. Input signal,

Vin, must drive TG output; TG just adds extra
delay
 Pass Transistor
• Single nMOS or pMOS tx
• Often used in place of TGs
– less area and wiring
– can’t pull to both VDD and
Ground
– typically
• Rise use nMOS for better
and Fall =
1
speed y ID
Times
–  = Rn
n tim x=0 y=1 
Cout e 0
y ID
– tf =
= 2.94
18 tim =1
r n
 n• much slower than fall e x=1 y=0 
time 1

• nMOS can’t pull output to VDD

– rise time suffers from threshold loss in
nMOS