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Unit-II CMOS Inverter

• Realized by a series connection of p- and n- device
• The conduction states of Mn and Mp is determined by input voltage Vin

Static Characteristics of CMOS Inverter, Combinational

Circuit Design, Sequential Circuit Design

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Contd……….. Inverter DC characteristics

• Portrayed in the voltage transfer characteristic (VTC), which is a plot of Vout as a
function of Vin
• The output high voltage of the circuits is VOH=VDD when Vin =0
• The output low voltage is VOL=0 when Vin= VDD

(a) Low input voltage (b) High input voltage

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VTC for an Inverter CMOS inverter DC characteristic

• The logic voltage ranges are defined by the changing slope of the VTC
• A logic 0 input voltage (input low voltage) 0  Vin  VIL

• A logic 1 input voltage (input high voltage) VIH  Vin  VDD

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CMOS inverter DC characteristic CMOS inverter DC characteristic

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Contd……… VTC Variation

• At the physical level, the relative device sizes contained in the ratio (βn/βp) determine
the switching points

Dependence of VM on the device ratio

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βn/βp ratio Skewed Inverters

• Inverters with different beta ratios r = βp /βn are called skewed inverters
• The βn/βp ratio determines the slope
• If r > 1, the inverter is HI-skewed.
of the VTC • If r < 1, the inverter is LO-skewed.
• If r = 1, the inverter has normal skew or is unskewed.
• Assuming βn = βp, current across both • A HI-skew inverter has a stronger pMOS transistor.
FETs are same hence symmetrical. • Therefore, if the input is VDD/2, we would expect the output will be greater than
VDD/2.
• If βn < βp shift towards Y-axis, else • In other words, the input threshold must be higher than for an unskewed
inverter.
away from Y-axis • Similarly, a LO-skew inverter has a weaker pMOS transistor and thus a lower
Dependence of Slope on the device ratio
switching threshold.

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Contd…………… Contd…….
• As the beta ratio is changed, the switching threshold moves. • By setting the currents to be equal and opposite, we can solve for Vinv as a
function of r
• However, the output voltage transition remains sharp.
• Gates are usually skewed by adjusting the widths of transistors while maintaining
minimum length for speed.
➢ Inverter Threshold Voltage (Mid point voltage)
• The inverter threshold can also be computed analytically
β𝑛 2 • Considering that the transistors are fully saturated
𝐼𝑑𝑛 = 𝑉 − 𝑉𝑡𝑛
2 𝑖𝑛𝑣
β𝑝
• 𝐼𝑑𝑝 = 𝑉𝑖𝑛𝑣 − 𝑉𝐷𝐷 − 𝑉𝑡𝑛 2
2

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Contd…………… Noise Margin

𝑊𝑝𝑉𝑠𝑎𝑡𝑝 • Noise margin is closely related to the DC voltage characteristics
• Redefining 𝑟 = , we can again find the inverter threshold as • Noise margins give a quantitative measure of how stable the inputs are with respect to
𝑊𝑛𝑉𝑠𝑎𝑡𝑛
coupled electromagnetic signal interface.
• This Parameter allows us to determine the allowable noise on the input of a gate so that the
output will not be affected.
• The specification most commonly used to describe noise margin (or noise immunity) uses two
parameters: the LOW noise margin, NML, and the HIGH noise margin, NMH.
𝑉𝐷𝐷 • NML is defined as the difference in maximum LOW input voltage recognized by the receiving
• If 𝑉𝑡𝑛 = −𝑉𝑡𝑝 𝑎𝑛𝑑 𝑟 = 1, 𝑉𝑖𝑛𝑣 =
2 gate and the maximum LOW output voltage produced by the driving gate.
• NML= VIL – VOL
• The value of NMH is the difference between the minimum HIGH output voltage of the driving
gate and the minimum HIGH input voltage recognized by the receiving gate.
• NMH=VOH-VIH

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Contd………………… Contd...........
• where "1"
• VIH = minimum HIGH input voltage V
OH V
NMH "1" OH
• VIL = maximum LOW input voltage V
Noise Margin High IH V
• VOH= minimum HIGH output voltage Undefined IH
Region
• VOL = maximum LOW output voltage Noise Margin Low
V
NML IL Undefined
V Region
OL
"0"

Gate Output Gate Input V

IL
"0"
VNM H = VOH − VIH V
OL

VNM L = VIL − VOL

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Contd………….
• Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zone and do Contd…………
not represent legal digital logic levels. • Logic levels are defined at the unity gain point where the slope is –1.
• Therefore, it is generally desirable to have VIH as close as possible to VIL and for this value to be • If either NML or NMH for a gate are too small, the gate may be disturbed by noise that occurs on
midway in the “logic swing,” VOL to VOH. the inputs.
• This implies that the transfer characteristic should switch abruptly; that is, there should be high • An unskewed gate has equal noise margins, which maximizes immunity to arbitrary noise
gain in the transition region. sources.
• For the purpose of calculating noise margins, the transfer characteristic of the inverter and the • If a gate sees more noise in the high or low input state, the gate can be skewed to improve that
definition of voltage levels VIL, VOL, VIH, and VOH are shown in Figure noise margin at the expense of the other.
• Note that if |Vtp| = Vtn , then NMH and NML increase as threshold voltages are increased.
• Quite often, noise margins are compromised to improve speed.

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Power Dissipation in CMOS Inverter Contd…………

• The static power dissipation of the CMOS inverter is quite negligible. • Typical input and output voltage waveforms and the expected load capacitor current
• During switching events where the output load capacitance is alternatingly charged up waveform are shown in Fig.
and charged down, on the other hand, the CMOS inverter inevitably dissipates power.
➢ Derivation of dynamic power consumption of CMOS Inverter
• Consider the simple CMOS Inverter as in Figure
• Assume that the input voltage is ideal step waveform with negligible rise and fall times

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Contd……………. Contd…………….
• Assuming periodic input and output waveforms, the average power dissipated by any device
• When the input voltage switches from low to high, the pMOS transistor in the circuit is
over one period can be found as follows:
turned off, and the nMOS transistor starts conducting.
1 𝑇
• During this phase, the output load capacitance Cload is being discharged through the • 𝑃𝑎𝑣𝑔 = 𝑇 ‫׬‬0 𝑣 𝑡 . 𝑖 𝑡 𝑑𝑡 …………………………………………… 1
nMOS transistor. • Since during switching, the nMOS transistor and the pMOS transistor in a CMOS inverter
• Thus, the capacitor current equals the instantaneous drain current of the nMOS conduct current for one-half period each, the average power dissipation of the CMOS inverter
transistor. can be calculated as the power required to charge up and charge down the output load
capacitance.
• When the input voltage switches from high to low, the nMOS transistor in the circuit is
𝑇
turned off, and the pMOS transistor starts conducting. 1 𝑑𝑉𝑜𝑢𝑡 𝑇 𝑑𝑉𝑜𝑢𝑡
• 𝑃𝑎𝑣𝑔 = 𝑇 ‫׬‬02 𝑉𝑜𝑢𝑡 −𝐶𝑙𝑜𝑎𝑑 𝑑𝑡 + ‫ 𝐷𝐷𝑉 𝑇׬‬− 𝑉𝑜𝑢𝑡 𝐶𝑙𝑜𝑎𝑑 𝑑𝑡 (2)
• During this phase, the output load capacitance Cload is being charged up through the 𝑑𝑡 2
𝑑𝑡
pMOS transistor; therefore, the capacitor current equals the instantaneous drain • Evaluating the integrals in eqn.(2), we obtain:
current of the pMOS transistor.

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Contd……………….. Contd……………..
• On simplifying we get: • The switching delay times have no relevance to the amount of power consumption during the
𝟏 switching events.
• 𝑷𝒂𝒗𝒈 = 𝑻 𝑪𝒍𝒐𝒂𝒅 𝑽𝑫𝑫𝟐 • The reason for this is that the switching power is solely dissipated for charging and discharging
1 the output capacitance from VOL to VOH, and vice versa.
• As 𝑇 = 𝑓, • For this reason, the switching power expression derived for the CMOS inverter also applies to
• 𝑷𝒂𝒗𝒈 = 𝑪𝒍𝒐𝒂𝒅 𝑽𝑫𝑫𝟐𝒇 all general CMOS circuits.
• A general CMOS logic circuit consists of an nMOS logic block between the output node and the
• It is clear that the average power dissipation of the CMOS inverter is proportional to the
switching frequency f ground, and a pMOS logic block between the output and VDD.
• As in the simple CMOS inverter case, either the pMOS block or the nMOS block can conduct
• Therefore, the low-power advantage of CMOS circuits becomes less prominent in high-speed
depending on the input voltage combination, but not both at the same time.
operation, where the switching frequency is high.
• The average power dissipation is independent of all transistor characteristics and transistor • Therefore, switching power is again dissipated solely for charging and discharging the output
capacitance.
sizes.

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Contd………….
• If the total parasitic capacitance in the circuit can be lumped at the output node with
reasonable accuracy, if the output voltage swing is between 0 and VDD, and if the input
voltage waveforms are assumed to be ideal step inputs, the average switching power is
given by
• 𝑷𝒂𝒗𝒈 = 𝑪𝒍𝒐𝒂𝒅 𝑽𝑫𝑫𝟐𝒇

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