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Overview of Sequential Circuits in VLSI

The document discusses different types of sequential circuits including latches and flip-flops. It describes SR latches which can be built using NOR or NAND gates and how adding a control input modifies their behavior. D latches avoid the undesirable state of SR latches. JK latches and T latches are also summarized along with their truth tables. Edge-triggered flip-flops like SR, D, and JK flip-flops are explained which change state at the clock edge rather than immediately on input change.

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Mudit Sand
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354 views21 pages

Overview of Sequential Circuits in VLSI

The document discusses different types of sequential circuits including latches and flip-flops. It describes SR latches which can be built using NOR or NAND gates and how adding a control input modifies their behavior. D latches avoid the undesirable state of SR latches. JK latches and T latches are also summarized along with their truth tables. Edge-triggered flip-flops like SR, D, and JK flip-flops are explained which change state at the clock edge rather than immediately on input change.

Uploaded by

Mudit Sand
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Sequential Circuit

Shreyas Patel
M.Tech VLSI Design (VIT , Vellore)
SVNIT,Surat

Sequential Circuit
Every digital system is likely to have combinational
circuits, most systems encountered in practice also
include storage elements, which require that the
system be described in term of sequential logic.

S-R Latch with NOR gate


The SR latch is a circuit with two cross-coupled

NOR gates or two cross-coupled NAND gates. It


has two inputs labeled S for set and R for reset.

SR Latch with NAND Gates

SR Latch with Control


Input
The operation of the basic SR latch can be

1
1

modified by providing an additional control


input that determines when the state of the
latch can be changed. In Fig. 5-5, it consists
of the basic SR latch and two additional
0
0 1
NAND gates.
1
0

SR Latch with Control


Input

D Latch
One way to eliminate the undesirable

condition of the indeterminate state in SR


latch is to ensure that inputs S and R are
never equal to 1 at the same time in Fig 55. This is done in the D latch.

D Latch

JK latch
Circuit Diagram

Truth Table
Q

EN
K

Logic Symbol
J

EN

Truth Table

EN

Q+

EN

0
1

Q+

Function

T latch
T CLK
0
1

T
Inpu
ts

Q(t+1)

Comments

Q(t)
Q(t)'

No change
Toggle

Latch Circuits: Not Suitable


When the enable signal is active, the

excitation inputs are gated directly to the


output Q. Thus, any change in the
excitation input immediately causes a
change in the latch output.
The problem is solved by using a special
timing control signal called a clock to
restrict the times at which the states of the
memory elements may change.
This leads us to the edge-triggered memory
elements called flip-flops.

Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices
Output changes state at a specified point

on a triggering input called the clock.


Change state either at the positive edge
(rising edge) or at the negative edge
(falling edge) of the clock signal.
Clock signal

Positive edges

Negative edges

Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops.

Note the > symbol at the clock input.


S

C
R

C
Q'

C
Q'

Q'

Positive edge-triggered flip-flops


S

C
R

C
Q'

C
Q'

Negative edge-triggered flip-flops

Q'

S-R Flip-flop
S-R flip-flop: on the triggering edge of the
clock pulse,

S
0
0
1
1

S=HIGH (and R=LOW) a SET state


R=HIGH (and S=LOW) a RESET state
both inputs LOW a no change
both inputs HIGH a invalid
R CLK
0
1
0
1

Q(t+1)

Comments

Q(t)
0
1
?

No change
Reset
Set
Invalid

X = irrelevant (dont care)


= clock transition LOW to HIGH

S-R Flip-flop

D Flip-flop
D flip-flop: single input D (data)
D=HIGH a SET state
D=LOW a RESET state

Q follows D at the clock edge.


Convert S-R flip-flop into a D flip-flop: add
an inverter.
D
CLK

CLK

Q(t+1)

Q'

1
0

1
0

C
R

Comments
Set
Reset

= clock transition LOW to HIGH

A positive edge-triggered D flip-flop


formed with an S-R flip-flop.

D Flip-flop

J-K Flip-flop

T Flip-flop
T
CLK

C
K

Q'

CLK

Q(t+1)

Comments

0
1

Q(t)
Q(t)'

No change
Toggle

Thank
You

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