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Fetch Decode Execute: Fetch Execute Cycle: Von Neumann Architecture: Processor Can Directly Access Memory!

The document describes the fetch-execute cycle in a Von Neumann architecture. It consists of 3 main stages - fetch, decode, execute. In the fetch stage, the program counter sends the address of the next instruction to the memory address register via the address bus. The memory data register then fetches the instruction from memory via the data bus and stores it in the current instruction register. In the decode stage, the instruction is decoded. In the execute stage, the instruction is executed by the arithmetic logic unit, with results stored in the accumulator register. The process then repeats with the program counter incremented to the next instruction address.

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Usman Ameen
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67 views

Fetch Decode Execute: Fetch Execute Cycle: Von Neumann Architecture: Processor Can Directly Access Memory!

The document describes the fetch-execute cycle in a Von Neumann architecture. It consists of 3 main stages - fetch, decode, execute. In the fetch stage, the program counter sends the address of the next instruction to the memory address register via the address bus. The memory data register then fetches the instruction from memory via the data bus and stores it in the current instruction register. In the decode stage, the instruction is decoded. In the execute stage, the instruction is executed by the arithmetic logic unit, with results stored in the accumulator register. The process then repeats with the program counter incremented to the next instruction address.

Uploaded by

Usman Ameen
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Fetch Execute Cycle:

Von Neumann Architecture:


Processor can directly access memory!
Units Registers Buses
Memory Unit MAR Memory Address Register Address Bus
MDR Memory Data Register Data Bus
Control Unit PC Program Counter Control Bus
CIR Current Instruction Register

ALU Accumulator
(Arithmetic & Logic Unit)
Arithmetic (+,-,*,/)
Logic (AND,OR,NOT)

FETCH DECODE EXECUTE

Units
Memory Unit Address, Content
Address……Memory Location
Content……Data or Instructions
Control Unit Co-ordination between different components
Flow of data in between the computer System
Attach….I/O Devices, Processor, Memory Unit
ALU Processor
(Arithmetic & Logic Unit) Calculations
Arithmetic (+,-,*,/) Calculations Acc
ALU: Unit, that will perform the calculations
Logic (AND,OR,NOT)
Acc: Registers within ALU, that will hold the calculations performed by ALU.

Buses Description Direction


Address Bus Signals related to addresses UNI (single)
Data Bus Signals related to data/content BI (two way)
Control Signals co-ordination/control UNI/BI
FETCH DECODE EXECUTE
6MARKS
PC PC contains the address of the NEXT instruction.
MAR Address is transferred from PC TO MAR via address bus.
MDR Holds the data of the address coming from MAR, done
via data bus.
CIR Instruction will be copied from MDR to CIR
PC+1 Increment
DECODED & EXECUTED Executed

7MARKS
PC PC contains the address of the NEXT instruction.
MAR Address is transferred from PC TO MAR via address bus.
MDR Holds the data of the address coming from MAR, done
via data bus.
CIR Instruction will be copied from MDR to CIR
PC+1 Increment
BACK TO MAR There is any address part left, that will be sent back to
MAR
DECODED & EXECUTED Executed
8MARKS
IAS Holds the instructions before they are processed
PC PC contains the address of the NEXT instruction.
MAR Address is transferred from PC TO MAR via address bus.
MDR Holds the data of the address coming from MAR, done
via data bus.
CIR Instruction will be copied from MDR to CIR
PC+1 Increment
BACK TO MAR There is any address part left, that will be sent back to
MAR
DECODED & EXECUTED Executed
9MARKS
Memory UNIT Address will be passed from Memory Unit to IAS
IAS Holds the instructions before they are processed
PC PC contains the address of the NEXT instruction.
MAR Address is transferred from PC TO MAR via address bus.
MDR Holds the data of the address coming from MAR, done
via data bus.
CIR Instruction will be copied from MDR to CIR
PC+1 Increment
BACK TO MAR There is any address part left, that will be sent back to
MAR
DECODED & EXECUTED Executed

IAS Registers
Immediate Access Store (PC,MAR,MDR,CIR,Accumulator)
Holds the instructions before they are Holds the instructions under
processed processing.
TO BE PROCESSED BEING PROCESSED

ALU Accumulator
Arithmetic and Logic Unit Register
PERFORMS the calculations HOLDS the calculations performed by
ALU
Arithmetic (+,-,*,/)
Logical (AND,OR,NOT)

Buses Control Unit


PATHWAYS to transmit data DATA FLOW
Co-ordination
PC
PC Holds the address of the NEXT instruction
MAR Holds the address of the CURENT instruction
MDR Holds the DATA of the CURRENT address
CIR Decodes and Executes
ACC Holds CALCULATIONS.

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