FPGA Implementation of Low-Power UART

Y. Sri Chakrapani Dr M Kamaraju Dr. [Link] Rao

Assoc Prof., Dept. of E.C.E, Prof. & HOD, Dept. of E.C.E , Prof. & HOD, Dept. of E.C.E ,
Gudlavalleru Engineering College, Gudlavalleru Engineering College, Bapatla Engineering College,
Gudlavalleru , India Gudlavalleru , India Bapatla , India
Email:srichakrapani@[Link] Email: madduraju@[Link] Email: nvrao68@[Link]

approximately 27% can be achieved with slight increase in area

Abstract—To meet the modern Communication systems demands,
this paper presents an implementation of Low Power UART and delay.
(Universal Asynchronous Receiver Transmitter) using FPGA (Field II. POWER REDUCTION TECHNIQUES
Programmable Gate Array). The technique used to design low
power UART is the usage of gray code instead of normal binary Since most of today's designs are based on CMOS technology,
code in the FSM (Finite State Machine) implementation for the first step toward power reduction is to understand the sources
obtaining less number of signal transitions. FPGA implementation of power dissipation in such devices [5]. Power consumption
of Low Power UART is done by mapping Verilog HDL design entry
sources in digital CMOS circuits are divided into three main
into the gate level net list with Xilinx Virtex2 FPGA. . The power
consumption of UART using gray code and binary code is obtained categories:
using XPower tool of Xilinx ISE 9.1i. • Static power dissipation
Index Terms—Low-Power; UART; FPGA; FSM. • Short-circuit power dissipation
• Dynamic power dissipation
I. INTRODUCTION Dynamic power is the dominant source of power dissipation
in CMOS devices and accounts for approximately 90 percent of
In modern VLSI design, low power is a important
overall CMOS power consumption. It occurs during the
parameter with major implications, especially for portable or
switching of logic gates, and as a result, this type of power
high- performance applications. Several techniques for low-
dissipation is frequency dependent. Dynamic power is therefore
power design have been proposed and evaluated by [3]
the average power required to perform all the switching events
and [4], including pipeli ne and parallel data paths,
across the circuit. Equation (1) defines various parameters of
reduction of glitches, supply voltage scaling, and usage of
gray codes. Many of these techniques have been shown to dynamic power dissipation (PDynamic).
produce marked power savings, especially when used in PDynamic = 1 / 2 ⋅ β ⋅ C ⋅ VDD
2
⋅F (1)
conjunction with other techniques. One such design, is utilized
in this paper as a means to implement Finite State
Machines (FSMs) using Gray codes instead of binary codes [2]. where,
This power reduction technique is applied to a UART device. β = Switching Activity per Node
UART is a common device used in many applications requiring C = Switched Capacitance
a serial interface. Most microcontrollers are designed to have at F = Frequency (switching events per second)
least one UART interface. One obvious application for the low- VDD = Supply Voltage
power UART design is ultra-low- power sensor devices. Battery- Low-power techniques vary depending on the level of the
powered sensors must acquire and transmit data (often serially) design targeted, ranging from semiconductor technology to the
with minimal power consumption. As an Intellectual Property higher levels of abstraction. These abstraction levels are
(IP) core or as a stand-alone device, the design presented in classified as algorithm, architecture, RT, gate, and transistor
this paper takes steps towards significantly reducing the power levels. Fig 1 shows various levels of hierarchy that should be
consumption for a UART serial interface. considered for low-power designs.
In this UART transmitter, a power reduction of
 Power-Saving
Algorithm Level Optimization Method
Percentage
Optimization
Algorithm Level 75

Architecture Level Architecture Level 50–75

Optimization
Register Transfer Level 15–50

Register Transfer Gate Level 5–15

Level Optimization
Transistor Level 3–5

Gate Level III. UART DESCRIPTION

Optimization
A Universal Asynchronous Receiver/Transmitter (UART) is
a device used for serial communications, which converts serial
Fig 1. Levels of Design power Optimization.
to parallel data (Receiver) and parallel to serial data (transmitter)
The higher levels of design abstraction shown in Fig 3 [6]. The parallel side of a UART is usually connected to the bus
provide larger amounts of power reduction for chip designs [5]. of a computer. When the computer writes a byte to the UART's
In higher levels of abstraction, such as algorithm level, designers transmit data register, the UART will start to transmit it on the
have a greater degree of freedom to implement low-power serial line.
design techniques. Hence, power-optimization process is the The design presented is a simple UART which can be used
most effective method in higher levels of abstraction. as a transmitter and receiver. The signals of the simple UART
As we move toward the lower levels, the amount of power Transmitter is given in Fig 2.
savings becomes less significant and the speed of power The UART Transmitter Frame is an asynchronous (i.e. clock-
optimization becomes slower. Lower level power-optimization less) serial communications protocol. This UART transmitter
techniques are more accurate; however, they are not as fast as frame consists of serial data including 1 start bit, 8 bits of data
higher level methods. Table I illustrates the amount of power and 1 bits stop bits [1]. Fig 3 shows the particular data format
savings for various optimization methods [5]. It's important to implemented in this design. Idle receive periods are
mention that a successful power-optimization methodology characterized by a high receive signal. The start of a
requires low-power techniques to be carefully considered at each transmission is marked by a low “start bit” which is
level of design abstraction. immediately followed by eight data bits, least-significant bit
Power can be reduced in algorithm level by choosing the (LSB) first. The end of a transmission is marked by a high “stop
appropriate coding style is given this paper. The use of gray bit.”
codes results in a significant decrease in switching activity.
Din [7:0]
Minimizing the number of transitions in the state assignment of
CS [3:0]
an FSM has a considerable influence on lowering the power Clock
consumption. If the next state of an FSM differs by one variable Ready
Load
from the preceding state (minimum Hamming distance)
activities are minimized and power can be saved considerably. Reset
Txd
Therefore, gray coding is preferred to binary coding in state Shift
assignment of FSMs. This technique is also very useful for
power reduction in SOC bus interconnects. Buses are significant
sources of power dissipation (almost 20 percent of total power Fig 2. Simple UART Transmitter
dissipation in most SOCs are due to bus interconnects) because The UART Transmitter operation is represented by a simple
of their high switching activity and large capacitive loading. flow chart, which is given in Fig 4. The Finite state machine is a
Therefore, bus signal encoding is very effective in lowering the simple Mealy type. The operation is described as follows:
switching activity. Upon system reset, the state machine defaults to IDLE state.
In this state, the state machine idles for as long as no transmit
TABLE I: POWER SAVINGS FOR OPTIMIZATION METHODS command (Ready Signal) is given. But when “READY”
becomes Active High (logic 1), then the state machine
transitions to START state. In START state, the Shift bit is transfer of serial bits in the next frame.
tested and when it is logic 1, the FSM enters into DATA7 state,
which represents the transmission of serial data from UART.

VHIGH
Start D7 D6 D5 D4 D3 D2 D1 D0 Stop
VLOW

Idle Data Transmission (Least Significant Bit first) Idle

Fig 3. Universal Asynchronous Receiver Transmitter serial communication frame

Reset
Shift=0
Ready && Shift=0
D4
Idle
Shift=1
Shift=0
Ready && Shift=1
Shift=0
D3
Start
Shift=1
Shift=1 Shift=0
Shift=0 D2
D7
Shift=1 Shift=0
Shift=1
Shift=0 D2
D6
Shift=1 Shift=0
Shift=1
Shift=0
D0
D5
Shift=1
Shift=1 Shift=0
Stop
Ready && Shift=1

Ready=0 && Shift=1

Fig 4. Universal Asynchronous Receiver Transmitter State Diagram

But if this bit is logic 0, the START state is kept in hold IV. LOW POWER UART IMPLEMENTATION
position. So, if the shift bit is logic 1 continuously then the state
A gray-coding FSM representation of numbers requires fewer
transition will occur from DATA7 to DATA0 state and finally
transitions than does a binary-coding FSM representation [8].
the STOP state.
Table II given below shows the numbers of transitions used for
In the STOP State if ready signal is active low, then the FSM
Binary and Gray coding respectively.
is going back into IDLE state and if ready signal is active high,
then the FSM is going into START state, which denotes the
The gray coding FSM uses less number of transitions as
compared to binary coding [7]. Since dynamic power is directly binary coding FSM for input value 01H is 46.81mw. The power
related to transition activity β (switching node), less power is consumed by using gray coding FSM for the same input value
consumed when states of an FSM use gray coding. 01H is 34.18mw. So, there is a decrease of 27% power by using
gray coding FSM instead of binary coding FSM for the
TABLE II: NO. OF TRANSITIONS FOR BINARY AND GRAY CODING
remaining input values.
Binary Coding Gray Coding The simulation results for UART FSM with binary coding
No. Of No. Of have been performed using Xilinx ISE Simulator and is shown
State in the Fig 5. The signal “CS” represents the current state of the
A B C D Transa A B C D Transa
ctions ctions FSM, “din” represents the 8- bit data input, “txd” represents the
Idle 0 0 0 0 0 0 0 0 0 0 serial data transmitted to the output, “ready” indicates whether
Start 0 0 0 1 1 0 0 1 0 1 the holding register is full or not, “load” indicates writing into
holding register, “shift” indicates when to shift a bit right.
Data7 0 0 1 0 2 0 0 0 1 2
Data6 0 0 1 1 1 0 0 1 1 1
Data5 0 1 0 0 3 0 1 1 1 1
Data4 0 1 0 1 1 0 1 0 1 1
Data3 0 1 1 0 2 0 1 0 0 1
Data2 0 1 1 1 1 0 1 1 0 1
Data1 1 0 0 0 4 1 1 1 0 1
Data0 1 0 0 1 1 1 0 1 0 1
stop 1 0 1 0 2 1 0 1 1 1
Total
Transi 18 11
tions
Fig 5. Simulation results of UART FSM with binary coding
V. RESULTS
The UART Transmitter has been implemented in Verilog The simulation results for UART FSM with gray coding also
Hardware Description Language [9] using Xilinx Virtex2 have been performed using Xilinx ISE Simulator and is shown
xc2v40-5cs144 FPGA. The Power consumed for Binary coding in the Fig 6.
FSM and Gray coding FSM are calculated using XPower Tool
belonging to XILINX ISE 9.1i [10]. The results of the power
consumption using binary and gray coding for some random
inputs are given in Table III.
TABLE III: POWER CONSUMPTION USING BINARY AND GRAY
CODING

Input Power Consumption (mW)

Values Binary Coding Gray Coding
01 H 46.81 34.18
11 H 49.71 36.83
21 H 49.63 36.83 Fig 6. Simulation results of UART FSM with gray coding

31 H 49.80 36.83
The synthesis process has been performed for the low
41 H 49.40 36.57 power UART transmitter and mapped into the target FPGA
device Xilinx Virtex2 xc2v40-5cs144. The total device
51 H 52.32 39.22
utilization for the design is given in the Table IV.
61 H 49.46 36.57
71 H 49.61 36.57
81 H 46.82 34.18
If we observe the results, the power consumed by using
TABLE IV: TARGET FPGA DEVICE UTILIZATION REFERENCES
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Transmitter using Xilinx Virtex2 FPGA. The same power
reduction technique of using gray coding instead of binary
coding for avoiding more no. of transitions in Finite state
machines can be extended to UART Receiver.