Unit-2

Transistor and Gate Sizing:

At the circuit level, transistors are the basic building blocks and a digital circuit can be
viewed as a network of transistors with some additional parasitic elements such as capacitors
and resistors
• Transistor sizes are the most important factor affecting the quality ie area, and power
dissipation of a circuit
• Some studies assume that the sizing problem is a convex function and linear programming
can be used to solve the sizing problem optimally
• Another problem encountered in cell based design is gate sizing
• The goal is to choose a set of gate sizes that best fits the design constraints
Sizing an Inverter Chain
• The simplest transistor sizing problem is that of an inverter chain
• The general design problem is to drive a large capacitive load without excessive delay, area
and power requirements
• A large inverter is required to drive the large capacitive load at the final stage

If the chain is too long, the signal delay will be too large due to intrinsic delay of each
inverter
• If the chain is too short, the output signal slope will be very weak with long rise and fall
times, which again causes long delay
• The challenge is to decide the length of the chain ie. How many inverters, and the size of
each inverter.
Transistor and Gate Sizing for Dynamic Power Dissipation:
As seen in the previous graph, a large gate is required to drive a large load with acceptable
delay but requires more power
• This is similar to the classical delay area tradeoff problem
• If we are not allowed to restructure the transistor network, the sizing for dynamic power
reduction generally has the same goal as the area reduction problem
• The basic rule is to use the smallest transistors or gates that satisfy the delay constraints
• To reduce dynamic power, the gates that toggle with higher frequency should be made
smaller
• Although the basic rule sounds simple, the actual sizing problem is very complicated

• Consider a part of the circuit as shown above

• Suppose that the gates are not on the critical delay path and should be sized down
• W can size down the first gate, the second gate or both, subject to the available sizes in the
cell library as long as the path delay is not violated
• If the path contains many gates, the optimization problem becomes very complicated
• Stack time – Used to express the timing constraints of the circuit – It is the difference
between the signal required time and signal arrival time at the output of a gate
• A positive stack time mean that the signal arrived earlier than its required time and the gate
can be sized down
• The goal of gate sizing is to adjust the gate sizes such that the stack time of each gate is as
low as possible without any gate having a negative stack i.e. timing violation
• The area minimum sizing problem has been a subject of research in logic synthesis for
dozen of years
• Today in top down cell based design environment gate sizing has been much automated by
the logic synthesis system

Transistor Sizing for Leakage Power Reduction:

• An interesting problem occurs when the sizing goal is to reduce the leakage power of a
circuit
• The leakage current of a transistor increases with decreasing threshold voltage and channel
length
• In general, a lower threshold or shorter channel transistor can provide more saturation
current and thus offers a faster transistor
• The presents a tradeoff between leakage power and delay
• The leakage power of a digital circuit depends on the logic state of a circuit
• Consider a simple two transistor inverter
• If the output of the inverter is at logic high, the leakage current of the inverter is determined
by the N- transistor that is turned off
• Conversely if the output is low, the leakage current depends on the P- transistor
• In order to suppress the leakage current, we can increase the threshold voltage or the
channel length of the Ntransistor
• However, by doing so we also increase the delay of the inverter because the N- transistor
now offers less saturation current when it is turned ON
• If we are fortunate that the falling transition of the inverter is not the critical delay, we can
use skewed transistor sizing method to reduce the leakage power without incurring any delay
penalty
Transistor sizing for leakage power reduction or speed increase
Equivalent Pin Ordering :
• Most combinational digital logic gates have input pins that logically equivalent
• Eg: AND, OR, XOR
• Such gates are use frequently because they are natural to the human thinking process
• As for circuit implementation, the gates are robust and easy to design
• Logically equivalent pins may not have identical circuit characteristics, which means that
the pins have different delay and power consumption
• Such property can be exploited for low power design
Equivalent Pin Ordering:
• Consider a CMOS NAND gate as shown below
• We examine the condition when the input A is at high logic and the input B switches from
logic low to high
• The difference in power dissipation varies depending on various factors such as
capacitances and transistor sizes
• To conserve power the inputs should be connected such that transistors from input A to
OUT occur more frequently than transitions from input B to OUT. This low power technique
is known as pin ordering
Network Restructuring and Reorganization:
• The pin reordering technique is a special case of more general method called transistor
restructuring
• In this method, we restructure the transistors of a combinational cell, based on signal
probabilities, to achieve better power efficiency within the allowable timing constraints
• Transistor Network Restructuring – In CMOS logic design, there is a well known technique
in which a Boolean function composed of AND and OR operators is directly mapped to a
complex transistor network that implements the function
– The mapping steps are as follows:
1. Each variable in the Boolean function corresponds to a pair of P and N transistors
2. For the N transistor network, an AND operator corresponds to a serial connection and an
OR operator corresponds to a parallel connection
3. For the P transistor network, the composition rule is inverted
4. An inverter is optionally added to the output of the complex gate to maintain the proper
polarity or to ensure signal strength

Network composition of CMOS complex logic gate Y = A ( B + C )

Power reduction up to 20% was reported using the transistor network restructuring technique
In this section, we look beyond a CMOS gate and consider a transistor network
• We study the problem of partitioning and reorganizing the network to explore the different
power-area-delay trade off
• Network reorganization by definition is the task of composing different transistor networks
that can implement the same functionality
• The figure below shows two ways to implement a 4 input AND operation with a serial chain
limit of three

Flip Flops & Latches design:

• Flip flops and latches are some of the most frequently used elements in digital VLSI
• In synchronous systems, they are the starting and ending points of signal delay paths, which
decide the maximum speed of the system
• Typically, they consume more power because they are clocked at the system operating
frequency • Careful design of the flip flop and latch circuits is important to a low power VLSI
design
• The energy dissipation of a flip flop can be divided into two components:
1. Clock energy 2. Data energy
The first component is the energy dissipated when the flip flop is clocked while the data of
the flip flop is unchanged
• The second component is the additional energy required to write a different data value into
flip flop
• In a typical flip flop the two energy components are comparable
• However, in most systems, the data rate of a flip flop is typically much lower than its clock
rate
• This means that identical data values is being loaded with very high probability
• Thus, the power saving techniques for flip flops mostly concentrate on the clock energy
reduction

• The above circuits provides a different tradeoff among setup time, hold time, data to output
and clock to output delay
• The use of NMOS pass transistors instead of transmission gates reduces the loading
capacitance of the clock pin at the cost of reduced speed
• This eliminates the need for a two phase non overlapping clock on the system or a phase
splitter inverter that consumes power inside the cell
• The circuit suffers from threshold voltage loss when logic 1 is propagated through the
NMOS pass transistor
• The single phase latch circuit avoids the threshold voltage problem but relies on charge
storage effect to retain its data value
• This cause some loss in the noise margin but the circuit has been successfully used in high
performance processor design

• A flip flop is typically constructed from two latches connected together

• The single phase dynamic flip flop at the top left is a cascaded version of two single phase
latches
• It is suitable for some low power applications because it does not require internal phase
splitting inverter for the clock pin
• The circuit at the bottom was reported to achieve lower power at the same speed with more
transistors, compared to a standard flip flop design on the top right
• One circuit that an exotic differential signaling method to increase speed at the expense of
area and power is shown below