Concept Recap:

 Instruction Cycle
Time to execute an entire instruction.
A Z80 instruction may involve 1 to 6 machine cycles depending on its complexity.
 Machine Cycle
Time to perform a single operation (e.g., fetch, memory read, I/O write).
Each machine cycle is made of 3 to 6 T-states.
 T-state
The smallest unit of time, equal to one clock period.
It’s a subdivision of a machine cycle.

Example 1: OUT (10H), A

 Instruction Size: 2 bytes (OUT opcode + 8-bit port address)

 Operations:
1. Opcode fetch
2. Memory read for the second byte (port address)
3. I/O write cycle to port 10H
 Machine Cycles: 3
 T-States: Typically 11 T-states total

Example 2: LDA (1234H)

Instruction Size: 3 bytes (LDA opcode + 16-bit address)

  Operations:
1. Opcode fetch
2. Memory read for low byte of address
3. Memory read for high byte of address
4. Memory read from the address (1234H)
 Machine Cycles: 4
 T-States: Around 13 T-states
 Result: A ← (1234H), i.e., the content at memory address 1234H is copied into the A register.

Example 3: MOV A, B

 Instruction Size: 1 byte

 Operations:
1. Opcode fetch only
 Machine Cycles: 1
 T-States: 4
 Result: A ← B (copy B into A)

Example 4: MVI C, 55H

 Instruction Size: 2 bytes (opcode + immediate data)

 Operations:
1. Opcode fetch
2. Immediate data read
 Machine Cycles: 2
 T-States: 7
 Result: C ← 55H

Example 5: CALL 2050H

 Instruction Size: 3 bytes

 Operations:
1. Opcode fetch
2. Memory read (low byte of address)
3. Memory read (high byte of address)
4. Memory write (push PC high)
5. Memory write (push PC low)
 Machine Cycles: 5
 T-States: Around 17
 Result: Control jumps to address 2050H, current PC saved on stack

Instruction: IN A, (0FH)

 Size: 2 bytes
 Find: Number of machine cycles and T-states

Solution:

1. Opcode fetch
2. Read port address (0FH)
3. I/O read from port 0FH

 Machine Cycles: 3
 T-States: 11
Result: Data from port 0FH is loaded into A register

2/Instruction: LXI H, 1234H

 Size: 3 bytes
 Operation:
1. Opcode fetch
2. Read low byte (34H)
3. Read high byte (12H)
 Machine Cycles: 3
 T-States: 10

Result: HL ← 1234H

Problem 3: STA 4567H

Size: 3 bytes
Purpose: Store accumulator (A) to memory address 4567H

Operations:

1. Opcode fetch
2. Read low byte (67H)
3. Read high byte (45H)
4. Memory write (A → *4567H+)

Machine Cycles: 4

T-States: ~13

Result: Memory location 4567H gets the value from A.

Problem 4: MOV M, A

Size: 1 byte
Purpose: Store A into memory pointed by HL

Operations:

1. Opcode fetch
2. Memory write to (HL)

Machine Cycles: 2

T-States: ~7

Result: *HL+ ← A

Problem 5: PUSH B

Size: 1 byte
Purpose: Push BC register pair to stack
Operations:

1. Opcode fetch
2. Write C to stack (SP - 1)
3. Write B to stack (SP - 2)

Machine Cycles: 3

T-States: ~11

Result: Stack grows by 2 bytes, BC saved

Problem 6: POP H

Size: 1 byte
Purpose: Pop two bytes from stack into HL

Operations:

1. Opcode fetch
2. Read from (SP) into L
3. Read from (SP + 1) into H

Machine Cycles: 3

T-States: ~10

Result: HL ← *SP+, *SP+1+, SP += 2

Problem 7: XCHG

Size: 1 byte
Purpose: Exchange HL with DE

Operations:

1. Opcode fetch only

Machine Cycles: 1

T-States: 4

Result: HL ↔ DE (register swap only)

Problem 8: RET

Size: 1 byte
Purpose: Return from subroutine (pop PC from stack)

Operations:

1. Opcode fetch
2. Read low byte from stack into PCL
 3. Read high byte from stack into PCH

Machine Cycles: 3

T-States: ~10

Result: PC ← value from stack

Problem 9: CPI (Compare immediate with A)

Size: 2 bytes
Purpose: Compare A with immediate value

Operations:

1. Opcode fetch
2. Read immediate byte
3. Perform comparison (internal operation)

Machine Cycles: 2

T-States: ~7

Result: Flags affected, A unchanged

Problem 10: JZ 2100H (Jump if Zero flag set)

Size: 3 bytes
Purpose: Conditional jump based on Z flag

Operations:

1. Opcode fetch
2. Read low byte (00H)
3. Read high byte (21H)
4. If Z flag set → Load PC ← 2100H

Machine Cycles:

 3 if no jump
 4 if jump taken

T-States:

 ~10 (not taken)

 ~13 (if taken)

Result: Conditional branch

Example 1: MVI A, 34H

 Size: 2 bytes
o 1 byte for opcode (MVI A)
o 1 byte for data (34H)
  Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Memory read (immediate data)
 T-States: 4 (M1) + 3 (M2) = 7T

Result: A ← 34H

Example 2: LDA 2050H

 Size: 3 bytes
o Opcode + 16-bit address (low + high)
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Read address low byte
o M3: Read address high byte
o M4: Read memory from 2050H
 T-States: 4 + 3 + 3 + 3 = 13T

Result: A ← [2050H]

Example 3: SHLD 4000H

 Size: 3 bytes
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Read address low byte
o M3: Read address high byte
o M4: Write L to 4000H
o M5: Write H to 4001H
 T-States: 4 + 3 + 3 + 3 + 3 = 16T

Result: Stores HL pair to memory

Example 4: CALL 3000H

 Size: 3 bytes
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Read 3000H low byte
o M3: Read 3000H high byte
o M4: Write PCH to SP-1
o M5: Write PCL to SP-2
 T-States: 4 + 3 + 3 + 3 + 3 = 16T or 17T

Result: PC ← 3000H, Stack ← return address

Example 5: XRA A

 Size: 1 byte
 Instruction Cycles: 1
  Machine Cycles:
o M1: Opcode fetch
 T-States: 4T

Result: A ← A XOR A = 0, flags set accordingly

Example 6: JNZ,1000H

 Size: 3 bytes
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Read low byte
o M3: Read high byte
o M4: If jump taken, load PC
 T-States:
o Jump not taken: 4 + 3 + 3 = 10T
o Jump taken: +3T = 13T

Result: Conditional jump

Example 7: PUSH H

 Size: 1 byte
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Write L to stack
o M3: Write H to stack
 T-States: 4 + 3 + 3 = 10T or 11T

Result: Stack ← HL

Example 8: LDAX B

 Size: 1 byte
 Instruction Cycles: 1
 Machine Cycles:
o M1: Opcode fetch
o M2: Memory read from address (BC)
 T-States: 4 + 3 = 7T

Result: A ← [(BC)]
Understanding the Table:

Each row in the table corresponds to a specific machine cycle of the Z80 microprocessor. The columns represent the state of
control signals during that cycle:

 Logic 0 = Active
 Logic 1 = Inactive

Control Signals:

 M1: Machine cycle 1 (Opcode fetch)

 MREQ: Memory request
 IORQ: I/O request
 RD: Read
 WR: Write

Example 1: Opcode Fetch Cycle

Problem: Identify the control signals during the M1 Opcode Fetch cycle.

From table:

 M1 = 0 (active)
 MREQ = 0 (active)
 IORQ = 1 (inactive)
 RD = 0 (active)
 WR = 1 (inactive)

Explanation:
During an opcode fetch:

 Z80 asserts M1 to indicate the first machine cycle of an instruction.

 It also activates MREQ and RD to read the opcode from memory.
 WR and IORQ are inactive because this is not a write or I/O operation.

Result:
This cycle is used to fetch the instruction opcode from memory into the instruction register.

Example 2: Memory Write Operation

Problem: What control signals are active during a Memory Write?

From table:

 M1 = 1 (inactive)
 MREQ = 0 (active)
 IORQ = 1 (inactive)
 RD = 1 (inactive)
 WR = 0 (active)

Explanation:
The Z80 activates MREQ and WR to write data into memory.
M1 is not asserted because it’s not the first cycle of an instruction.
RD and IORQ are inactive.

Result:
This cycle writes data from the Z80’s data bus into a memory location.

Example 3: I/O Read Operation

Problem: During an I/O Read cycle, which control signals are asserted?

From table:

 M1 = 1 (inactive)
 MREQ = 1 (inactive)
 IORQ = 0 (active)
 RD = 0 (active)
 WR = 1 (inactive)

Explanation:
Z80 activates IORQ and RD to read data from an I/O device.
Memory is not involved, so MREQ remains inactive.
WR is also inactive.

Result:
This is how Z80 fetches input from peripherals (like a keyboard or sensor).

Example 4: Interrupt Acknowledge Cycle

Problem: What happens during an Interrupt Acknowledge (INTA) cycle?

From table:

 M1 = 0 (active)
 MREQ = 1 (inactive)
 IORQ = 0 (active)
 RD = 0 (active)
 WR = 0 (active)

Explanation:

 Z80 activates M1, IORQ, RD, and WR.

 This is special because the CPU acknowledges an interrupt and may fetch a restart instruction (RST).

Result:
This cycle allows the CPU to respond to hardware interrupts and prepare to execute an interrupt service routine.

Example 5: Signal Identification

Problem: A logic analyzer shows the following signals active:

MREQ = 0, RD = 0, WR = 1, IORQ = 1

Which machine cycle is this?

Solution: Matching with the table:

 MREQ = 0 (active)
 RD = 0 (active)
 WR = 1 (inactive)
 IORQ = 1 (inactive)

These values match the Memory Read cycle.

Result:
The CPU is reading data from memory.

1. During which machine cycle are the control signals MREQ and RD active, while WR and IORQ are inactive?

A) I/O Read
B) Memory Read
C) Opcode Fetch
D) Interrupt Acknowledge

Correct Answer: B) Memory Read

Explanation: MREQ = 0, RD = 0, WR = 1, IORQ = 1 matches Memory Read.

2. Which of the following machine cycles will have IORQ = 0 and WR = 0?

A) Memory Write
B) I/O Write
C) Opcode Fetch
D) I/O Read

Correct Answer: B) I/O Write

Explanation: IORQ and WR are both active only in I/O Write.

3. If M1 = 0, MREQ = 0, RD = 0, WR = 1, what is the machine cycle?

A) Opcode Fetch
B) Memory Write
C) I/O Read
D) Interrupt Acknowledge

Correct Answer: A) Opcode Fetch

Explanation: This combination uniquely identifies the Opcode Fetch cycle.

4. In an I/O Read operation, which signals are active?

A) MREQ, RD
B) IORQ, WR
C) IORQ, RD
D) MREQ, WR

Correct Answer: C) IORQ, RD

Explanation: IORQ and RD are used to read data from an I/O device.
5. Which machine cycle has all control signals (MREQ, IORQ, RD, WR) active (logic 0)?

A) Memory Write
B) I/O Read
C) Interrupt Acknowledge
D) Opcode Fetch

Correct Answer: C) Interrupt Acknowledge

Explanation: During INTA, all control lines go active

art 1: How to Solve M1 Opcode Fetch Problems

Example Scenario:

The instruction LD B, A (opcode 47H) is stored at memory address 2002H. The accumulator A holds 9FH.

We’re asked to:

1. List the sequence of events during the Opcode Fetch.

2. Use timing diagrams to show signal transitions.
Step-by-Step Execution of M1 (Opcode Fetch)

This takes 4 T-states: T1, T2, T3, T4.

T1 (Start of Opcode Fetch)

 PC (Program Counter) = 2002H is placed on the address bus A0–A15.

 M1 goes LOW (active) → indicates start of opcode fetch.
 MREQ and RD go LOW (active) after the falling edge of T1 → start memory read.
 Data bus is in high impedance.

T2 (Memory Responds)

 Memory places the opcode (47H) from address 2002H onto the data bus D0–D7.
 Data bus is now active.

T3 (CPU Reads Data)

 Z80 reads the 47H from data bus into Instruction Register.
 Control signals (RD, MREQ) go HIGH (inactive).

T4 (Instruction Decode)

 Instruction Decoder decodes 47H → execute LD B, A.

 Lower 7 address bits used to refresh DRAM (RFSH active).

Example 1: Determine the Machine Cycle

Given:
MREQ = 0, RD = 0, WR = 1, IORQ = 1, M1 = 1

Question: Which machine cycle is this?

Solution:
From the table:

 MREQ & RD = active

 WR & IORQ = inactive
 M1 = inactive

Answer: Memory Read

Explanation: Signals match the Memory Read operation.

Example 2: Identify the Cycle for an I/O Device Reading

Given:
The CPU is reading from a peripheral (I/O port). Which signals go active?

Options:
A) MREQ, RD
B) IORQ, RD
C) IORQ, WR
D) MREQ, WR
Answer: B) IORQ, RD
Explanation: IORQ is for I/O operations, and RD indicates a read.

Example 3: Write Operation to RAM

Given:
Signals active: MREQ = 0, WR = 0, RD = 1, IORQ = 1

Question: What’s happening?

Solution:

 Memory write cycle (MREQ & WR active)

Answer: Memory Write

Result: Data is written from CPU into RAM.

Example 4: Opcode Fetch Cycle Identification

Question: Which signals go active during Opcode Fetch?

Answer:
M1 = 0
MREQ = 0
RD = 0
IORQ = 1
WR = 1

Result:
CPU is fetching the instruction opcode from memory.

Example 5: Identify Interrupt Acknowledge

Question: Which cycle activates all control signals except MREQ?

Given:
M1 = 0, IORQ = 0, RD = 0, WR = 0, MREQ = 1

Answer: Interrupt Acknowledge (INTA)

Explanation: Only this cycle uses IORQ, RD, WR all at once.

Visual Timing Diagram Notes:

 CLK shows the system clock with each T-state.

 A0–A15 shows address bus (e.g., 2002H in opcode fetch).
 M1, MREQ, RD are low during M1 fetch.
 Data Bus D0–D7 shows opcode (e.g., 47H) appearing during T2-T3.
 RFSH activates during T4 for DRAM refresh.Z80 Machine Cycle & Control Signals – Practice Quiz

Section A: Multiple Choice Questions (MCQs)

1. Which of the following is not a valid signal combination for a Z80 machine cycle?
A) M1 = 0, MREQ = 0, RD = 0, WR = 1
B) M1 = 1, MREQ = 0, RD = 0, WR = 1
C) M1 = 1, IORQ = 0, RD = 0, WR = 1
D) M1 = 1, MREQ = 0, RD = 1, WR = 0

2. During the I/O Read cycle, which signals are active (logic 0)?
A) MREQ, RD
B) IORQ, RD
C) MREQ, WR
D) IORQ, WR

3. Which machine cycle has M1 = 0, IORQ = 0, RD = 0, WR = 0?

A) Memory Write
B) Opcode Fetch
C) Interrupt Acknowledge
D) I/O Write

4. In the Opcode Fetch cycle, what happens during T3?

A) Opcode is placed on the data bus
B) Address is placed on address bus
C) Instruction is decoded
D) Data is read into CPU

5. What is the purpose of T4 in M1 opcode fetch?

A) Read opcode
B) Write memory
C) Execute instruction and refresh memory
D) Fetch data from I/O

1. C
Explanation: RD and WR can't both be 1 in an I/O Read; they contradict.
2. B
IORQ and RD go LOW in an I/O Read cycle.
3. C
Interrupt Acknowledge is the only cycle where M1 = 0 and all three RD, WR, IORQ = 0.
4. D
During T3, the opcode is read from the data bus into CPU.
5. C
T4 is used for instruction decode and dynamic RAM refresh.
Example Setup

 Two machine codes:

o 3E at memory address 2000H
o 9F at memory address 2001H
 Clock frequency = 4 MHz

This means:

 Clock period T=1f=14×106=0.25μsT = \frac{1}{f} = \frac{1}{4 \times 10^6} = 0.25 \mu sT=f1=4×1061=0.25μs

Instruction Breakdown

The byte 3E corresponds to the instruction LD A, n, which loads an 8-bit immediate data into register A.

So the instruction is:

LD A, 9Fh

Which requires two machine cycles to execute:

1. Opcode Fetch (fetch the instruction 3E)

2. Memory Read (fetch the immediate operand 9F)

Machine Cycle 1: Opcode Fetch

1. Address = 2000H
2. Data = 3E
3. The Z80 reads this instruction using Opcode Fetch Cycle, which typically takes 4 T-states.
4. Timing Signals:
o M1 = 0 (Active): Indicates opcode fetch.
o MREQ = 0, RD = 0: Memory request and read signals are active.
o Data bus carries 3E.

Time Calculation:

Opcode Fetch Time=4T=4×0.25μs=1μs

Machine Cycle 2: Memory Read

1. After decoding 3E, Z80 realizes it needs to fetch the next byte (the operand).
2. It increments the Program Counter (PC) to 2001H.
3. It performs a Memory Read Cycle (not opcode fetch) to get the operand 9F.
 4. This cycle takes 3 T-states.
5. Timing Signals:
o M1 = 1 (inactive)
o MREQ = 0, RD = 0
o Data bus carries 9F

Time Calculation:

Memory Read Time=3T=3×0.25μs=0.75μs

Total Instruction Time

Total Time=Opcode Fetch+Memory Read=1+0.75=1.75μs

Timing Diagram Explanation (Figure 3)

 T1–T3 of M1 cycle = opcode fetch from 2000H

 T1–T3 of next cycle = memory read from 2001H
 D7–D0 line shows data 3E and 9F being fetched
 Control signals (MREQ, RD) go LOW during fetch/read cycles

Sure! Here are 5 detailed examples of Z80 memory read/write and opcode fetch cycles, each with timing analysis and solutions
based on a 4 MHz clock frequency (T = 0.25 µs).

Example 1: LD A, 9Fh

LD A, 9Fh ; Opcode: 3E 9F

Stored at:

 3E at 2000H
 9F at 2001H

Cycles:

1. Opcode Fetch (3E from 2000H): 4T = 1 µs

2. Memory Read (9F from 2001H): 3T = 0.75 µs
Total Time = 1.75 µs

Example 2: LD B, C

LD B, C ; Opcode: 41h

Stored at:

 41h at 3000H

Cycles:

 Only Opcode Fetch needed (no operand)

 4 T-states = 1 µs

Result: Register B gets the contents of register C

Total Time = 1 µs
Example 3: LD HL, 2345H

LD HL, 2345H ; Opcode: 21 45 23

Stored at:

 21 at 4000H
 45 at 4001H
 23 at 4002H

Cycles:

1. Opcode Fetch (21): 4T = 1 µs

2. Memory Read (Low byte 45): 3T = 0.75 µs
3. Memory Read (High byte 23): 3T = 0.75 µs
Total Time = 2.5 µs

Result: HL = 2345H

Example 4: LD (5000H), A

LD (5000H), A ; Opcode: 32 00 50

Stored at:

 32 at 5000H
 00 at 5001H
 50 at 5002H

Cycles:

1. Opcode Fetch (32): 4T = 1 µs

2. Memory Read (00): 3T = 0.75 µs
3. Memory Read (50): 3T = 0.75 µs
4. Memory Write (to 5000H): 3T = 0.75 µs
Total Time = 3.25 µs

Result: Contents of register A are stored in memory location 5000H

Example 5: IN A, (C)

IN A, (C) ; Opcode: ED 78

Stored at:

 ED at 6000H
 78 at 6001H

Cycles:

1. Opcode Fetch (ED): 4T = 1 µs

2. Memory Read (78): 3T = 0.75 µs
3. I/O Read Cycle: 4T = 1 µs (I/O read timing is slightly different)
Total Time = 2.75 µs

Result: Reads from I/O port addressed by C register and stores in A.

Steps of Execution:

1. First Machine Cycle: Opcode Fetch

 Address on address bus: 2003H

 Data on data bus: 77H (opcode)
 T1–T4 states used for fetching the opcode

Timing Details:

 T1: Z80 places 2003H on the address bus.

 T2: Memory places opcode 77H on the data bus.
 T3: Z80 reads opcode from data bus and decodes it.
 T4: Preparation for the next machine cycle.

Signals:

 MREQ goes low during T2–T3 to indicate memory request.

 RD is low to indicate read operation.
 M1 is active (only during opcode fetch).

2. Second Machine Cycle: Memory Write

 Address on address bus: 2350H (from HL)

 Data on data bus: 9FH (from accumulator A)
 T1–T3 states used for writing data

Timing Details:

 T1: 2350H placed on address bus. Data bus starts to prepare.

 T2: Z80 places 9FH on data bus.
 T3: Z80 asserts WR (Write) signal low, writing 9FH into 2350H.

Signals:
  MREQ goes low to indicate memory operation.
 WR goes low during T2–T3 to write the data to memory.

Example 1: Opcode Fetch Only Problem:

An instruction 3EH (MVI A, data) is stored at address 1000H. Assume the clock frequency is 4 MHz. Calculate the time
taken to fetch this opcode.

Solution:

 Clock Period = 1 / 4 MHz = 0.25 µs

 Opcode fetch takes 4 T-states

Timing:
Execution time = 4 × 0.25 µs = 1 µs

Result:
Opcode 3EH is fetched from 1000H in 1 µs.

Example 2: Opcode Fetch + Memory Read Problem:

3E 9F is stored at 2000H and 2001H respectively. Instruction is MVI A, 9FH.
Find total execution time and explain memory activity.

Solution:

 3E is opcode for MVI A, data

 9F is the immediate data
 Two machine cycles:
o Opcode Fetch (from 2000H)
o Memory Read (fetch immediate from 2001H)

Timing:

 Opcode Fetch = 4T = 4 × 0.25 = 1 µs

 Memory Read = 3T = 3 × 0.25 = 0.75 µs
 Total = 1.75 µs

Result:
Register A holds 9F. Instruction executed in 1.75 µs.

Example 3: Memory Write Cycle Problem:

HL = 2350H, A = 9FH, Opcode 77H at 2003H (LD (HL), A)
Find timing and memory activity.

Solution:

 Opcode Fetch from 2003H (77H)

 Memory Write: write 9FH from A to 2350H

Timing:

 Opcode Fetch = 4T = 1 µs
 Memory Write = 3T = 0.75 µs
 Total = 1.75 µs
Result:
9F is written into memory location 2350H.

Example 4: Immediate Memory Store Problem:

Store value 56H into memory 2200H using instruction STA 2200H.
Opcode for STA is 32H, followed by address bytes (00H, 22H).
Assume memory from 3000H.

Memory Layout:

 3000H: 32H
 3001H: 00H
 3002H: 22H

A = 56H, Clock = 4 MHz

Solution:
STA requires 3 machine cycles:

1. Opcode fetch (32H)

2. Read low byte of address (00H)
3. Read high byte of address (22H)
4. Write data to 2200H

Timing:

 Opcode fetch = 4T = 1 µs
 Memory Read (2 × 3T) = 2 × 0.75 = 1.5 µs
 Memory Write = 3T = 0.75 µs
 Total = 3.25 µs

Result:
Memory location 2200H now contains 56H.

Example 5: Register-Memory Operation with Indirect Addressing

Problem:
Instruction LD A, (HL) — opcode 7EH at 2100H, HL = 3000H, memory at 3000H = 66H.
Find time taken and final content of A.

Solution:

 Opcode fetch (7EH) from 2100H

 Memory Read from 3000H

Timing:

 Opcode fetch = 4T = 1 µs
 Memory Read = 3T = 0.75 µs
 Total = 1.75 µs

Result:
Register A = 66H
2. Use an Instruction Set Table

Instruction tables (like in your image) show:

 Instruction format (e.g., ADD A, r)

 Byte size (how many bytes the instruction occupies in memory)
 Machine cycles (steps to execute the instruction)
 T-states (total clock cycles for execution)

3. Understanding the Format (e.g., 1/1/4)

This means:

 1 byte: Instruction length in memory

 1 machine cycle
 4 T-states (clock cycles)

4. Use Emulator Source Codes or Books

Example: Let’s say you want to find timing for ADD A, (IX+d)

You’d:

 Check the Z80 datasheet or online opcode table

 See it's 3 bytes (prefix + opcode + displacement)
 5 machine cycles
 19 T-states
  RD: Read signal (active low)
 WR: Write signal (active low)
 MREQ: Memory request signal (active low)
 MEMRD: Memory Read Enable
 MEMWR: Memory Write Enable

(a) Using Logic Gates

 AND gate (with inverted inputs):

o MEMRD = RD AND MREQ (both must be active low to generate MEMRD)
o MEMWR = WR AND MREQ

Why? These control signals are only valid when both MREQ and RD/WR are active.

(b) Using Decoder

 A 2-to-4 line decoder generates multiple outputs.

 Inputs: RD and WR as selection lines; MREQ as enable (E).
 When MREQ is active and RD/WR are appropriately selected:
o O1 → MEMRD
o O2 → MEMWR

� 4+ Examples

� Example 1: Generate MEMRD

Given:nMREQ = 0, RD = 0

Solution:

 Using logic: MEMRD = MREQ AND RD = 0 AND 0 = 0 → active (LOW)

 Decoder: MSB = 0 0 (binary) → O1 = MEMRD is activated

✅ MEMRD is asserted (active).

� Example 2: Generate MEMWR

Given:

 MREQ = 0, WR = 0

Solution:

 Using logic: MEMWR = MREQ AND WR = 0 AND 0 = 0 → active (LOW)

 Decoder: MSB = 1 0 → O2 = MEMWR is activated

✅ MEMWR is asserted.

� Example 3: Both RD and WR = 0

This is invalid. Microprocessors cannot read and write simultaneously.

Solution:
  Hardware should prevent this.
 No MEMRD or MEMWR should be activated.

✅ Conflict condition.

� Example 4: Idle Memory

Given:

 MREQ = 1, RD = 0, WR = 0

Solution:

 Using logic:
o MEMRD = 1 AND 0 = 1 → not active
o MEMWR = 1 AND 0 = 1 → not active

✅ Nothing is asserted, memory is idle.

Problem 1: When does MEMRD become active?

Given:
MREQ = 0, RD = 0, WR = 1

Solution:

 MEMRD = MREQ AND RD = 0

 MEMWR = MREQ AND WR = 1

MEMRD is active, MEMWR is not.

Problem 2: Can MEMRD and MEMWR both be 0?

Given:
MREQ = 0, RD = 0, WR = 0

Solution:

 MEMRD = 0
 MEMWR = 0
❗ Not allowed — violates processor operation: can’t read and write together.

Problem 3: Decoder Output Table

Use truth tables to avoid invalid states.

Problem 4: Design a Truth Table for Logic Circuit

Let’s define:

✅ Indicates valid logic behavior.

� Problem 5: Identify Invalid State

Given:
MREQ = 0, RD = 0, WR = 0

Question:
What happens in this situation?

Solution:

 MEMRD = MREQ AND RD = 0 AND 0 = 0 (active)

 MEMWR = MREQ AND WR = 0 AND 0 = 0 (active)

✅ This is invalid because a microprocessor cannot read and write at the same time.

Conclusion:
→ This state should be avoided in hardware design (use protection logic to avoid this condition).

� Problem 6: Decoder Output Identification

You are using a 2-to-4 decoder where:

 Enable = MREQ (active low)

 Inputs = RD, WR

Given:
MREQ = 0, RD = 1, WR = 0

Question:
Which output of the decoder is activated?

Solution:
Inputs (RD, WR) = 1, 0 = binary 10 → output O2

If O2 = MEMWR, then MEMWR is active.

✅ Answer: MEMWR is asserted (active low)

� Problem 7: Logic Circuit Analysis

Given:
You are using AND gates to generate MEMRD and MEMWR.

Inputs:

 MREQ = 1
 RD = 0
 WR = 1

Question:
What is the state of MEMRD and MEMWR?

Solution:

 MEMRD = MREQ AND RD = 1 AND 0 = 0

 MEMWR = MREQ AND WR = 1 AND 1 = 1

✅ MEMRD is active
✅ MEMWR is inactive

� Problem 8: Idle Bus Condition

Given:
All control lines are inactive:

 MREQ = 1
 RD = 1
 WR = 1

Question:
Is the memory being accessed?

Solution:

 MEMRD = 1 AND 1 = 1 → inactive

 MEMWR = 1 AND 1 = 1 → inactive

✅ The memory bus is idle (no read or write operation).

� Problem 9: Truth Table Construction

Construct a truth table for the following inputs:

MREQ, RD, WR
and determine MEMRD, MEMWR
Problem 10: Timing Conflict Resolution

Scenario:
A bus cycle mistakenly asserts both RD and WR (both = 0).

Question:
Design a logic circuit to prevent MEMWR from being active when RD is also active.

Solution: You can modify the logic as:

ini
CopyEdit
MEMWR = MREQ AND WR AND RD

Here, MEMWR will only activate when RD is not active.

Explanation:

 This ensures if RD = 0 (active), MEMWR = 0 (inactive), preventing a write.

❗ This logic enforces mutual exclusivity.

� Problem 11: Real-Time Check

A microprocessor sends these signals:

Question:
Track MEMRD and MEMWR across time.

Answer Table:
✅ You now have a time-based simulation.

What It Represents:

 1024 × 8 Memory Chip

o 1024 = number of memory locations
o 8 = bits per location (1 byte)
 This is 1 KB (kilobyte) of memory.
 Has 10 address lines (A0–A9) because 2;: = 1024
 I/O lines (8 bits) are used for data input or output.
 Control Signals:
o CS (Chip Select) – Enables the chip for use.
o RD (Read) – Triggers a read from memory.
o WR (Write) – Triggers a write to memory.

✅ Basic Operations

� Example 1: Write Operation

Given:

 CS = 0, RD = 1, WR = 0, Address = 0x03F, Data = 10101100

Action:
  The memory location 0x03F (decimal 63) will store the byte 10101100.

❗ Write successful

� Example 2: Read Operation

Given:

 CS = 0, RD = 0, WR = 1, Address = 0x1C0

Action:

 Data stored at memory address 0x1C0 will be put on the I/O bus (8 bits wide).

❗ Read complete

� Example 3: Invalid Condition

Given:

 CS = 0, RD = 0, WR = 0

Action:

 Both RD and WR active at once. ❗

✅ This is a logic conflict and must be avoided.

� Example 4: Idle Chip

Given:

 CS = 1, regardless of RD/WR

Action:

 The chip is disabled, and it ignores other control lines.

✅ Safe idle state.

� Problem 1: How many address lines are needed for a 1K × 8 memory chip?

Solution:

 1K = 1024 locations
 2^n=1024⇒n=102^n = 1024 \Rightarrow n = 102n=1024⇒n=10

❗ Answer: 10 address lines (A0–A9)

� Problem 2: Determine the data width of this chip

Solution:
  1024 × 8 → 8 bits per location

❗ Answer: 8-bit data width

� Problem 3: Memory Capacity in Bytes

Solution:

 1024 locations × 1 byte = 1024 bytes

 = 1 KB

❗ Answer: 1 KB

� Problem 4: If CS = 0, RD = 1, WR = 1, what happens?

Solution:

 Both RD and WR are inactive

 CS is active
 But no read or write is requested

❗ Answer: No operation

� Problem 5: Reading and Writing Example

Task: Write 11001100 to address 0x0A5, then read it back.

Steps:

1. Write:
o Set CS = 0, RD = 1, WR = 0
o Address bus = 0x0A5, Data = 11001100
2. Read:
o Set CS = 0, RD = 0, WR = 1
o Address bus = 0x0A5
o Data output on I/O = 11001100

❗ Correctly read what was written

� Problem 6: What happens if CS = 1?

Solution:

 Chip is not selected.

 No matter what RD/WR values are, the memory is inactive.

❗ No operation occurs

� Problem 7: How many bytes can be stored in a 4K × 8 chip?

Solution:

 4K = 4096 locations
  1 byte per location → 4096 bytes

❗ Answer: 4096 bytes (4 KB)

Example 1: Memory Read Timing

Problem:
The Z80 wants to read from memory address 2800H. What happens on the bus during this operation?

Solution:

1. Address Bus: A0–A15 carry 2800H.

2. High-order address (A8–A15) and low-order (A0–A7) stabilize early in the cycle.
3. MREQ goes LOW to indicate a memory request.
4. RD goes LOW to initiate a read.
5. MSEL goes LOW if address decoder recognizes 2800H range.
6. Memory places the byte on D0–D7.
7. CPU latches the data; then RD and MREQ go HIGH.

Result:
If memory at 2800H contains 3AH, Z80 reads 3AH.

Example 2: Memory Write Operation

Problem:
Write value 55H to memory location 3000H.

Solution:

1. A0–A15: Place 3000H.

2. D0–D7: Load data 55H.
3. MREQ goes LOW.
4. WR goes LOW to initiate write.
5. If 3000H is in range decoded by the memory chip, MSEL goes LOW.
6. Value 55H written into memory.
Result:
After the cycle, 55H is stored at 3000H.

Example 3: Address Decoding with 2K RAM (6116) at 2800H

Problem:
Use a 2K RAM starting at 2800H. Determine the address range and how to use a decoder to select it.

Solution:

 2K = 2048 bytes = 800H → Ends at 2FFFH.

 Address range: 2800H–2FFFH
 Decoder (like 74LS138) uses A15–A11:
o 2800H = 0010 1000 0000 0000
o Enable when A15–A11 = 00101
 Use A15–A13 and gates to generate chip select (MSEL) when in this range.

Result:
Proper chip select only active for 2800H–2FFFH; avoids mirroring.

Example 4: Z80 Fetches LD A, 9FH

Problem:
Opcode 3E 9F at address 0000H. Describe the fetch cycle.

Solution:

 Instruction: LD A, 9FH → 3E is opcode, 9F is data.

1. Cycle 1 (Opcode Fetch):

o A0–A15 = 0000H, MREQ + RD go LOW.
o Data bus: 3E
2. Cycle 2 (Memory Read):
o A0–A15 = 0001H, MREQ + RD LOW.
o Data bus: 9F

Result:
A register gets loaded with 9F.

Example 5: What if Decoder is Incorrect

Problem:
If a memory chip is supposed to respond to 2800H–2FFFH but decoder enables it for all 2XXXH addresses (partial decoding), what
happens?

Solution:

 All addresses like 2000H, 2400H, 2C00H will select same chip.
 Multiple logical addresses map to the same physical chip = memory mirroring.

Result:
Accessing 2000H may overwrite data at 2800H — leads to unexpected bugs.
Example 6: Design Memory Map with EPROM and RAM

Problem:
Design a memory map for the Z80 with:

 4K EPROM (2732) starting at 0000H

 2K RAM (6116) starting at F800H

Solution:

 EPROM 2732 → 4K = 1000H → address range: 0000H–0FFFH

 RAM 6116 → 2K = 0800H → address range: F800H–FFFFH

Address decoding:

 For EPROM (0000H–0FFFH): A15–A12 = 0000

o Use decoder that outputs low when A15–A12 = 0000
 For RAM (F800H–FFFFH): A15–A11 = 11111
o Use A15–A11 = 11111 to select RAM

Result:

 EPROM is enabled only in 0000H–0FFFH

 RAM is enabled only in F800H–FFFFH

Example 7: Interface Two 8K RAMs (6264)

Problem:
You have two 8K RAMs. Place one at 8000H and one at A000H. Design the address decoding.

Solution:

 8K = 2000H
 RAM1 → 8000H–9FFFH → A15–A13 = 100
 RAM2 → A000H–BFFFH → A15–A13 = 101

Use 74LS138 decoder:

 Connect A15–A13 to inputs A, B, C of 74LS138

 RAM1 → output Y4 (when input = 100)
 RAM2 → output Y5 (when input = 101)

Result:
Each RAM chip is uniquely selected without overlap or mirroring.

Example 8: Identify Memory Chip with Incomplete Decoding

Problem:
You notice that writing to 1000H, 3000H, and 5000H affects the same memory location. Why?

Solution:

 These addresses differ in A13–A15 but share lower address bits.

  Suggests decoder uses only A12–A0 → only 13-bit decoding
 Memory chip sees all as same address due to ignored high-order bits

Result:
Memory mirroring is occurring. Use full decoding to avoid ambiguity.

Example 9: Read Timing Violation Issue

Problem:
A Z80 system fails to read from a slow EPROM. What could be the problem?

Solution:

 EPROM access time (e.g., 450ns) might be longer than Z80 read window (~250ns)
 Timing diagram shows data from memory must stabilize before RD rises
 If data is late → CPU reads invalid byte

Solution:

 Insert wait states

 Use READY pin to delay CPU during slow memory read

Result:
Valid data is read. System becomes stable.

Example 10: Design with Mixed ROM and RAM Using 74LS138

Problem:
Design a system with:

 8K ROM at 0000H
 8K RAM at 2000H
 8K RAM at 4000H

Solution:

 Each block = 8K = 2000H

 ROM → 0000H–1FFFH → A15–A13 = 000
 RAM1 → 2000H–3FFFH → A15–A13 = 001
 RAM2 → 4000H–5FFFH → A15–A13 = 010

Use 74LS138:

 Inputs: A15–A13 → connected to A, B, C

 Y0 → ROM, Y1 → RAM1, Y2 → RAM2

Result:
All devices mapped without conflict. Only one MSEL active at a time.