• Basic state transitions

• Machine Cycle and Instruction cycles

• Timing diagram
• Data transfer instructions
 Basic State Transitions
• MP operates sequentially into two states:
- Fetch
- Execution
• Fetch:
- Carry all current instruction bytes and enters
into execution states
• Execution
- Arithmetic
- logical
- Data transfer
- Decision making operations
 Machine Cycles
• Time period/number of T-state required to
access a peripheral is called a machine cycle.
• Instructions are stored sequentially in
memory.
• The opcode is executed by MP
• To execute an instruction MP first takes the
opcode from memory (opcode fetch).
• Then, this instruction is decoded by
instruction decoder
• After this MP performs the operation.
• In 2 bytes instruction MP works in two steps:
1. Fetches the opcode and decodes it
- After decoding the instruction, MP comes to
know second byte of the instruction.
2. To get the second byte from memory, MP
performs the memory read cycle
- Then the MP executes the instruction.
• If the instruction is of three bytes
- MP will execute another memory read cycle.
• All these operations are performed in order
with respect to the clock.
• MP performs an operation in a specific time
period called
- Clock cycles
 T-State and Machine Cycle
• T-state is the time period of a single cycle of
the clock frequency.
• Access a peripheral
- Perform a read or write operation
- From memory or from an IO.
• Machine cycle may consists of three to six T-
states.
• 8085 requires only 3 T-states to access
peripheral.
• In case of fetch cycle
- 8085 requires additional time to decode an
instruction
- So fetch cycle requires 4 to 6 T-states.
 Instruction Cycle
• Total number of machine cycles required to
execute a complete instruction or,
• Number of machine cycles required to fetch
and execute an instruction
• Instruction Cycle = Fetch Cycle + Execute Cycle
• In 8085, an instruction cycle consists of one to
five machine cycles.
• Each machine cycle consists of many clock
periods (T-States)
• Machine cycles are classified as per the MP
operations.
• There are eight different operations and thus
eight machine cycles.
 Timing Diagram
• Display of initiation of R/W and transfer of
data under the control of 3-status signals:
- IO/M
- S1
- S0
 Machine Cycles
• Opcode fetch cycle
• Operand fetch cycle
• Memory read cycle
• Memory write cycle
• I/O read cycle
• I/O write cycle
• Interrupt acknowledge cycle
• Idle machine cycle
 Opcode fetch cycle

• MP uses this cycle to take the opcode of an

instruction.
• The address of the memory location is given
by Program Counter.
• This is the first cycle of any instruction cycle.
• The opcode is taken from the memory
• Transferred to the instruction register for
decoding and execution.
• The status of IO/M line is low
• Time required for complete cycle: 4-6 T-states.
 Operand fetch cycle

• In 2-and 3-byte instructions opcode does not

complete instruction fetching
• Hence requires operand fetch cycles.
• For 2-byte instructions require one operand
fetch cycle
• For 3-byte instructions require two operand
fetch cycles.
• In fetch cycle, the address/data instruction are
fetched
- But the contents are not transferred to
instruction register
- Instead they are stored in temporary registers.
• The status of IO/M line is low
• Time required to complete the operand fetch
cycle is 3T-states.
 Memory read cycle

• The MP executes these cycles to read data

from memory.
• The address of the memory location is given
by instructions.
• The PC is not used, instead, instruction will
give address or
• Specify where the address is located
• The status of IO/M line is low.
• Time required to complete 3T-states.
 Memory write cycle
• MP executes these cycles to write data of
memory.
• The address of memory is given by the
instructions.
• The status of IO/M is low
• Time required to complete the memory write
cycle is 3T-states.
 I/O read cycle

• MP executes to read data from I/O device

instead of memory.
• The status of IO/M line is high
• Address of the port is given by instruction.
• Time required to complete the cycle: 3T states.
 I/O write cycle

• Write or send data to I/O device

• The status of IO/M line is high
• Address of the port is given by instruction
• Time required to complete the cycle: 3T states.
 Interrupt acknowledge cycle

• To get information from the interrupting

device.
• Time required to complete the interrupt
acknowledge cycle is 3T-states.
 Idle machine cycle
• For internal execution
• All data address and control lines are tri-stated.
• i.e. MP does not perform any external
operations.
• Time required to complete: 3T-states
 Timing Diagram

• The graphical representation of the status of

the various signals involved during a machine
cycle, with respect to time (clock), is called
timing diagram.
• Gives basic idea on:
- When the instruction is getting fetched
- Executed
- Which signal is getting activated
 One byte instructions
• MOV C, A (Copy) 0100 111 4FH
• ADD B 1000 0000 80H
• CMA (Compliment or invert)
 Two byte instructions
• MVI A, 35H (Load) 0011 1110 4FH
0011 0101
35H
Three byte instructions
JMP 2550H 1100 0011 C3
0101 0000 50
0011 0101 25
 Immediate addressing
• MVI A, 05H: Move 05H in the accumulator
• ADI 06H: Add 06H to the contents of the
accumulator
• LXI H, 2500H: Load HL pair with 2500H
 Register addressing
MOV A,B
ADD B
Direct Addressing
STA 2400H (Store)
IN 02H (Input the data)
Register Indirect addressing
LXI H, 2500H Load HL pair with 2500H
MOV A,M
HLT
• Implicit addressing
CMA: Compliment the contents of the ‘A’
RAR: Rotate the contents of the ‘A’ right by one
bit
RAL: Rotate the contents of the ‘A’ left by one bit
• Data transfer (Copy) operations
A data can be available at:
1. Immediate available (Im)
2. Some memory (M)
3. Some register (R)
4. Some IO
Data available Data to transfer
Im (immediate) R, M
R R, M
M R
IO A
A IO
 Branching operations
JMP: Jump within a program
CALL: Jump from main program to subroutine
RET: Jump from sub-routine to main program
RST: Jump from main program
 Data transfer instructions
1. MOV Rd, Rs; MOV Rd, M; MOV M, B
(Copy from source to destination)
2. MVI Rd, data; M, data
(Move immediate- 8 bit)
3. LXI register pair, 16-bit data
(Load register pair immediate)
4. LDA 10-bit address
(Load ‘A’ direct)
5. LDAX B/D register pair
(Load ‘A’ indirect)
6. STA- 16-bit address:
(Store ‘A’ direct)
7. STAX register pair
(Store ac ‘A’ indirect)
8. LHLD 16 bit address
(Load H and L registers direct)
9. SHLD 16 bit address
(Store H and L registers direct)
10. XCHG
(Exchange H and L with D and E)
11. SPHL
(Copy H and L registers to the stack pointer)
12. PCHL (Copy H and L registers to the program
counter)
13. XTHL (Exchange H and L with top of stack)
14. PUSH register pair (Push registers pair onto
stack)
15.POP register pair (Pop off stack to register pair)
16. OUT 8-bit port address (Output data from ‘A’
to a port with 8-bit address)
17. IN 8-bit port address (Input data to ‘A’ from a
port with 8-bit address)
Arithmetic instructions
1. ADD R; M (Add register or memory to ‘A’)
2. ADC R; M (Add register to ‘A’ with carry)
3. ADI 8-bit data: Add immediate to ‘A’
4. ACI 8-bit data: Add immediate to ‘A’ with carry
5. DAD register pair/SP: Add register pair to H
and L registers
6. DAA: Decimal adjust ‘A’
7. SUB R; M: Subtract register or memory from
‘A’
8. SBB R; M: Subtract source and borrow from ‘A’
9. SUI 8-bit data: Subtract immediate from ‘A’
10. SBI 8-bit data: Subtract immediate from ‘A’
with borrow
11. INR R; M: Increment register or memory by 1
12. INX Rp: Increment register pair by 1
13. DCR R; M: Decrement register or memory by
1
14. DCX Rp: Decrement register pair by 1
 Logical instructions
1. CMP R; M: Compare register or memory with
accumulator
If (A) (reg/mem): carry flag is set
If (A)= (reg/mem): zero flag is set
If (A) (reg/mem): carry and zero flags are reset
2. CPI 8-bit data: Compare immediate with ‘A’
If (A)  data: carry flag is set
If (A)= data: zero flag is set
If (A) data: carry and zero flags are reset
3. ANA R; M: Logical AND register or memory
with ‘A’
4. ANI 8-bit data: Logical AND immediate with ‘A’
5. XRA R; M: Exclusive OR register or memory
with ‘A’
6. XRI 8-bit data: Exclusive OR immediate with
‘A’
7. ORA R; M: Logical OR register or memory with
‘A’
8. ORI 8-bit data: Logical OR immediate with ‘A’
9. CMA: Complement ‘A’
10. RLC: Rotate ‘A’ left
11. RRC: Rotate ‘A’ right
12. RAL: Rotate ‘A’ left through carry
13. RAR: Rotate ‘A’ right through carry
14. CMC: Complement carry
15. STC: Set carry
Branching Instructions
1. JMP 16-bit address: Jump unconditionally
2. Jump conditionally: Jump if condition true
3. CALL 16-bit address: Unconditional
subroutine call
4. Call conditionally: Call if condition true
5. RET: Return from subroutine unconditionally
6. Return from subroutine conditionally: Return
if condition true
7. PCHL: Load program counter with HL contents
8. RST 0-7: Restart
 Machine control instructions
1. NOP: No operation
2. HLT: Halt
3. DI: Disable interrupts
4. EI: Enable interrupts
5. RIM: Read interrupt mask
6. SIM: Set interrupt mask
• MOVE, LOAD AND STORE
MOV r1, r2: Move register to register
MOV M, r: Move register to memory
MVI r: Move immediate register
MVI M: Move immediate memory
LXI B: Load immediate register pair B and C
LXI D: Load immediate register pair D and E
LXI H: Load immediate register pair H and L
LXI SP : Load immediate stack pointer
STAX B : Store A indirect
LDAX B : Load A indirect
STA : Store A direct
LDA : Load A direct
SHLD : Store H and L direct
LHLD : Load H and L direct
XCHG : Exchange registers
PUSH B : Push register pair B and C on stack
PUSH D : Push register pair D and E on stack
PUSH H : Push register pair H and L on stack
PUSH PSW : Push A and flags on stack
POP B : Pop register pair B and C off stack
POP D : Pop register pair D and E off stack
POP H : Pop register pair H and L off stack
POP PSW : Pop A and flags off stack
XTHL : Exchange top of stack H and L
SPHL : H and L to stack pointer
JUMP
JMP : Jump unconditional
JC : Jump on carry
JNC : Jump on no carry
JZ : Jump on zero
JNZ : Jump on no zero
JP : Jump on positive
JM : Jump on minus
JPE : Jump on parity even
JPO : Jump on parity odd
PCHL : H and L to program counter
CALL
CALL : Call unconditional
CC : Call on carry
CNC : Call on no carry
CZ : Call on zero
CNZ : Call on no zero
CP : Call on positive
CM : Call on minus
CPE : Call on parity even
CPO : Call on parity odd
RETURN
RET : Return
RC : Return on carry
RNC : Return on
RZ : Return on zero
RNZ : Return on no zero
RP : Return on positive
RM : Return on minus
RPE : Return on parity even
RPO : Return on parity odd
INCREMENT AND DECREMENT
INR r : Increment register
DCR r : Decrement register
INR M : Increment memory
INX B : Increment B and C registers
INX : Increment stack pointer
CPI : Comparer immediate with A
RLC : Rotate A left
RRC : Rotate A right
RAL : Rotate A left through carry
RAR : Rotate A right through carry
CMA : Complement A
STC : Set carry
CMC : Complement carry
DAA : Decimal adjust A
ADD
ADD r : Add register to A
ADC r : Add register to A with carry
ADD M : Add memory to A
ADC M : Add memory to A with carry
ADI : Add immediate to A
DAD : B Add B and C to H and L
DAD : D Add D and E to H and L
DAD : SP Add stack pointer to H and L
SUBTRACT
SUB r : Subtract register from A
SBB r : Subtract register from A with borrow
SUB M : Subtract memory from A
SBB M : Subtract memory from A with borrow
SUI : Subtract immediate from A
SBI : Subtract immediate from A with borrow
LOGICAL
ANA r : Add register with A
XRA r : Exclusive OR register with A
ORA r : OR register with A
CMP r : Comparer register with A
ANA M : Add memory with A
XRA M : Exclusive OR memory with A
ORA M : OR memory with A
CMP M : Comparer memory with A
ANI : Add immediate with A
XRI Exclusive OR immediate with A
ORI OR : Immediate with A