8051 MICROCONTROLLERS

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Microcontrollers and embedded
OUTLINES
processors
‰ Overview of the 8051 family

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 ‰ General-purpose microprocessors
MICRO-
CONTROLLERS
contains
AND ¾ No RAM
EMBEDDED ¾ No ROM
PROCESSORS ¾ No I/O ports

Microcontroller
‰ Microcontroller has
vs. General- ¾ CPU (microprocessor)
Purpose ¾ RAM
Microprocessor ¾ ROM
¾ I/O ports
¾ Timer Serial Communication Interface,

ADC and other peripherals

PWM etc.
¾

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 Data bus
MICRO- General-
purpose
CONTROLLERS Micro-
Processor I/O Serial
AND RAM ROM
Port
Timer COM
Port
EMBEDDED
PROCESSORS CPU
Address bus

Microcontroller
vs. General- integrated into single chip
Purpose Microcontroller
Microprocessor CPU RAM ROM
(cont’)

Serial
I/O Timer COM
Port

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 ‰ General-purpose microprocessors
MICRO-
¾ Must add RAM, ROM, I/O ports, and
CONTROLLERS timers externally to make them functional
AND ¾ Make the system bulkier and much more
EMBEDDED expensive
PROCESSORS ¾ Have the advantage of versatility on the
amount of RAM, ROM, and I/O ports
Microcontroller ‰ Microcontroller
vs. General- ¾ The fixed amount of on-chip ROM, RAM,
Purpose and number of I/O ports makes them ideal
Microprocessor for many applications in which cost and
(cont’) space are critical
¾ In many applications, the space it takes,
the power it consumes, and the price per
unit are much more critical considerations
than the computing power

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 ‰ An embedded product uses a
MICRO- microprocessor (or microcontroller) to
CONTROLLERS do one task and one task only
AND
¾ There is only one application software that
EMBEDDED
is typically burned into ROM
PROCESSORS
‰ A PC, in contrast with the embedded
Microcontrollers system, can be used for any number of
for Embedded applications
Systems ¾ It has RAM memory and an operating
system that loads a variety of applications
into RAM and lets the CPU run them
¾ A PC contains or is connected to various
embedded products
ƒ Each one peripheral has a microcontroller inside
it that performs only one task

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 ‰ Home
MICRO- ¾ Appliances, intercom, telephones, security systems,
CONTROLLERS garage door openers, answering machines, fax
AND machines, home computers, TVs, cable TV tuner,
VCR, camcorder, remote controls, video games,
EMBEDDED cellular phones, musical instruments, sewing
PROCESSORS machines, lighting control, paging, camera, pinball
machines, toys, exercise equipment
Microcontrollers ‰ Office
for Embedded ¾ Telephones, computers, security systems, fax
Systems machines, microwave, copier, laser printer, color
printer, paging
(cont’)
‰ Auto
¾ Trip computer, engine control, air bag, ABS,
instrumentation, security system, transmission
control, entertainment, climate control, cellular
phone, keyless entry

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 ‰ Many manufactures of general-purpose
MICRO- microprocessors have targeted their
CONTROLLERS microprocessor for the high end of the
AND
embedded market
EMBEDDED
¾ There are times that a microcontroller is
PROCESSORS
inadequate for the task
x86 PC ‰ When a company targets a general-
Embedded purpose microprocessor for the
Applications embedded market, it optimizes the
processor used for embedded systems
‰ Very often the terms embedded
processor and microcontroller are used
interchangeably

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 ‰ One of the most critical needs of an
MICRO- embedded system is to decrease
CONTROLLERS power consumption and space
AND
EMBEDDED ‰ In high-performance embedded
PROCESSORS processors, the trend is to integrate
more functions on the CPU chip and let
x86 PC designer decide which features he/she
Embedded wants to use
Applications ‰ In many cases using x86 PCs for the
(cont’)
high-end embedded applications
¾ Saves money and shortens development
time
ƒ A vast library of software already written
ƒ Windows is a widely used and well understood
platform
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 ‰ 8-bit microcontrollers
MICRO-
CONTROLLERS ¾ Motorola’s 6811
AND ¾ Intel’s 8051
EMBEDDED ¾ Zilog’s Z8
PROCESSORS ¾ Microchip’s PIC

Choosing a ‰ There are also 16-bit and 32-bit

Microcontroller microcontrollers made by various chip
makers

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 ‰ Meeting the computing needs of the
MICRO-
CONTROLLERS
task at hand efficiently and cost
AND effectively
EMBEDDED ¾ Speed
PROCESSORS ¾ Packaging
¾ Power consumption
Criteria for
¾ The amount of RAM and ROM on chip
Choosing a
Microcontroller ¾ The number of I/O pins and the timer on
chip
¾ How easy to upgrade to higher-
performance or lower power-consumption
versions
¾ Cost per unit

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 ‰ Availability of software development
MICRO- tools, such as compilers, assemblers,
CONTROLLERS and debuggers
AND
EMBEDDED ‰ Wide availability and reliable sources
PROCESSORS of the microcontroller
¾ The 8051 family has the largest number of
Criteria for diversified (multiple source) suppliers
Choosing a ƒ Intel (original)
ƒ Atmel
Microcontroller
(cont’) ƒ Philips/Signetics
ƒ AMD
ƒ Infineon (formerly Siemens)
ƒ Matra
ƒ Dallas Semiconductor/Maxim

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 ‰ Intel introduced 8051, referred as MCS-
OVERVIEW OF 51, in 1981
8051 FAMILY ¾ The 8051 is an 8-bit processor
ƒ The CPU can work on only 8 bits of data at a
time
8051
Microcontroller ¾ The 8051 had
ƒ 128 bytes of RAM
ƒ 4K bytes of on-chip ROM
ƒ Two timers
ƒ One serial port
ƒ Four I/O ports, each 8 bits wide
ƒ 6 interrupt sources
‰ The 8051 became widely popular after
allowing other manufactures to make
and market any flavor of the 8051, but
remaining code-compatible
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 External
Interrupts
OVERVIEW OF
8051 FAMILY

Counter Inputs
On-chip
Interrupt ROM On-chip Etc.
Control Timer 0
8051 for code RAM Timer 1
Microcontroller
(cont’)
CPU

OSC Bus I/O Serial

Control Ports Port

P0 P1 P2 P3 TXD RXD

Address/Data

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 ‰ The 8051 is a subset of the 8052
OVERVIEW OF
8051 FAMILY ‰ The 8031 is a ROM-less 8051
¾ Add external ROM to it
8051 Family ¾ You lose two ports, and leave only 2 ports
for I/O operations

Feature 8051 8052 8031

ROM (on-chip program
4K 8K 0K
space in bytes)
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

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 ‰ 8751 microcontroller
OVERVIEW OF
8051 FAMILY ¾ UV-EPROM
ƒ PROM burner
Various 8051 ƒ UV-EPROM eraser takes 20 min to erase
Microcontrollers ‰ AT89C51 from Atmel Corporation
¾ Flash (erase before write)
ƒ ROM burner that supports flash
ƒ A separate eraser is not needed
‰ DS89C4x0 from Dallas Semiconductor,
now part of Maxim Corp.
¾ Flash
ƒ Comes with on-chip loader, loading program to
on-chip flash via PC COM port

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 ‰ DS5000 from Dallas Semiconductor
OVERVIEW OF
8051 FAMILY ¾ NV-RAM (changed one byte at a time),
RTC (real-time clock)
Various 8051 ƒ Also comes with on-chip loader
Microcontrollers ‰ OTP (one-time-programmable) version
(cont’) of 8051
‰ 8051 family from Philips
¾ ADC, DAC, extended I/O, and both OTP
and flash

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 8051 ASSEMBLY
LANGUAGE
PROGRAMMING

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Register are used to store information
INSIDE THE
8051
temporarily, while the information
could be
Registers ¾ a byte of data to be processed, or
¾ an address pointing to the data to be
fetched
‰ The vast majority of 8051 register are
8-bit registers
¾ There is only one data type, 8 bits

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 ‰ The 8 bits of a register are shown from
INSIDE THE
8051
MSB D7 to the LSB D0
¾ With an 8-bit data type, any data larger
Registers than 8 bits must be broken into 8-bit
(cont’) chunks before it is processed
most least
significant bit significant bit

D7 D6 D5 D4 D3 D2 D1 D0

8 bit Registers

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 ‰ The most widely used registers
INSIDE THE
8051 ¾ A (Accumulator)
ƒ For all arithmetic and logic instructions
Registers ¾ B, R0, R1, R2, R3, R4, R5, R6, R7
(cont’) ¾ DPTR (data pointer), and PC (program
counter)
DPTR holds the address of DATA in memory
A
B
R0 DPTR DPH DPL
R1
R2
PC PC (Program counter)
R3
R4
R5 holds the address of the next instruction to
be executed
R6
R7

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 MOV destination, source ;copy source to dest.
INSIDE THE ¾ The instruction tells the CPU to move (in reality,
8051 COPY) the source operand to the destination
operand
MOV “#” signifies that it is a value
Instruction
MOV A,#55H ;load value 55H into reg. A
MOV R0,A ;copy contents of A into R0
;(now A=R0=55H)
MOV R1,A ;copy contents of A into R1
;(now A=R0=R1=55H)
MOV R2,A ;copy contents of A into R2
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3 ;copy contents of R3 into A
;now A=R3=95H

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 ‰ Notes on programming
INSIDE THE ¾ Value (proceeded with #) can be loaded
8051 directly to registers A, B, or R0 – R7
ƒ MOV A, #23H
MOV ƒ MOV R5, #0F9H If it’s not preceded with #,
Instruction Add a 0 to indicate that
it means to load from a
memory location
(cont’) F is a hex number and
not a letter
for clarity, not comuplsory

¾ If values 0 to F moved into an 8-bit

register, the rest of the bits are assumed
all zeros
ƒ “MOV A, #5”, the result will be A=05; i.e., A
= 00000101 in binary
¾ Moving a value that is too large into a
register will cause an error
ƒ MOV A, #7F2H ; ILLEGAL: 7F2H>8 bits (FFH)
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 ADD A, source ;ADD the source operand
INSIDE THE ;to the accumulator
8051 ¾ The ADD instruction tells the CPU to add the source
byte to register A and put the result in register A
ADD ¾ Source operand can be either a register or
immediate data, but the destination must always
Instruction be register A
ƒ “ADD R4, A” and “ADD R2, #12H” are invalid
since A must be the destination of any arithmetic
operation
MOV A, #25H ;load 25H into A
MOV R2, #34H ;load 34H into R2
ADD A, R2 ;add R2 to Accumulator
There are always ;(A = A + R2)
many ways to write
the same program, MOV A, #25H ;load one operand
depending on the ;into A (A=25H)
registers used ADD A, #34H ;add the second
;operand 34H to A
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 ‰ In the early days of the computer,
8051 programmers coded in machine language,
ASSEMBLY consisting of 0s and 1s
PROGRAMMING ¾ Tedious, slow and prone to error
‰ Assembly languages, which provided
Structure of
mnemonics for the machine code instructions,
Assembly
plus other features, were developed
Language
¾ An Assembly language program consist of a series
of lines of Assembly language instructions
‰ Assembly language is referred to as a low-
level language
¾ It deals directly with the internal structure of the
CPU

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 ‰ Assembly language instruction includes
8051 ¾ a mnemonic (abbreviation easy to remember)
ASSEMBLY ƒ the commands to the CPU, telling it what those
PROGRAMMING to do with those items
¾ optionally followed by one or two operands
Structure of ƒ the data items being manipulated
Assembly
‰ A given Assembly language program is
Language
a series of statements, or lines
¾ Assembly language instructions
ƒ Tell the CPU what to do
¾ Directives (or pseudo-instructions)
ƒ Give directions to the assembler

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 ‰ An Assembly language instruction
8051
ASSEMBLY consists of four fields:
PROGRAMMING [label:] Mnemonic [operands] [;comment]

ORG 0H ;start(origin) at location

Structure of 0
MOV R5, #25H ;load 25H into R5
Assembly MOV R7, #34H ;load 34H into R7
Directives do not
Language MOV A, #0 ;load 0 into generate
A any machine
ADD A, R5 ;add contentscode
ofandR5aretoused
A
;now A = A + only
R5 by the assembler
Mnemonics ADD A, R7 ;add contents of R7 to A
produce ;now A = A + R7
opcodes ADD A, #12H ;add to A value 12H
;now A = A + 12H
HERE: SJMP HERE ;stay in this loop
END ;endComments
of asm may
source file
be at the end of a
The label field allows line or on a line by themselves
the program to refer to a The assembler ignores comments
line of code by name
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 ‰ The step of Assembly language
ASSEMBLING
AND RUNNING
program are outlines as follows:
AN 8051 1) First we use an editor to type a program,
PROGRAM many excellent editors or word
processors are available that can be used
to create and/or edit the program
ƒ Notice that the editor must be able to produce
an ASCII file
ƒ For many assemblers, the file names follow
the usual DOS conventions, but the source file
has the extension “asm“ or “src”, depending
on which assembly you are using

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 2) The “asm” source file containing the
ASSEMBLING program code created in step 1 is fed to
AND RUNNING an 8051 assembler
AN 8051 ƒ The assembler converts the instructions into
PROGRAM machine code
(cont’) ƒ The assembler will produce an object file and
a list file
ƒ The extension for the object file is “obj” while
the extension for the list file is “lst”
3) Assembler require a third step called
linking
ƒ The linker program takes one or more object
code files and produce an absolute object file
with the extension “abs”
ƒ This abs file is used by 8051 trainers that
have a monitor program

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 4) Next the “abs” file is fed into a program
ASSEMBLING called “OH” (object to hex converter)
AND RUNNING which creates a file with extension “hex”
AN 8051 that is ready to burn into ROM
PROGRAM ƒ This program comes with all 8051 assemblers
(cont’)
ƒ Recent Windows-based assemblers combine
step 2 through 4 into one step

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 EDITOR
PROGRAM
ASSEMBLING [Link]
AND RUNNING
AN 8051 ASSEMBLER
PROGRAM PROGRAM
[Link]
Other obj files
Steps to Create [Link]

a Program LINKER
PROGRAM

[Link]

OH
PROGRAM

[Link]
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 ‰ The lst (list) file, which is optional, is
ASSEMBLING
AND RUNNING
very useful to the programmer
AN 8051 ¾ It lists all the opcodes and addresses as
PROGRAM well as errors that the assembler detected
¾ The programmer uses the lst file to find
lst File the syntax errors or debug
1 0000 ORG 0H ;start (origin) at 0
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE;stay in this loop
9 000C END ;end of asm source file
address
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 ‰ The program counter points to the
PROGRAM
COUNTER AND
address of the next instruction to be
ROM SPACE executed
¾ As the CPU fetches the opcode from the
Program program ROM, the program counter is
Counter increasing to point to the next instruction
‰ The program counter is 16 bits wide
¾ This means that it can access program
addresses 0000 to FFFFH, a total of 64K
bytes of code

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 ‰ All 8051 members start at memory
PROGRAM
COUNTER AND
address 0000 when they’re powered
ROM SPACE up
¾ Program Counter has the value of 0000
Power up ¾ The first opcode is burned into ROM
address 0000H, since this is where the
8051 looks for the first instruction when it
is booted
¾ We achieve this by the ORG statement in
the source program

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 ‰ Examine the list file and how the code
PROGRAM is placed in ROM
COUNTER AND 1 0000 ORG 0H ;start (origin) at 0

ROM SPACE
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
Placing Code in ;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
ROM ;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE ;stay in this loop
9 000C END ;end of asm source file

ROM Address Machine Language Assembly Language

0000 7D25 MOV R5, #25H
0002 7F34 MOV R7, #34H
0004 7400 MOV A, #0
0006 2D ADD A, R5
0007 2F ADD A, R7
0008 2412 ADD A, #12H
000A 80EF HERE: SJMP HERE

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 ‰ After the program is burned into ROM,
PROGRAM
COUNTER AND
the opcode and operand are placed in
ROM SPACE ROM memory location starting at 0000
ROM contents
Address Code
Placing Code in
0000 7D
ROM 0001 25
(cont’) 0002 7F
0003 34
0004 74
0005 00
0006 2D
0007 2F
0008 24
0009 12
000A 80
000B FE

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 ‰ A step-by-step description of the
PROGRAM
COUNTER AND
action of the 8051 upon applying
ROM SPACE power on it
1. When 8051 is powered up, the PC has
Executing 0000 and starts to fetch the first opcode
Program from location 0000 of program ROM
ƒ Upon executing the opcode 7D, the CPU
fetches the value 25 and places it in R5
ƒ Now one instruction is finished, and then the
PC is incremented to point to 0002, containing
opcode 7F
2. Upon executing the opcode 7F, the value
34H is moved into R7
ƒ The PC is incremented to 0004

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 ‰ (cont’)
PROGRAM
COUNTER AND 3. The instruction at location 0004 is
ROM SPACE executed and now PC = 0006
4. After the execution of the 1-byte
Executing instruction at location 0006, PC = 0007
Program 5. Upon execution of this 1-byte instruction
(cont’) at 0007, PC is incremented to 0008
ƒ This process goes on until all the instructions
are fetched and executed
ƒ The fact that program counter points at the
next instruction to be executed explains some
microprocessors call it the instruction pointer

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 ‰ No member of 8051 family can access
PROGRAM
COUNTER AND
more than 64K bytes of opcode
ROM SPACE ¾ The program counter is a 16-bit register

ROM Memory Byte Byte Byte

Map in 8051 0000 0000 0000

Family
0FFF
8751
AT89C51 3FFF
DS89C420/30

7FFF
DS5000-32

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 ‰ 8051 microcontroller has only one data
8051 DATA
TYPES AND
type - 8 bits
DIRECTIVES ¾ The size of each register is also 8 bits
¾ It is the job of the programmer to break
Data Type down data larger than 8 bits (00 to FFH,
or 0 to 255 in decimal)
¾ The data types can be positive or negative

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 ‰ The DB directive is the most widely
8051 DATA
TYPES AND
used data directive in the assembler
DIRECTIVES ¾ It is used to define the 8-bit data
¾ When DB is used to define data, the
Assembler numbers can be in decimal, binary, hex,
The “D” after the decimal
Directives ASCII formats number is optional, but using
“B” (binary) and “H”
ORG 500H (hexadecimal) for the others is
required
DATA1: DB 28 ;DECIMAL (1C in Hex)
DATA2: DB 00110101B ;BINARY (35 in Hex)
DATA3: DB 39H ;HEX
The Assembler will ORG 510H Place ASCII in quotation marks
convert the numbers DATA4: DB “2591” The;ASCII
AssemblerNUMBERS
will assign ASCII
into hex code for the numbers or characters
ORG 518H
DATA6: DB “My name is Joe”
Define ASCII strings larger ;ASCII CHARACTERS
than two characters

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 ‰ ORG (origin)
8051 DATA ¾ The ORG directive is used to indicate the
TYPES AND beginning of the address
DIRECTIVES ¾ The number that comes after ORG can be
either in hex and decimal
Assembler ƒ If the number is not followed by H, it is decimal
Directives and the assembler will convert it to hex
(cont’) ‰ END
¾ This indicates to the assembler the end of
the source (asm) file
¾ The END directive is the last line of an
8051 program
ƒ Mean that in the code anything after the END
directive is ignored by the assembler

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 ‰ EQU (equate)
8051 DATA
TYPES AND ¾ This is used to define a constant without
DIRECTIVES occupying a memory location
¾ The EQU directive does not set aside
Assembler storage for a data item but associates a
directives constant value with a data label
(cont’) ƒ When the label appears in the program, its
constant value will be substituted for the label

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 ‰ EQU (equate) (cont’)
8051 DATA
TYPES AND ¾ Assume that there is a constant used in
DIRECTIVES many different places in the program, and
the programmer wants to change its value
Assembler throughout
ƒ By the use of EQU, one can change it once and
directives
the assembler will change all of its occurrences
(cont’)
Use EQU for the
counter constant

COUNT EQU 25
... ....
MOV R3, #COUNT

The constant is used to

load the R3 register

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 ‰ The program status word (PSW)
FLAG BITS AND
PSW REGISTER
register, also referred to as the flag
register, is an 8 bit register
Program Status ¾ Only 6 bits are used
Word ƒ These four are CY (carry), AC (auxiliary carry), P
(parity), and OV (overflow)
– They are called conditional flags, meaning
that they indicate some conditions that
resulted after an instruction was executed
ƒ The PSW3 and PSW4 are designed as RS0 and
RS1, and are used to change the bank
¾ The two unused bits are user-definable

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 CY AC F0 RS1 RS0 OV -- P
FLAG BITS AND A carry from D3 to D4
CY PSW.7 Carry flag.
PSW REGISTER
AC PSW.6 Auxiliary carry flag. Carry out from the d7 bit
-- PSW.5 Available to the user for general purpose
Program Status RS1 PSW.4 Register Bank selector bit 1.
Word (cont’) RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
Reflect the number of 1s
The result of -- PSW.1 User definable bit. in register A
signed number P PSW.0 Parity flag. Set/cleared by hardware each
operation is too instruction cycle to indicate an odd/even
large, causing number of 1 bits in the accumulator.
the high-order
bit to overflow RS1 RS0 Register Bank Address
into the sign bit
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH

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 Instructions that affect flag bits
FLAG BITS AND Instruction CY OV AC
PSW REGISTER ADD X X X
ADDC X X X

ADD SUBB X X X
MUL 0 X
Instruction And DIV 0 X
PSW DA X
RPC X
PLC X
SETB C 1
CLR C 0
CPL C X
ANL C, bit X
ANL C, /bit X
ORL C, bit X
ORL C, /bit X
MOV C, bit X
CJNE X

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 ‰ The flag bits affected by the ADD
FLAG BITS AND
PSW REGISTER
instruction are CY, P, AC, and OV
Example 2-2

ADD Show the status of the CY, AC and P flag after the addition of 38H
and 2FH in the following instructions.
Instruction And
PSW MOV A, #38H
(cont’) ADD A, #2FH ;after the addition A=67H, CY=0
Solution:
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 1 since the accumulator has an odd number of 1s (it has five 1s)
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 Example 2-3
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 9CH
PSW REGISTER and 64H in the following instructions.
MOV A, #9CH
ADD ADD A, #64H ;after the addition A=00H, CY=1
Instruction And
Solution:
PSW
(cont’) 9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has zero 1s)

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 Example 2-4
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 88H
PSW REGISTER and 93H in the following instructions.
MOV A, #88H
ADD
ADD A, #93H ;after the addition A=1BH, CY=1
Instruction And
PSW Solution:
(cont’) 88 10001000
+ 93 10010011
11B 00011011
CY = 1 since there is a carry beyond the D7 bit
AC = 0 since there is no carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has four 1s)

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 ‰ There are 128 bytes of RAM in the
REGISTER 8051
BANKS AND
¾ Assigned addresses 00 to 7FH
STACK
‰ The 128 bytes are divided into three
RAM Memory different groups as follows:
Space 1) A total of 32 bytes from locations 00 to
Allocation 1F hex are set aside for register banks
and the stack
2) A total of 16 bytes from locations 20H to each bit in this
2FH are set aside for bit-addressable region can be
accessed
read/write memory individually

3) A total of 80 bytes from locations 30H to

7FH are used for read and write storage,
called scratch pad
temporary storage of data

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 RAM Allocation in 8051

8051 7F

REGISTER Scratch pad RAM

BANKS AND 30
STACK 2F
Bit-Addressable RAM

RAM Memory 20
Space 1F
Allocation
Register Bank 3
18
(cont’) 17 Register Bank 2
10
0F
Register Bank 1 (stack)
08
07
Register Bank 0

00

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 ‰ These 32 bytes are divided into 4
8051
REGISTER
banks of registers in which each bank
BANKS AND has 8 registers, R0-R7
STACK ¾ RAM location from 0 to 7 are set aside for
bank 0 of R0-R7 where R0 is RAM location
Register Banks 0, R1 is RAM location 1, R2 is RAM
location 2, and so on, until memory
location 7 which belongs to R7 of bank 0
¾ It is much easier to refer to these RAM
locations with names such as R0, R1, and
so on, than by their memory locations
‰ Register bank 0 is the default when
8051 is powered up

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 8051 Register banks and their RAM address
REGISTER Bank 3
Bank 0 Bank 1 Bank 2
BANKS AND
STACK 7 R7 F R7 17 R7 1F R7

6 R6 E R6 16 R6 1E R6

Register Banks 5 R5 D R5 15 R5 1D R5

(cont’) 4 R4 C R4 14 R4 1C R4

3 R3 B R3 13 R3 1B R3

2 R2 A R2 12 R2 1A R2

1 R1 9 R1 11 R1 19 R1

0 R0 8 R0 10 R0 18 R0

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 Program Status Word/ Flag Register

‰ We can switch to other banks by use

8051
REGISTER
of the PSW register
BANKS AND ¾ Bits D4 and D3 of the PSW are used to
STACK select the desired register bank
¾ Use the bit-addressable instructions SETB
Register Banks and CLR to access PSW.4 and PSW.3
(cont’)
PSW bank selection
RS1(PSW.4) RS0(PSW.3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1

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 Example 2-5
8051
MOV R0, #99H ;load R0 with 99H
REGISTER MOV R1, #85H ;load R1 with 85H
BANKS AND
STACK
Example 2-6

Register Banks MOV 00, #99H ;RAM location 00H has 99H
MOV 01, #85H ;RAM location 01H has 85H
(cont’) for bank 3:
SETB PSW.4
SETB PSW.3
Example 2-7
SETB PSW.4 ;select bank 2
MOV R0, #99H ;RAM location 10H has 99H
MOV R1, #85H ;RAM location 11H has 85H

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 ‰ The stack is a section of RAM used by
8051 the CPU to store information
REGISTER temporarily
BANKS AND
¾ This information could be data or an
STACK
address
Stack ‰ The register used to access the stack
is called the SP (stack pointer) register
¾ The stack pointer in the 8051 is only 8 bit
wide, which means that it can take value
of 00 to FFH
¾ When the 8051 is powered up, the SP
register contains value 07
ƒ RAM location 08 is the first location begin used
for the stack by the 8051

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 increment

The storing of a CPU register in the

Store
‰
8051
stack is called a PUSH
REGISTER
BANKS AND ¾ SP is pointing to the last used location of
STACK the stack
¾ As we push data onto the stack, the SP is
Stack incremented by one
(cont’) ƒ This is different from many microprocessors
‰ Loading the contents of the stack back
into a CPU register is called a POP Copy
Decrement

¾ With every pop, the top byte of the stack

is copied to the register specified by the
instruction and the stack pointer is
decremented once

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 Example 2-8
8051
Show the stack and stack pointer from the following. Assume the
REGISTER default stack area.
BANKS AND MOV R6, #25H
STACK MOV R1, #12H
MOV R4, #0F3H
PUSH 6
Pushing onto PUSH 1
Stack PUSH 4
Solution:
After PUSH 6 After PUSH 1 After PUSH 4
0B 0B 0B 0B
0A 0A 0A 0A F3
09 09 09 12 09 12
08 08 25 08 25 08 25
Start SP = 07 SP = 08 SP = 09 SP = 0A

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 Example 2-9
8051
Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND POP 3 ; POP stack into R3
STACK POP 5 ; POP stack into R5
POP 2 ; POP stack into R2

Popping From Solution:

Stack
After POP 3 After POP 5 After POP 2
0B 54 0B 0B 0B
0A F9 0A F9 0A 0A
09 76 09 76 09 76 09
08 6C 08 6C 08 6C 08 6C
Start SP = 0B SP = 0A SP = 09 SP = 08
Because locations 20-2FH of RAM are reserved
for bit-addressable memory, so we can change the
SP to other RAM location by using the instruction
“MOV SP, #XX”
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 ‰ The CPU also uses the stack to save
8051
REGISTER
the address of the instruction just
BANKS AND below the CALL instruction
STACK ¾ This is how the CPU knows where to
resume when it returns from the called
CALL subroutine
Instruction And
Stack

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 ‰ The reason of incrementing SP after
8051
REGISTER
push is
BANKS AND ¾ Make sure that the stack is growing
STACK toward RAM location 7FH, from lower to
upper addresses
Incrementing ¾ Ensure that the stack will not reach the
Stack Pointer bottom of RAM and consequently run out
of stack space
¾ If the stack pointer were decremented
after push
ƒ We would be using RAM locations 7, 6, 5, etc.
which belong to R7 to R0 of bank 0, the default
register bank

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 ‰ When 8051 is powered up, register
8051
REGISTER
bank 1 and the stack are using the
BANKS AND same memory space
STACK ¾ We can reallocate another section of RAM
to the stack
Stack and Bank
1 Conflict

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 Example 2-10
8051 Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND MOV SP, #5FH ;make RAM location 60H
STACK
;first stack location
MOV R2, #25H
MOV R1, #12H

Stack And Bank

MOV R4, #0F3H
PUSH 2
1 Conflict PUSH 1
(cont’) PUSH 4

Solution:
After PUSH 2 After PUSH 1 After PUSH 4
63 63 63 63
62 62 62 62 F3
61 61 61 12 61 12
60 60 25 60 25 60 25
Start SP = 5F SP = 60 SP = 61 SP = 62

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 JUMP, LOOP AND CALL
INSTRUCTIONS

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Repeating a sequence of instructions a
LOOP AND certain number of times is called a
JUMP loop
INSTRUCTIONS
¾ Loop action is performed by
Decrement and Jump if not Zero
DJNZ reg, Label
Looping
ƒ The register is decremented
ƒ If it is not zero, it jumps to the target address
referred to by the label
A loop can be repeated a ƒ Prior to the start of loop the register is loaded
maximum of 255 times, if with the counter for the number of repetitions
R2 is FFH
ƒ Counter can be R0 – R7 or RAM location
;This program adds value 3 to the ACC ten times
MOV A,#0 ;A=0, clear ACC
MOV R2,#10 ;load counter R2=10
AGAIN: ADD A,#03 ;add 03 to ACC
DJNZ R2,AGAIN ;repeat until R2=0,10 times
MOV R5,A ;save A in R5

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 ‰ If we want to repeat an action more
LOOP AND
JUMP
times than 256, we use a loop inside a
INSTRUCTIONS loop, which is called nested loop
¾ We use multiple registers to hold the
Nested Loop count

Write a program to (a) load the accumulator with the value 55H, and
(b) complement the ACC 700 times

MOV A,#55H ;A=55H

MOV R3,#10 ;R3=10, outer loop count
NEXT: MOV R2,#70 ;R2=70, inner loop count
AGAIN: CPL A ;complement A register (bitwise)
DJNZ R2,AGAIN ;repeat it 70 times
DJNZ R3,NEXT

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 ‰ Jump only if a certain condition is met
LOOP AND JZ label ;jump if A=0
JUMP MOV A,R0 ;A=R0
INSTRUCTIONS JZ OVER ;jump if A = 0
MOV A,R1 ;A=R1
JZ OVER ;jump if A = 0
Conditional ...
Jumps OVER: Can be used only for register A,
not any other register

Determine if R5 contains the value 0. If so, put 55H in it.

MOV A,R5 ;copy R5 to A
JNZ NEXT ;jump if A is not zero
MOV R5,#55H
NEXT: ...

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 ‰ (cont’)
LOOP AND JNC label ;jump if no carry, CY=0
JUMP ¾ If CY = 0, the CPU starts to fetch and execute
INSTRUCTIONS instruction from the address of the label
¾ If CY = 1, it will not jump but will execute the next
Conditional instruction below JNC
Jumps Find the sum of the values 79H, F5H, E2H. Put the sum in registers
(cont’) R0 (low byte) and R5 (high byte).
MOV R5,#0
MOV A,#0 ;A=0
MOV R5,A ;clear R5
ADD A,#79H ;A=0+79H=79H
; JNC N_1 ;if CY=0, add next number
; INC R5 ;if CY=1, increment R5
N_1: ADD A,#0F5H ;A=79+F5=6E and CY=1
JNC N_2 ;jump if CY=0
INC R5 ;if CY=1,increment R5 (R5=1)
N_2: ADD A,#0E2H ;A=6E+E2=50 and CY=1
JNC OVER ;jump if CY=0
INC R5 ;if CY=1, increment 5
OVER: MOV R0,A ;now R0=50H, and R5=02
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 8051 conditional jump instructions
LOOP AND Instructions Actions
JUMP JZ Jump if A ＝ 0
INSTRUCTIONS JNZ Jump if A ≠ 0
DJNZ Decrement and Jump if A ≠ 0
Conditional CJNE A,byte Jump if A ≠ byte
Jump if byte ≠ #data
Jumps CJNE reg,#data
(cont’) JC Jump if CY ＝ 1
JNC Jump if CY ＝ 0
JB Jump if bit ＝ 1
JNB Jump if bit ＝ 0
JBC Jump if bit ＝ 1 and clear bit

‰ All conditional jumps are short jumps

¾ The address of the target must within
-128 to +127 bytes of the contents of PC

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 The unconditional jump is a jump in
‰
LOOP AND which control is transferred
JUMP unconditionally to the target location
INSTRUCTIONS
LJMP (long jump)
Unconditional ¾ 3-byte instruction
Jumps ƒ First byte is the opcode
ƒ Second and third bytes represent the 16-bit
target address
– Any memory location from 0000 to FFFFH
SJMP (short jump)
¾ 2-byte instruction
ƒ First byte is the opcode
ƒ Second byte is the relative target address
– 00 to FFH (forward +127 and backward
-128 bytes from the current PC)

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 ‰ To calculate the target address of a
LOOP AND
JUMP
short jump (SJMP, JNC, JZ, DJNZ, etc.)
INSTRUCTIONS ¾ The second byte is added to the PC of the
instruction immediately below the jump
Calculating ‰ If the target address is more than -128
Short Jump to +127 bytes from the address below
Address
the short jump instruction
¾ The assembler will generate an error
stating the jump is out of range

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 Line PC Opcode Mnemonic Operand
LOOP AND 01 0000 ORG 0000
JUMP 02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
INSTRUCTIONS 04 0004 6003 JZ NEXT
05 0006 08 INC R0
Calculating 06 0007 04
+ AGAIN: INC A
07 0008 04 INC A
Short Jump 08 0009 2477 NEXT: ADD A,#77H
Address 09 000B 5005 JNC OVER
(cont’) 10 000D E4 CLR A
11 000E F8 MOV R0,A
12 000F F9
+ MOV R1,A
13 0010 FA MOV R2,A
14 0011 FB MOV R3,A
15 0012 2B OVER: ADD A,R3
16 0013 50F2 JNC AGAIN
17 0015 80FE + HERE: SJMP HERE
18 0017 END

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 ‰ Call instruction is used to call subroutine
CALL
¾ Subroutines are often used to perform tasks
INSTRUCTIONS that need to be performed frequently
¾ This makes a program more structured in
addition to saving memory space
LCALL (long call)
¾ 3-byte instruction
ƒ First byte is the opcode
ƒ Second and third bytes are used for address of
target subroutine
– Subroutine is located anywhere within 64K
byte address space
ACALL (absolute call)
¾ 2-byte instruction
ƒ 11 bits are used for address within 2K-byte range

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 ‰ When a subroutine is called, control is
CALL
INSTRUCTIONS
transferred to that subroutine, the
processor
LCALL ¾ Saves on the stack the the address of the
instruction immediately below the LCALL
¾ Begins to fetch instructions form the new
location
‰ After finishing execution of the
subroutine
¾ The instruction RET transfers control back
to the caller
ƒ Every subroutine needs RET as the last
instruction

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 ORG 0
BACK: MOV A,#55H ;load A with 55H
CALL MOV P1,A ;send 55H to port 1
INSTRUCTIONS LCALL
MOV
DELAY
A,#0AAH
;time
;load
delay
A with AA (in hex)
MOV P1,A ;send AAH to port 1
LCALL LCALL
SJMP
DELAY
BACK ;keep doing this indefinitely
(cont’) Upon executing “LCALL DELAY”,
the address of instruction below it,
The counter R5 is set to “MOV A,#0AAH” is pushed onto
FFH; so loop is repeated stack, and the 8051 starts to execute
255 times.
at 300H.
;---------- this is delay subroutine ------------
ORG 300H ;put DELAY at address 300H
DELAY: MOV R5,#0FFH ;R5=255 (FF in hex), counter
AGAIN: DJNZ R5,AGAIN ;stay here until R5 become 0
RET ;return to caller (when R5 =0)
END ;end of asm file
When R5 becomes 0, control falls to the
The amount of time delay depends RET which pops the address from the stack
on the frequency of the 8051 into the PC and resumes executing the
instructions after the CALL.
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 001 0000 ORG 0
002 0000 7455 BACK: MOV A,#55H ;load A with 55H
CALL 003 0002 F590 MOV P1,A ;send 55H to p1
INSTRUCTIONS 004
005
0004
0007
120300
74AA
LCALL DELAY
MOV A,#0AAH
;time
;load
delay
A with AAH
006 0009 F590 MOV P1,A ;send AAH to p1
CALL 007
008
000B
000E
120300
80F0
LCALL DELAY
SJMP BACK ;keep doing this
Instruction and 009 0010
Stack 010
011
0010
0300
;-------this is the delay subroutine------
ORG 300H
012 0300 DELAY:
013 0300 7DFF MOV R5,#0FFH ;R5=255
014 0302 DDFE AGAIN: DJNZ R5,AGAIN ;stay here
015 0304 22 RET ;return to caller
016 0305 END ;end of asm file

Stack frame after the first LCALL

0A
09 00 Low byte goes first
and high byte is last
08 07
SP = 09
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 01 0000 ORG 0
02 0000 7455 BACK: MOV A,#55H ;load A with 55H
03 0002 F590 MOV P1,A ;send 55H to p1
CALL 04 0004 7C99 MOV R4,#99H
05 0006 7D67 MOV R5,#67H
INSTRUCTIONS 06 0008 120300 LCALL DELAY ;time delay
07 000B 74AA MOV A,#0AAH ;load A with AA
08 000D F590 MOV P1,A ;send AAH to p1
Use PUSH/POP 09 000F 120300 LCALL DELAY
in Subroutine
10 0012 80EC SJMP BACK ;keeping doing
this
11 0014 ;-------this is the delay subroutine------
12 0300 ORG 300H
13 0300 C004 DELAY: PUSH 4 ;push R4
14 0302 C005 PUSH 5 ;push R5
Normally, the 15 0304 7CFF MOV R4,#0FFH;R4=FFH
number of PUSH 16 0306 7DFF NEXT: MOV R5,#0FFH;R5=FFH
and POP 17 0308 DDFE AGAIN: DJNZ R5,AGAIN
instructions must 18 030A DCFA DJNZ R4,NEXT
19 030C D005 POP 5 ;POP into R5
always match in any
20 030E D004 POP 4 ;POP into R4
called subroutine 21 0310 22 RET ;return to caller
22 0311 After first LCALL After PUSH 4
END After of
;end PUSH 5 file
asm
0B 0B 0B 67 R5
0A 0A 99 R4 0A 99 R4
09 00 PCH 09 00 PCH 09 00 PCH
Department08of Computer
0B PCLScience
08 and 0B Information
PCL 08 Engineering
0B PCL
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 ;MAIN program calling subroutines
ORG 0
CALL MAIN: LCALL SUBR_1 It is common to have one
INSTRUCTIONS LCALL
LCALL
SUBR_2
SUBR_3
main program and many
subroutines that are called
from the main program
Calling
HERE: SJMP HERE
;-----------end of MAIN
Subroutines SUBR_1: ...
... This allows you to make
RET each subroutine into a
;-----------end of subroutine1 separate module
- Each module can be
SUBR_2: ...
... tested separately and then
RET brought together with
;-----------end of subroutine2 main program
- In a large program, the
SUBR_3: ... module can be assigned to
... different programmers
RET
;-----------end of subroutine3
END ;end of the asm file

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 ‰ The only difference between ACALL
CALL
and LCALL is
INSTRUCTIONS
¾ The target address for LCALL can be
ACALL anywhere within the 64K byte address
¾ The target address of ACALL must be
within a 2K-byte range
‰ The use of ACALL instead of LCALL
can save a number of bytes of
program ROM space

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 ORG 0
CALL BACK: MOV
MOV
A,#55H
P1,A
;load
;send
A with
55H to
55H
port 1
INSTRUCTIONS LCALL DELAY ;time delay
MOV A,#0AAH ;load A with AA (in hex)
MOV P1,A ;send AAH to port 1
ACALL LCALL DELAY
(cont’) SJMP BACK ;keep doing this indefinitely
...
END ;end of asm file

A rewritten program which is more efficiently

ORG 0
MOV A,#55H ;load A with 55H
BACK: MOV P1,A ;send 55H to port 1
ACALL DELAY ;time delay
CPL A ;complement reg A
SJMP BACK ;keep doing this indefinitely
...
END ;end of asm file

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 ‰ CPU executing an instruction takes a
TIME DELAY
FOR VARIOUS
certain number of clock cycles
8051 CHIPS ¾ These are referred as to as machine cycles
‰ The length of machine cycle depends
on the frequency of the crystal
oscillator connected to 8051
‰ In original 8051, one machine cycle
lasts 12 oscillator periods
Find the period of the machine cycle for 11.0592 MHz crystal
frequency

Solution:
11.0592/12 = 921.6 kHz;
machine cycle is 1/921.6 kHz = 1.085μs

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 For 8051 system of 11.0592 MHz, find how long it takes to execute
TIME DELAY each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
FOR VARIOUS (d) LJMP (e) SJMP (f) NOP (g) MUL AB
8051 CHIPS
(cont’) Solution:
Machine cycles Time to execute
(a) 1 1x1.085μs ＝ 1.085μs
(b) 1 1x1.085μs ＝ 1.085μs
(c) 2 2x1.085μs ＝ 2.17μs
(d) 2 2x1.085μs ＝ 2.17μs
(e) 2 2x1.085μs ＝ 2.17μs
(f) 1 1x1.085μs ＝ 1.085μs
(g) 4 4x1.085μs ＝ 4.34μs

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS
8051 CHIPS MOV A,#55H
AGAIN: MOV P1,A
ACALL DELAY
Delay CPL A
Calculation SJMP AGAIN A simple way to short jump
to itself in order to keep the
;---time delay-------
DELAY: MOV R3,#200 microcontroller busy
HERE: DJNZ R3,HERE HERE: SJMP HERE
RET We can use the following:
SJMP $
Solution:
Machine cycle
DELAY: MOV R3,#200 1
HERE: DJNZ R3,HERE 2
RET 2
Therefore, [(200x2)+1+2]x1.085μs ＝ 436.255μs.

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS
8051 CHIPS Machine Cycle
DELAY: MOV R3,#250 1
HERE: NOP 1
Increasing NOP 1
Delay Using NOP 1
NOP 1
NOP DJNZ R3,HERE 2
RET 2

Solution:
The time delay inside HERE loop is
[250(1+1+1+1+2)]x1.085μs ＝ 1627.5μs.
Adding the two instructions outside loop we
have 1627.5μs + 3 x 1.085μs ＝ 1630.755μs

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS Machine Cycle
8051 CHIPS DELAY: MOV R2,#200 1
Notice in nested loop,
AGAIN: MOV R3,#250 1
as in all other time
Large Delay HERE: NOP
NOP
1
1
delay loops, the time
Using Nested DJNZ R3,HERE 2
is approximate since
we have ignored the
Loop DJNZ R2,AGAIN 2
first and last
RET 2
instructions in the
subroutine.
Solution:
For HERE loop, we have (4x250)x1.085μs＝1085μs.
For AGAIN loop repeats HERE loop 200 times, so
we have 200x1085μs＝217000μs. But “MOV
R3,#250” and “DJNZ R2,AGAIN” at the start and
end of the AGAIN loop add (3x200x1.805)=651μs.
As a result we have 217000+651=217651μs.

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 ‰ Two factors can affect the accuracy of
TIME DELAY the delay
FOR VARIOUS
¾ Crystal frequency
8051 CHIPS
ƒ The duration of the clock period of the machine
cycle is a function of this crystal frequency
Delay ¾ 8051 design
Calculation for ƒ The original machine cycle duration was set at
Other 8051 12 clocks
ƒ Advances in both IC technology and CPU
design in recent years have made the 1-clock
machine cycle a common feature
Clocks per machine cycle for various 8051 versions
Chip/Maker Clocks per Machine Cycle
AT89C51 Atmel 12
P89C54X2 Philips 6
DS5000 Dallas Semi 4
DS89C420/30/40/50 Dallas Semi 1
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 Find the period of the machine cycle (MC) for various versions of
TIME DELAY 8051, if XTAL=11.0592 MHz.
(a) AT89C51 (b) P89C54X2 (c) DS5000 (d) DS89C4x0
FOR VARIOUS
8051 CHIPS Solution:
(a) 11.0592MHz/12 = 921.6kHz;
MC is 1/921.6kHz = 1.085μs ＝ 1085ns
Delay (b) 11.0592MHz/6 = 1.8432MHz;
MC is 1/1.8432MHz = 0.5425μs ＝ 542ns
Calculation for (c) 11.0592MHz/4 = 2.7648MHz ;
Other 8051 MC is 1/2.7648MHz = 0.36μs ＝ 360ns
(cont’) (d) 11.0592MHz/1 = 11.0592MHz;
MC is 1/11.0592MHz = 0.0904μs ＝ 90ns

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 Instruction 8051 DSC89C4x0
MOV R3,#55 1 2
TIME DELAY DEC R3 1 1
FOR VARIOUS DJNZ R2 target 2 4
LJMP 2 3
8051 CHIPS SJMP 2 3
NOP 1 1
Delay MUL AB 4 9
Calculation for For an AT8051 and DSC89C4x0 system of 11.0592 MHz, find how
Other 8051 long it takes to execute each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
(cont’) (d) LJMP (e) SJMP (f) NOP (g) MUL AB

Solution:
AT8051 DS89C4x0
(a) 1¯1085ns ＝ 1085ns 2¯90ns = 180ns
(b) 1¯1085ns ＝ 1085ns 1¯90ns = 90ns
(c) 2¯1085ns ＝ 2170ns 4¯90ns = 360ns
(d) 2¯1085ns ＝ 2170ns 3¯90ns = 270ns
(e) 2¯1085ns ＝ 2170ns 3¯90ns = 270ns
(f) 1¯1085ns ＝ 1085ns 1¯90ns = 90ns
(g) 4¯1085ns ＝ 4340ns 9¯90ns = 810ns
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