Memory Management Contd…

Soma Hazra

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 Paging
Paging allows the physical address space of a process to be
non-contiguous.
Divide physical memory into fixed-sized blocks called frames.
Divide logical memory into blocks of same size called pages.
(size of page is power of 2, between 512 bytes to 16 MB).
Each address generated by the CPU divided in two parts:
a page number(p), and an offset(d).
For this support from hardware is very much needed.
Every address generated by CPU is divided into two parts:

 Page number: used as an Index to a page table that contains

the base address of each page in physical memory.
 Page offset: Combined with the base address to define the
physical memory address that is sent to the memory unit.

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Address Translation Architecture

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Example

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 Example
Page size = 4 bytes
Process size = 16bytes
Physical memory = 32 b

Number of pages = ?
Number of frames=?

Where do the following map?

Logical 0: Page 0, offset 0:

Logical 3: Page 0, offset 3:

Logical 4: ?

Logical 13: ? 5
• Logical Address 0 maps to physical address 20.
[ (5*4)+0]

• Logical Address 3 maps to physical address 23.

[(5*4)+3]

What for logical address 13 and 4?

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 Paging and Fragmentation
Don't have external fragmentation with paging.
 Any free frame can be allocated to a process that needs
it.
May have internal fragmentation with paging.
 Frames are allocated as units. Last frame may not be
completely full.
 Example: if pages are 2,048 bytes a process of 72,766
bytes would need 35 pages plus 1,086 bytes. It would be
allocated 36 frames, resulting in an internal
fragmentation of 2048-1086=962 bytes.
Note: In the worst case, a process would need n pages
plus one byte.

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 Allocation of Frames
The O.S. keeps track of which frames are
allocated and which are free in a frame table.
If a process requests n frames, there must be n
frames available to satisfy the request. If so,
they are allocated to the process.
As each frame is allocated to each page, the
frame number is put in the page table for that
process.
Note: The user views memory as contiguous
space. The program is actually scattered
throughout physical memory.
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 Free Frames

Free frames. (a) Before allocation. (b) After allocation 9

Storing Page Table in Main Memory
The page table is implemented as a set of dedicated
registers (for small number of entries).
For large page tables, use of fast registers is not
feasible.
That is why, the page table is kept in main memory
and a Page-table base register (PTBR) points to the
page table.
Changing page table requires changing only this one
register.
This reduces the context switch time.
Drawback: In this scheme every data/instruction
access requires two memory accesses. One for the
page table and one for the data/instruction.
Solution: By using translation look-aside buffer (TLB).
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Translation Look-Aside Buffer (TLB)
The two memory access problem can be solved by using a
special fast-lookup hardware cache, called TLB.
 Each entry in TLB consists of two parts: a key and a value.
 When the memory is presented with an item, it is compared
with all keys simultaneously. If the item is found then the
corresponding value field is returned.
 the search is very fast , but this kind of hardware is very
expensive, so it is generally small (64 - 1024 entries).

In each memory access, the TLB is searched first to locate

the page number.
 If the page is found (a hit) the associated frame is used to
access the data in memory.
 If the page is not found (a miss), the page number is looked up
in the page table in main memory. The page number and
associated frame is added to the TLB.

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Paging Hardware With TLB

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 Effective Access Time (EAT)
Effective access time (EAT) is the average time needed to access memory.
Hit Ratio: The percentage of times that a particular page number is found
in the TLB.
Effective access time can be calculated based on:
 The time it takes to access main memory
 The time it takes to access the TLB
 The hit ratio for the TLB
Example:
 Time to access main memory = 100ns
 Time to access TLB = 20 ns
 Hit ratio = 0.8 (80%)
 If page is found in TLB, total access time = ?
 If page is not found in TLB, total access time = ?
 Effective access time = ?
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 Inverted Page Table
One entry for each real page of memory.
Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page.
Decreases memory needed to store each page
table, but increases time needed to search the
table when a page reference occurs.
Use hash table to limit the search to one — or at
most a few — page-table entries.
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Inverted Page Table Architecture

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 Shared Pages
• Shared code
– One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
– Shared code must appear in same location in the logical
address space of all processes.

• Private code and data

– Each process keeps a separate copy of the code and data.
– The pages for the private code and data can appear
anywhere in the logical address space.

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Shared Pages Example

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 Segmentation
Segmentation is a memory-management scheme that supports
user view of memory.
The logical address space is a collection of segments.
Each segment has a name and a length. The addresses specify
both the segment name and the offset with in the segment.
For simplicity, the segments are given numbers.
The logical address specifies the segment number and the offset:
<segment-number, offset>
Normally, the user program is compiled, and the compiler
automatically constructs segments reflecting the input program.
A Pascal compiler might create separate segments for following:
 main program, function, object,
 local variables, global variables,
 stack, symbol table,
 arrays etc.

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 Segmentation Architecture
Logical address consists of two numbers:
<segment-number, offset>
The segment number is used as an index into segment table.
The offset value must be between 0 and segment limit.
Segment table – maps two-dimensional physical addresses;
each table entry has:
base – contains the starting physical address where the
segments reside in memory.
limit – specifies the length of the segment.
The limit register is used to check for valid memory
references.

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Segmentation Hardware

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 Example
Suppose a program is divided into 5 segments:
Segment 0: Subroutine
Segment 1: sqrt function
Segment 2: main program
Segment 3: stack
Segment 4: symbol table
The segment table is as follows:
Segment Limit Base
0 1000 1400
1 400 6300
2 400 4300
3 1100 3200
4 1000 4700

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Example of Segmentation
So, a reference to
byte 53 of
Segment 2 is
mapped onto
location
4300+53=4353.

Where does
segment 3, offset
567 map?
Where does segment
0, offset 1222 map?

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 Segmentation with Paging
• Both paging and segmentation have their advantages and
disadvantages.
• So, it is better to combine these two schemes to improve
on each.
• The main objective of this scheme is to avoid
fragmentation all together and supports user view of
memory.
• In this scheme each segment is divided into pages and
each segment maintains a page table.
• Hence the logical address is divided into 3 parts: (S, P, D)
where ‘S’ is the segment number, ‘P’ is the page number
and ‘D’ is the offset or displacement.
• The architecture is given below:

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Segmentation with Paging (contd…)

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