Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
First Semester 2024-2025
Mid-Semester Examination
(EC-2 Regular)
Course No : ESZG642/ MEL ZG642
Course Title : VLSI ARCHITECTURE
Nature of Exam : Closed Book
Weightage : 60 marks
No. of Pages = 2
Duration :
No. of Questions = 4
Date of Exam :
Q1. Let’s consider two design options for improving the performance of a graphics benchmark where floating-
point (FP) operations play a key role.
In the first option, we enhance the hardware for the floating-point square root (FSQRT) operation, which is
responsible for 20% of the execution time. By improving the FSQRT, we can speed it up by a factor of 10.
In the second option, we aim to improve the performance of all FP instructions in the graphics processor, which
make up 50% of the total execution time. This alternative offers a speedup factor of 1.6 for all FP operations.
By comparing the overall effect of these optimizations on execution time, determine which approach provides
the greater benefit? [8 marks]
Q2. A half adder is given to you as a standard component in a library. It has a delay of 0.8 ns. The library also
provides D-Flip-flops with “Set up time” = 0.1 ns and “Clock-to-Q delay” = 0.1 ns. Using only these two
components, design an optimal 8-bit adder that can give a sustained throughput of 8-bit addition at a clock
rate of 500 MHz. [8 marks]
Q3. The control unit of the architecture given in the text uses sequence branch and instruction branch as a part
of Instruction decoding in instruction execution. Explain with suitable example how this is implemented and
how does it branch from one sequence to another. [8 marks]
Q4. A CISC instruction set architecture has the following architecture, ules of operation and instructions:
a) SCAN @RY, RX: This instruction checks all the elements of a one-dimensional array and
returns the total count of negative numbers stored in the array. RX field in the instruction word
specifies the register that contains the array size (number of elements in the array); RY field specifies
the register that contains the starting address of the array. Elements of the array are stored in the
memory at successive addresses starting from the address specified in the RY Register. The count
value of the number of negative numbers stored in the array is to be returned into memory location
which is one below the last element in the array.
b) AIN (RX, RY): This instruction fetches the two integers (2’s complement binary numbers)
stored in memory at addresses provided by registers RX and RY. It then adds them and converts the
sum into its twos complement and stores it in memory at address provided by register RY.
(i) Write the annotated level 2 flowcharts for the above two instructions using the execution unit
schematic diagram and rules of operation given in the text (mention changes if any required
to the execution unit). [8+8 = 16 marks]
(ii) For the flowchart states drawn for the above two instructions (assuming these are the only two
instructions to support) identify the different uses of each for the following macros: Reg;
ALU; PC; T1. Propose a optimal control-word format for each of these and assign suitable
bits to each. [4+4+2+2 = 12 marks]
(iii) Show the sequence of both instructions using the table below: [4+4=8 marks]
Instruction Starting Control Word Next Control IB SB
Sequence Address Word Address Instruction Instruction
Decoder Decoder
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