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UCS510

This document contains a roll number and details for an end semester examination in Computer Architecture and Organization. It lists 7 questions related to topics like instruction cycles, addressing modes, cache memory, pipelining, and input/output modes. The questions involve drawing diagrams, calculating values, explaining concepts, and more. The document provides a framework for students to attempt 5 of the 7 questions within a 2 hour time period.

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Subhav Goyal
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63 views2 pages

UCS510

This document contains a roll number and details for an end semester examination in Computer Architecture and Organization. It lists 7 questions related to topics like instruction cycles, addressing modes, cache memory, pipelining, and input/output modes. The questions involve drawing diagrams, calculating values, explaining concepts, and more. The document provides a framework for students to attempt 5 of the 7 questions within a 2 hour time period.

Uploaded by

Subhav Goyal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll Number:

Thapar Institute of Engineering & Technology, Patiala


Department of Computer Science & Engineering
END SEMESTER EXAMINATION
Course Code: UCS 510
B. E. (Second Year): Semester-Ill
Course Name: Computer Architecture
(CSE) & Organization
Date: 29 Jan, 2021 Time: 11.00 - 1.00 Hrs
Name of Faculty: Dr. Rupali Bhardwaj,
Time: 2 Hours, M. Marks: 50
Vivek Gupta
Note: Attempt any five questions and attempted questions should be in sequence.
IIQ 1 (a) Consider the following multiplexer. Find the value of output function 'g'. (4)
Q 0 MUX

(b) Consider a four variable function f (A, B, C, D) = E (5,7,11,12) + d (3,11,13,15). Find (6)
the minimal expression.
Q2 (a) Design a 2-bit arithmetic circuit with one selection variable S and two n-bit data (6)
inputs A & B. The circuit generates the following four arithmetic operations in
411 conjunction with the input carry Cin. Draw the logic diagram for the first four
stages.
S Cln=0 Cm =1

0 D4i+B D=A-B

1 D=A+1 D=A-1

(b) Convert (76.125)io into IEEE single precision representation. (4)


Q3 (a) Describe Instruction cycle in brief with flowchart. Specify corresponding micro (5)
operations at each stage.
(b) Assume an instruction set that uses a fixed 16-bit instruction length. Operand (5)
specifiers are 6 bits in length. There are K-two operand instructions and L zero
operand instructions. What is the maximum number of one operand instructions
that can be supported? (no three-address instruction exists). P.T.O.
Q4 (a) ISZ indirect instruction is fetched from memory and executed using registers PC, (4)
AR, DR, and IR of the basic computer. The initial content of PC is F2C. The content
of memory F2C is E78F. The content of memory at address 78F is 895C. The content
of memory at address 95C is FFFO. The value of each register updated at each
timing signal recorded in the table given below. Fill the values at position A, B, C,
D, E, F, G, and H.
Timing Signal PC (in hex) AR (in hex) DR (in hex) IR (in hex)

TO A
Ti B C

T2
T3
T4 F
T5
T6

(b) Let the address stored in the program counter be designated by the symbol X1. The (6)
instruction stored at X1 has an address part(operand reference) X2. The operand
needed to execute the instruction is stored in memory word with address X3. An
index register contains the value X4. Determine the effective address for the
following addressing modes: Indirect, PC relative, Direct, Indexed, Autodecrement„
Autoincrement
Q5 (a) A four-way set associative cache memory can accommodate a total of 8192 words (2+1)
from the main memory. The main memory size is 128 K >c 32, how many bits are
there in the tag, index field of the address format?What is the size of the cache
memory?
(b) Given x=0101 and y=1010 (already in two's complement notation) compute the (7)
product p =xxy using booth's algorithm by drawing flowchart also.
Q6 (a) A computer has a cache, main memory and a disk used for virtual memory. If a (6)
reference word is in the cache, 20 ns are required to access it. If it is in main
memory but not in the cache , 60 ns are needed to load it into the cache. If the word
is not in main meory, 12 ms are required to fetch the word from the disk, followed 11101
by 6Ons to copy it to the cache, and then reference is started again. The cache hit
ratio is 0.9 and main memory hit ratio is 0.6. What is the average time in
nanoseconds required to access a referenced word on this sytem?
(b) Differentiate between the following- (4)
(i) RISC vs CISC (ii) Paging vs Segmentation
Q7 (a) Consider the following sequence of instructions being processed on the 5- (4+2)
stage(Fetch, Decode, Execute, Memory access, Write back) RISC processor.-
LOAD R4, #100(R2)
ADD R5, R2, R3
SUB R6, R4, R5
AND R7, R2, R5
Assume that the pipeline does not use operand forwarding. Draw a space time
diagram that represents instruction flow through the pipeline during each clock
cycle. How long does it take for the instruction sequence to complete?
(b) Explain three input-output modes of data transfer with a suitable example. (4)

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