Memory Management

1. Memory Management - Basics

Goal: To manage the computer's primary memory (RAM) efficiently and

securely. Memory is a crucial but limited resource. The operating system's
memory manager is responsible for:
Allocation: Assigning memory blocks to processes that need them.
Deallocation: Reclaiming memory from processes when they terminate or
no longer need it.
Tracking: Keeping track of which parts of memory are currently in use
and by which process, and which parts are free (available).
Protection: Ensuring a process cannot access memory that hasn't been
allocated to it, preventing interference with the OS or other processes.
Sharing: Allowing processes to share specific parts of memory when
appropriate (e.g., shared libraries).
Mechanism: The Memory Management Unit (MMU) is a hardware component
that translates logical addresses generated by the CPU into physical
addresses in RAM. The OS configures the MMU according to its memory
management strategy.

2. Memory Protection

Purpose: To prevent processes from accessing memory outside their

allocated address space. This protects the integrity of the OS and other
concurrently running processes.
Mechanism (Base and Limit Registers): A simple hardware-based method.
Base Register: Stores the starting physical address of a process's
allocated memory block.
Limit Register: Stores the size (length) of the allocated memory block.
Address Validation: When the CPU generates a logical address (relative
to the start of the process's space), the MMU performs these checks:
1. Is the logical address ≥ 0? (Implicitly true usually)
2. Is the logical address < Limit Register?
If both conditions are true, the logical address is considered valid. The
physical address is calculated as:

Physical Address = Base Register + Logical Address

If the logical address is ≥ the Limit Register, it's an error (addressing

violation), and the hardware traps to the OS, which typically terminates
the offending process.
 OS Role: The OS is responsible for loading the correct base and limit register
values whenever it switches context (i.e., switches the CPU to run a different
process).

3. Multiprogramming with Fixed Partition

Concept: The main memory is divided into a number of static (fixed-size)

partitions before processes start running. This division remains constant.
Types:
Equal-Size Partitions: All partitions are the same size. Simpler to manage
but less flexible.
Unequal-Size Partitions: Partitions have different sizes. Allows better
matching of process size to partition size but requires more complex
management.
Process Allocation: When a process arrives, it's placed in an input queue for
the smallest available partition that is large enough to hold it. If a suitable
partition is occupied, the process waits.
Advantages: Simple to implement and manage.
Disadvantages:
Internal Fragmentation: Occurs when a process loaded into a partition is
smaller than the partition size. The unused space within the partition
cannot be used by any other process, leading to wasted memory. For
example, if a 50KB process is loaded into a 64KB partition, 14KB is
wasted due to internal fragmentation.
Limited Multiprogramming: The number of concurrent processes is
limited by the number of partitions.
Size Limitation: A process larger than the largest partition cannot be run.

4. Multiprogramming with Variable Partition

Concept: The OS keeps track of memory as one large block initially. When a
process arrives, the OS allocates a region (partition) exactly the size required
by the process from a free block (hole). Memory consists of allocated
partitions and free blocks (holes).
Process Allocation: The OS maintains a list of free blocks. When a process
needs memory, the OS searches the list for a suitable hole. Common search
strategies include:
First-Fit: Allocate the first hole that is large enough. Fast but may leave
small unusable holes.
Best-Fit: Allocate the smallest hole that is large enough. Tries to minimize
leftover hole size but may leave tiny, unusable holes. Requires searching
the entire list.
Worst-Fit: Allocate the largest hole. Leaves the largest possible leftover
hole, which might be more useful later. Requires searching the entire list.
 Next-Fit: Allocate the next hole that is large enough, starting from where
the previous search left off (rather than always starting at the beginning).
Slightly faster than first-fit in some cases, but can lead to more
fragmentation.
Advantages: No internal fragmentation (partitions are exactly the size
needed). More flexible degree of multiprogramming.
Disadvantages:
External Fragmentation: Occurs as processes are loaded and removed.
Memory becomes divided into many small, non-contiguous free blocks
(holes). Even if the total free memory is sufficient for a new process, it
might not be usable because no single free block is large enough.
Compaction: A solution to external fragmentation. The OS shuffles
memory contents to place all free memory together into one large block.
This is computationally expensive and requires stopping normal
processing.

5. Multiple Base Register / Base and Limit Registers

This builds upon the basic base/limit protection (#2). Instead of just one
base/limit pair for the entire process address space, systems (especially those
using segmentation, #7) can use multiple base/limit register pairs.
Segmentation Context: In segmentation, a process's logical address space is
divided into multiple segments (e.g., code, data, stack). Each segment can
have its own base/limit pair.
Mechanism: The logical address generated by the CPU typically includes a
segment identifier (or selector) and an offset within that segment.
1. The segment identifier is used to select the appropriate base/limit register
pair (often looked up in a segment table, see #7).
2. The offset is checked against the selected limit register value.
3. If offset < limit , the physical address is calculated as base + offset .
Advantages: Provides finer-grained protection (e.g., code segment can be
marked read-only) and facilitates sharing of specific segments (like code)
between processes by mapping multiple segment table entries to the same
physical memory region.

6. Paging

Concept: A memory management scheme that eliminates external

fragmentation and allows a process's physical address space to be non-
contiguous.
Mechanism:
Physical Memory: Divided into fixed-size blocks called frames. (Size is
power of 2, e.g., 4KB).
 Logical Memory (Process View): Divided into blocks of the same fixed
size called pages.
Page Table: For each process, the OS maintains a page table. This table
maps each logical page of the process to a physical frame in memory. The
entry for page p contains the frame number f where that page is stored.
Address Translation:
1. The CPU generates a logical address, which is conceptually divided
into a page number (p) and a page offset (d).
2. The MMU uses the page number p as an index into the process's
page table to find the corresponding frame number (f).
3. The MMU replaces the page number p with the frame number f to
form the physical address: frame number (f) + page offset (d). The
offset d remains unchanged because the page and frame sizes are
identical.
Advantages:
No external fragmentation. Any free frame can be allocated to any page.
Allows physical memory allocation to be non-contiguous.
Facilitates sharing of common code (e.g., libraries) by having multiple
processes' page tables point to the same frames.
Disadvantages:
Internal Fragmentation: Possible in the last page of a process if the
process size is not an exact multiple of the page size. On average, half a
page is wasted per process.
Page Table Overhead: Page tables themselves consume memory.
Translation Time: Each memory access requires at least one extra
memory access (to the page table). This is usually mitigated by using a
hardware cache called the Translation Lookaside Buffer (TLB).

7. Segmentation

Concept: A memory management scheme that supports the user's view of

memory. A program is seen as a collection of logical units called segments.
Segments can have different sizes and often correspond to program
structures like:
Main program (code segment)
Procedures/functions
Data structures (global variables, heap)
Stack
Mechanism:
Logical Address: Consists of a two-tuple: <segment number (s), offset
(d)>.
 Segment Table: For each process, the OS maintains a segment table.
Each entry in the table corresponds to a segment and contains:
Segment Base: The starting physical address where the segment
resides in memory.
Segment Limit: The length (size) of the segment.
Address Translation:
1. The CPU generates a logical address <segment number s , offset
d >.
2. The MMU uses the segment number s as an index into the process's
segment table to find the base and limit for that segment.
3. The MMU checks if the offset d is valid: 0 <= d < segment limit .
4. If valid, the physical address is calculated as: segment base + offset
d.
5. If invalid ( d >= segment limit ), a trap (addressing error) occurs.
Advantages:
Reflects logical program structure.
Facilitates protection (e.g., marking code segments read-only) and
sharing of entire segments.
Segments can grow or shrink dynamically (within limits).
Disadvantages:
External Fragmentation: Like variable partitioning, as segments are
allocated and deallocated, memory can become fragmented into
unusable holes. Compaction may be needed.
Segment sizes vary, making memory allocation more complex than with
fixed-size pages.

8. Page Table Structure

Problem: Simple linear page tables (an array indexed by page number) can
become excessively large for systems with large logical address spaces (e.g.,
32-bit or especially 64-bit). A 32-bit address space with 4KB pages needs 2 20

(over a million) entries. If each entry is 4 bytes, the table needs 4MB per
process. For 64-bit, it's infeasible.
Solutions (Structures to manage large page tables):
Hierarchical Paging (Multi-Level Page Tables):
Concept: Break the logical address space into multiple page table
levels. The main page table (outer level) points to second-level page
tables, which then point to the actual frames (or further levels).
Example (Two-Level): A logical address is split into p1 (outer page
table index), p2 (second-level page table index), and d (offset). p1
indexes the outer table to find the base address of the relevant
 second-level table. p2 indexes that second-level table to find the
frame number f . Physical address = f + d .
Advantage: Second-level tables only need to exist for the address
ranges actually used by the process, saving significant space
compared to one huge linear table.
Disadvantage: Requires multiple memory accesses per address
translation (one for each level), increasing latency (mitigated by TLB).
Hashed Page Tables:
Concept: The virtual page number p is hashed into a hash table.
Each entry in the hash table contains a linked list of elements {virtual
page number, frame number, pointer to next element}.
Mechanism: Hash p , search the corresponding linked list for a
match on p . If found, retrieve the frame number f .
Advantage: Handles very large (sparse) address spaces efficiently
(common in 64-bit systems). Table size is somewhat independent of
the virtual address space size.
Disadvantage: Collision handling adds complexity.
Inverted Page Tables:
Concept: Reverses the standard approach. Instead of one table per
process mapping virtual pages to physical frames, there is one
system-wide table with one entry for each physical frame. Each
entry stores {process ID (PID), virtual page number (p)} currently
occupying that frame.
Mechanism: To translate a logical address <PID, p, d>, the OS must
search the entire inverted page table for an entry matching <PID, p>.
If found at index i , the physical address is i + d .
Advantage: Table size is proportional to physical memory size, not
the combined size of all virtual address spaces.
Disadvantage: Searching the table can be very slow. This is usually
addressed by using a hash table to index into the inverted table
based on <PID, p>, significantly speeding up the lookup but adding
complexity.

9. Virtual Memory - Basic Concepts

Concept: An abstraction or technique that allows the execution of processes

that may not be completely resident in physical memory (RAM). It separates
the logical memory addresses used by a process from the actual physical
memory addresses.
Motivation:
Run Large Programs: Enables running programs whose size exceeds the
available physical RAM. Only the necessary parts of the program need to
be in memory at any given time.
 Increased Multiprogramming: Allows more processes to reside partially
in memory concurrently, increasing CPU utilization and system
throughput.
Simplified Programming: Programmers don't need to worry about the
physical memory limitations; they can assume a large, contiguous logical
address space.
Mechanism:
The process's logical address space (virtual address space) is treated as
a large, linear array of bytes.
Parts of this logical space reside in physical memory, while other parts are
stored on a fast secondary storage device (like an SSD or HDD), typically
in a swap space or paging file.
The Memory Management Unit (MMU), in conjunction with the OS,
translates logical addresses to physical addresses during execution.
If a referenced logical address corresponds to a part of the process not
currently in physical memory, a page fault (or segment fault) occurs,
triggering the OS to load the missing part from secondary storage into
physical memory.
Implementation: Commonly implemented using Demand Paging (#10) or
Demand Segmentation.

10. Demand Paging

Concept: A specific implementation of virtual memory using the paging

technique (#6). Instead of loading all pages of a process into memory before
execution, pages are loaded only when they are actually accessed
(demanded). Often referred to as a "lazy swapper" – it only swaps a page into
memory when it's needed.
Mechanism:
When a process starts, the OS loads only a few (or none) of its pages into
physical memory frames.
The page table entries for pages not currently in memory are marked as
invalid (using a valid-invalid bit associated with each entry). Entries for
pages in memory are marked valid and contain the corresponding frame
number.
Page Fault Handling:
1. CPU generates a logical address for a page p .
2. MMU attempts translation using the page table.
3. If the page table entry for p is marked invalid, the MMU triggers a
page fault trap to the OS.
4. OS Response (Page Fault Handler):
a. Check if the logical address was actually valid (within the
process's address space) but the page was just not in memory. If the
 address itself is invalid (outside the process's defined space),
terminate the process.
b. Find a free physical memory frame. If no frame is free, select a
victim frame using a page replacement algorithm (#13). If the
victim frame contains modified data (dirty bit is set), write its
contents back to secondary storage (swap out).
c. Schedule a disk operation to read the required page p from
secondary storage into the now-available frame.
d. Update the page table entry for p : set the valid-invalid bit to valid,
store the new frame number, and clear the dirty bit.
e. Restart the instruction that caused the page fault. The instruction
can now complete as the required page is in memory.
Advantages: Less I/O needed at process startup, less memory needed per
process, allows for higher degree of multiprogramming, supports very large
virtual address spaces.
Disadvantages: Potential delay due to page faults during execution.
Performance heavily depends on the page fault rate.

11. Copy-on-Write (CoW)

Concept: An optimization strategy primarily used during process creation

(e.g., via the fork() system call in Unix-like systems) to delay or avoid
copying large amounts of data.
Mechanism:
1. When a process creates a child process ( fork() ), instead of immediately
duplicating all the parent's pages for the child, the OS allows both parent
and child to share the same physical frames initially.
2. These shared pages are marked as read-only in the page tables of both
processes, even if they were originally writable.
3. If either process attempts to write to a shared page:
a. A protection fault (trap) occurs because the page is marked read-only.
b. The OS recognizes this as a CoW fault.
c. The OS allocates a new physical frame.
d. The OS copies the contents of the original shared page into the new
frame.
e. The OS updates the page table of the process that attempted the
write: the entry for the relevant page now points to the new frame, and
the page is marked as writable.
f. The write operation is allowed to proceed on the private copy.
4. Pages that are never written to remain shared, saving memory and the
time required for copying.
Advantages: Significantly speeds up process creation ( fork() ). Reduces
memory consumption, as pages are only duplicated if modified. Efficient for
 scenarios where the child process immediately executes a different program
( exec() ).

12. Performance (of Demand Paging)

Key Factor: The performance of demand paging is critically dependent on the

page fault rate (p) – the probability that a memory access will cause a page
fault.
Effective Access Time (EAT): The average time taken for a memory access.
It's calculated considering both normal memory access and the time taken to
handle page faults.

EAT = (1 − p) × ma + p × pf t

Where:
p = Page fault rate (0 ≤ p ≤ 1)
ma = Memory Access time (e.g., 100 nanoseconds)
pf t = Page Fault Time (time to service a page fault)
Page Fault Time (pft): This is the dominant factor. It involves:
Trapping to the OS.
Saving process state.
Checking page validity.
Finding a free frame (potentially involving page replacement).
Disk I/O: Reading the page from disk (swap-in). This is very slow
(milliseconds) compared to memory access (nanoseconds).
Potentially writing the victim page to disk (swap-out).
Updating page tables.
Restoring process state and restarting the instruction.
Impact: Because pft is orders of magnitude larger than ma (milliseconds vs.
nanoseconds), even a small page fault rate p can drastically increase the EAT
and degrade system performance. For acceptable performance, p must be
extremely low. Example: If ma = 100 ns and pft = 10 ms (10,000,000 ns), even
with p=0.001 (1 fault per 1000 accesses), EAT = (0.999 100) + (0.001
10,000,000) = 99.9 + 10,000 = 10,099.9 ns, which is a ~100x slowdown
compared to no page faults.

13. Page Replacement Algorithms

Purpose: When a page fault occurs and there are no free physical frames
available, the OS must choose an existing page in memory (a "victim" page) to
remove (swap out to disk) to make room for the required page. The goal of the
algorithm is to select the victim page that minimizes the likelihood of needing
that page again soon, thus minimizing future page faults.
Common Algorithms:
FIFO (First-In, First-Out):
 Mechanism: Treats page frames allocated to a process like a queue.
The oldest page (the first one brought into memory) is selected as
the victim.
Implementation: Simple, requires only a queue structure.
Disadvantage: Often performs poorly because the oldest page might
be a frequently used variable or part of the code. Suffers from
Belady's Anomaly: increasing the number of allocated frames can
sometimes increase the number of page faults.
Optimal (OPT or MIN):
Mechanism: Selects the page that will not be used for the longest
period of time in the future.
Implementation: Unimplementable in practice because it requires
predicting the future sequence of memory references.
Advantage: Guarantees the lowest possible page fault rate for a
given reference string and frame allocation. Used as a benchmark to
evaluate other algorithms.
LRU (Least Recently Used):
Mechanism: Selects the page that has not been referenced for the
longest period of time in the past. Based on the heuristic that pages
used recently are likely to be used again soon (locality of reference).
Implementation: More complex. Requires hardware support to track
usage time. Common methods:
Counters: Each page table entry has a counter; on memory
reference, copy the system clock to the counter. Victim is the
page with the smallest counter value (requires searching).
Stack: Maintain a stack of page numbers. On reference, move
the page number to the top. Victim is the page at the bottom
(requires stack updates on every access).
Advantage: Generally good performance, good approximation of
OPT, does not suffer from Belady's Anomaly.
Disadvantage: Significant overhead without hardware support.
Approximations are often used.
LRU Approximations (e.g., Second-Chance / Clock Algorithm):
Mechanism: Uses a reference bit associated with each page entry
(set by hardware when page is accessed). Organizes frames in a
circular buffer with a pointer (clock hand). When a victim is needed:
1. Check the reference bit of the page pointed to by the hand.
2. If bit is 0: Select this page as the victim.
3. If bit is 1: Clear the bit (give it a second chance) and advance
the clock hand to the next page. Repeat step 1.
 Advantage: Much lower overhead than true LRU, generally performs
well.
Other Algorithms: Least Frequently Used (LFU), Most Frequently Used (MFU),
various clock variations exist.

14. Thrashing

Concept: A phenomenon in virtual memory systems where the system spends

an excessive amount of time paging (swapping pages between RAM and disk)
instead of performing useful computation. It leads to severely degraded
performance and low CPU utilization.
Cause: Occurs when processes running on the system do not have enough
physical memory frames allocated to them to hold their working set – the set
of pages actively needed for execution at a given time.
Mechanism/Symptoms:
1. A process experiences a high rate of page faults because its necessary
pages are constantly being swapped out.
2. The OS spends a lot of time handling these page faults (disk I/O).
3. CPU utilization drops because processes are often waiting for pages to be
loaded.
4. The OS scheduler might observe the low CPU utilization and conclude
that it needs to increase the degree of multiprogramming (admit more
processes into the system).
5. Admitting more processes further reduces the number of frames available
to each process, exacerbating the problem and leading to even more
page faults. This creates a vicious cycle.
Detection: Monitor page fault frequency and CPU utilization. High page fault
rate combined with low CPU utilization is a strong indicator of thrashing.
Prevention/Solution:
Working Set Model: The OS estimates the working set size for each
process and ensures each process has enough frames allocated to hold
its working set. If not enough memory is available, suspend some
processes (reduce degree of multiprogramming).
Page-Fault Frequency (PFF): Monitor the page fault rate for each
process. If the rate exceeds an upper threshold, allocate more frames. If it
falls below a lower threshold, potentially remove frames. If more frames
are needed but none are available, suspend a process.
Local Replacement: Use page replacement algorithms that only consider
the frames allocated to the faulting process itself (local scope), rather
than choosing a victim from any frame in the system (global scope). This
prevents one thrashing process from stealing frames from well-behaved
processes.
Increase RAM: Add more physical memory to the system.