Lecture 11
Placement – Part III
VLSI Physical Design Fundamentals
Bach Luong
Tresemi
© Tresemi 2024 VLSI Physical Design Fundamentals 1
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 2
Power Analysis
Data Import
• Estimation of power dissipation (static and dynamic) in the design
• Static power analysis is the calculation of leakage power even when cell is not
switching
Floor Pre-
Planning
• Dynamic power analysis is the calculation of dynamic power dissipated by cell due
placement
to switching and short circuit
• Power analysis estimation usually done in several stages throughout the design
cycle, placement (less accurate), postroute (more accurate using simulation input
Placement switching activity.
Placement
CTS Post-
placement
Routing
Data Export
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Power Analysis
Data Import
There are three types of power dissipation
• Dynamic power - Switching current
• Internal power - Short circuit current
Floor Pre- • Static power - Leakage current
Planning placement
• Dynamic power
- Power dissipation when logic gates change state from 0 to 1 or 1 to 0.
- Frequency, voltage, load capacitance dependent, and switching activity factor.
• Internal power
Placement Placement - Power dissipation when both P and
N transistors are shorted (direct
path) when changing states. Usually
internal power is < %10 of dynamic power
CTS Post- - Voltage, short circuit current and frequency
placement dependent
• Static power
- Power dissipation due to leakage current
Routing when logic gates in idle stage
- Voltage, switching threshold voltage,
and transistor size dependent
Data Export
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Power Analysis
Data Import
Ptotal = Pswitching + Pshort-circuit + PLeakage
Floor Pre- Pswitching = Af * Cload * (VDD ^2) * F
Planning placement Pshort-circuit = VDD * Isc * F
PLeakage = VDD * Ileakage
Where,
Placement Placement F = Frequency
Cload = Capacitive loading due to pin and nets
Af = Switching activity factore
VDD = Supply Voltage
CTS Post- tsc = Short circuit time in cmos
placement Isc = Short circuit current from pmos to nmos
Ileakage = Leakage current
Routing
Data Export
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Power Analysis
Data Import
Leakage Current Components
• Gate leaking current
Floor Pre- - Also known as gate oxide tunneling leakage. Current flow as the result of gate voltage
Planning placement electric field and drain voltage electric field.
• Subthreshold leaking current
- Happen when gate voltage is below threshold voltage, current flow from drain to source
• Reversed biased leakage current
Placement - Occur when source or drain of nmos at Vdd or
Placement
pmos at Vss. A reversed PN diode is formed at
the source or drain causing current to flow thru
substrate.
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 6
Power Analysis
Data Import
Leakage vs Dynamic Power Trend
Floor Pre- • Leakage current increase exponentially in lower geometries
Planning placement - Lower voltage => lower Vth => increase leakage
- Thinner gate oxide => increase leakage
Placement Placement
CTS Post-
placement
Routing
Data Export
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Power Analysis
Data Import
Static Power Analysis
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
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Power Optimization
Data Import
• Swapping cells with lower power
• Deleting buffers/inverters
Floor Pre- • Without degrading timing
Planning placement • To run power optimization in pre_cts mode
- set input switching activity
set_default_switching_activity –global_activity 0.2 –sequential_activity 0.8
Placement Placement
- Instruct tool to optimize both dynamic and leakage power equally
set_db opt_leakage_to_dynamic_ratio 0.5
CTS - Instruct tool to optimize both dynamic and leakage power and make trade off
Post-
placement to balance both
set_db opt_leakage_to_dynamic_ratio 0.5
Routing - Run power opt
opt_power –pre_cts
Data Export
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Power Optimization
Data Import
Power optimization log
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
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Area Optimization
Data Import
• Downside cells to smaller to reduce area
• Deleting buffers/inverters
Floor Pre- • Without degrading timing or introduce new DRV violations
Planning placement • Tool only targets positive slack nets
• This step happens by default after timing optimization step
• Or can be run explicitly
Placement Placement opt_area
CTS Post-
placement
INV8X INV4X
Downsizing Removed buffer
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 11
Area Optimization
Data Import
• Area optimization log
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement • Report area
report_area -summary
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 12
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 13
Tiecells Insertion
Data Import
What is a Tiecell?
• Design to provide a safe way to connect a high or low signal to input gate of a logic gate.
• Directly tie input gate to VDD or VSS rail may damage gate oxide during fabrication in lower
Floor Pre- geometry technologies (antenna effect).
Planning placement
Tie-high
- Output is always high and is used to tie logic input gate to high (VDD)
Tie-low
Placement Output is always low and is used to tie logic input gate to low (VSS)
Placement
CTS Post-
placement
Routing
Tie_low cell
Tie_high cell
Data Export
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Tiecells Insertion
Data Import
Netlist before tiecells insertion
• Contain 1’b0 and 1’b1
Floor Pre-
Planning placement
Placement Placement
Netlist after tiecells insertion
CTS Post- • All 1’b0 replace by tielo cells
placement • All 1’b1 replace by tiehi cells
Routing
Tiecells constraints
• Max fanout limit
• Max distance
Data Export
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Tiecells Insertion
Data Import
Adding Tie cells
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 16
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 17
Adding Spare cells
Data Import
Spare cells
• Extra cells that add to design for future ECO usage
• ECO : engineering change order (design changes) - due to timing or functionality - pre or post silicon
Floor Pre- • Spare cells generally consist of a group of variety cells (combinatorial cells and FFs)
Planning placement • Spare cells can be added to the netlist by designer or by APR tool during placement
• Spare cells input are normally tied to either VDD or GND through tie cells and outputs can be left floating
• Tool automatically spread throughout the design
• Added before or after placement
Placement Placement
Advantage of using spare cells
• Reusability – ECO can be carried out using metal layers only.
I base layers (below M1) can be re-used.
CTS Post- • Cost saving – only need new mask sets for metal layers changes.
placement • Cycle time reduction – enable quick changes by rewiring metals
Disadvantage of using spare cells
• Increase static power
Routing • Increase area
Data Export
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Adding Spare cells
Data Import
Adding Spare cells
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 19
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 20
Multi Bit Flip Flop (MBFF)
Data Import
What is MBFF?
• A flip flop with multiple input and output bits
• Create as the result of combining multiple single bit flip flops
Floor Pre- • Pre-built as a library cells with various bits configuration (4, 8, 16…etc)
Planning placement • MBFF optimization take place during in post placement opt stage
Placement Placement
CTS Post-
placement
Routing Benefits
• Area reduction
• Power reduction
• Better clock skew control
Data Export • Timing improvement
© Tresemi 2024 VLSI Physical Design Fundamentals 21
Multi Bit Flip Flop (MBFF)
Data Import
MBFF Optimization
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 22
© Tresemi 2024 VLSI Physical Design Fundamentals
References
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▪ Cadence RAK
© Tresemi 2024 VLSI Physical Design Fundamentals 24
