Introduction to VLSI Physical Design

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⚫ Recap on Design Flow Website: https://www.sites.google.com/view/learnvlsi
⚫ A quick refresh on synthesis
⚫ Introduction to Physical Design
⚫ Inputs and Outputs for Physical Design
⚫ Floor planning
⚫ Basics of Physical Cells
⚫ Power Planning
⚫ Placement of Memories (Macros)
⚫ Placement of Standard Logic Cells
⚫ Placement of IOs

Ganesh Prabhu C, ~20 years experience

https://www.linkedin.com/in/ganesh-prabhu-2414254/
Introduction to VLSI Physical Design
Website: https://www.sites.google.com/view/learnvlsi
⚫ Clock Tree Synthesis LinkedIn: https://www.linkedin.com/company/learnvlsi

⚫ Routing
⚫ Optimizations during backend flows
⚫ Layout (GDS2) creation
⚫ Chip finishing (DRC / LVS / Timing Sign-off)
⚫ Tools used for Physical Design
⚫ References

Ganesh Prabhu C, ~20 years experience

https://www.linkedin.com/in/ganesh-prabhu-2414254/
Disclaimer
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 SoC Design Flow

©The VLSI Handbook: Design Principles,

Industry and Career Perspectives

Reference: Book “The VLSI Handbook: Design Principles, Industry and Career Perspectives”, Udit Kumar, Aditya Gupta, Sumit Soman
 SoC Design Flow

©The VLSI Handbook: Design Principles,

Industry and Career Perspectives
Reference: Book “The VLSI Handbook: Design Principles, Industry and Career Perspectives”, Udit Kumar, Aditya Gupta, Sumit Soman
 Quick Recap of Synthesis Flow
⚫ Synthesis
 The functional description of design in higher abstraction language
(RTL) is transformed into logic gates
 All transformations and optimizations are logical
 These transformation are timing aware
 All clocks are considered as ideal
 Net connecting each logic cells are not realistic
 Hold checks are not considered, as clock paths are ideal and net delays
are not realistic

Design RTL (Verilog /

VHDL / SystemVerilog)
Timing Constraints Synthesized
Synthesis
Verilog Netlist
Library Timing Views
Wire Load Models
Different Stages of Synthesis

Synthesis Generic Logic Cell Optimize Dump

Inputs Mapping Mapping outputs

read RTL Map to Generic Boolean&

Libraries Timing
read libraries Optimization
elaborate top Map to Technology
read SDC Libraries

report timing
Write netlist
What is a library
⚫ Library is a collection of cells which is used for implementing a
design
⚫ Cells in a library
 Standard Cell Library
 Logic Gates
– Combinational Gates – NAND, NOR, XOR, INV, BUF
– Sequential Gates – Flop, Latches, Clock Gating Cells
 IO Cell Library
 Power IOs
 Digital Ios
 Analog Ios
 Special Ios
 Macro Cell Library
 Memory Cells
 Hard Macro Cells
 Physical Cell Library
 Fillers, DECAP cells
 TAP Cells, TIE Cells
Different Views of Library Cells
⚫ Different views of libraries
 Timing views : Timing models
 nldm
 ccs
 Ecsm
 Abstract views : Basic layout of cells
 Layout views : Detailed layout of cells
 Behavior views : Functional behavior description
⚫ Different Options of cells
 Multiple VT cells
 HVT, SVT, LVT
 Multiple Drive Strengths
 Low drive cells
 Medium drive cells
 High drive cells
Synthesis Optimizations
⚫ Timing based optimization ⚫ Different Timing Paths
 Maximize performance  Reg to Reg Path
 In to Reg Path
⚫ Area based optimization  Reg to Out Path
 Minimize area  In to Out Path
⚫ Power based optimization
 Minimize Power

In to Reg Reg to Reg Reg to Out

Input D Q D Q Output

C C
Launch Path
Clock Net
Clock

Capture Path
Input Output

In to Out
Reg to Reg Path

tcombo

Q D Q

tcq tsu
C C
Launch Path
Clock Net

Capture Path
Timing Requirement
⚫ Basic Timing Requirement

 Max Delay : t > tcq + tcombo + tsu

 Min Delay : tcq + tcombo > tho

Data
D Q D Q Data Out

Launch Clock Capture Clock

C C

Clock

Launch Clock
Min Delay Max Delay

Capture Clock
In-Out, In-Reg and Out-Reg Path

Reg to Out
In to Reg

Output
Input
D Q D Q Q D Q
D

C C C C

Clock

In to Out
Input Output
Q D Q
D

C C
Synthesis Optimizations - Power
⚫ Static Power
 Leakage Power
 The power consumed by the devices when the design is turned on.

⚫ Dynamic Power
 Internal Power
 The power consumed by the gates when the inputs are changing,
but the outputs are not changing
 Dynamic Power
 The power consumed by the gates when the inputs are changing
and the outputs are also changing

Object Logical Physical

implementation implementation

Timing Power Timing Power

Logic gates Yes Yes No No

Memories Yes Yes No No

Macros Yes Yes No No

PG Nets NA NA NA No

Clock Nets No No No No
Signal Nets Yes No No No
Introduction to Physical Design

Logical World to Physical World

⚫ Description : Physical Design is the process, where the logical
circuit is transformed into physical geometries which can be
fabricated in a foundry.
⚫ Taking Care about power supplies, physical connections and
real clocks
⚫ During Physical Design, certain performance parameters are
ensured for the correct performance of the circuit and
manufacturability of the circuit.
 Performance
 Power
Verilog Netlist
 Area GDS2
 Yield
Timing Constraints Physical Design
Design DEF
Library Timing Views
Physical Netlist
Library Abstract Views
Technology Information
Building a 2 Bit Multiplexer Chip
Block Diagram Switch Diagram
A A
Z Z
B B
S

S
Logic Diagram
Truth Table A
A B S Z
1 0 0 1 S S Z
1 0 1 0

Logic Equation B
Z = S.A + S.B
NAND Representation of 2:1 Mux

S S Z

B
A Sequential Design

M1 D Q

C
A

S S Z D Q MOut
M2 D Q

C C

B
MSel D Q

MClk C
CMOS Inverter
Gate
Source Drain

VDD N N
Source
Gate
P – Well
Drain

A Z
Gate
Drain Source Drain

Gate
Source P P

VSS N – Well
CMOS Inverter

Source
VDD
VDD

N
Gate
Source

P – Well
Gate
A

N
Drain

A Z

Drain
Drain
Z

Drain
Gate
Source

P
Gate

VSS

N – Well
Source

VSS
CMOS Inverter Layout

VDD VDD VDD

Source
Gate

Drain

A Z A Z A Z
Drain

Gate
Source

VSS VSS VSS

NAND Gate Layout

VDD

Source Source
VDD
Gate
A Source
B Drain Drain

Z B
Drain

A Gate
Z
Source A Source Drain

Drain Source Drain

B Gate VSS
Source

VSS
MUX Layout
A VDD

S S Z Drain Source Drain

B VDD
VDD A
Source Drain

Drain Source Drain

Source Drain
Drain Source Drain B
B VSS Z
S
VDD A
Source Drain
A
Source Drain
Drain Source Drain Source Drain

Source Drain
B
VSS
VSS

A
Source Drain

Source Drain

VSS
Need for Floorplan

Bed Room 1

Kitchen
Living Room
Entrance Exit

Bed Room 2
Number of Flops in a SoC

Processor Number of Transistors

Intel 8085 6,500
Qualcomm Snapdragon 855 10,300,000,000
AMD Ryzen 9 9,890,000,000
Apple A15 15,000,000,000
Apple M1 16,000,000,000
Core 2 Duo 291,000,000
Nvidia GH100 80,000,000,000
Floorplanning
⚫ Floorplanning is the process of creating a physical plan for the design
to place the cells, IOs and Memories (Macros) in an optimized way to
meet connectivity between cells, timing, power and area.
⚫ Eg : Planning for a house construction.
 Where to place the doors and windows
 Where to build the hall, rooms, kitchen, bathrooms, etc .,
 Where to take the electric line from the electric post
 How to connect the electrical lines to each room
 How to create access to each rooms

Object Logical Physical

implementation implementation

Verilog Netlist Timing Power Timing Power

Logic gates Yes Yes No No

Timing Constraints
Memories Yes Yes No No

Floorplanning Floorplan
Library Abstract Views Macros Yes Yes No No
DEF
PG Nets NA NA NA No
Library Timing Views
Clock Nets No No No No
Technology Information Signal Nets Yes No No No
Why floorplanning is required
Exit
Kitchen Bath Toilet
Logic Gates Logic
Bedroom 2 Gates
Dining Hall

Hall
Bedroom 1 Memories

IOs
Entrance

⚫ Arrange the blocks in a chip

⚫ Decide the location of I/O (Input/Output) ⚫ Minimize chip area
pads
⚫ Minimize Delay
⚫ Decide the type of power distribution
⚫ Minimize congestion
⚫ Decide the type of clock distribution
How do we create floorplan ?
⚫ Utilization
 Refers to the percentage of core
area utilized by standard logic
cells
 High Utilization will make design
closure very complex
 High utilization will create routing
congestion causing routing shorts
and opens.
⚫ Aspect Ratio
⚫ Site Name
⚫ What is a Site Name ?
 Site defines the placement site in
a design
Eg : Core Site / IO Site / Macro Site
Row Creation
Standard Cell Row Sites

3 Sites
Basics of Physical Cells
⚫ Physical Cells are the cells used during physical
implementation of circuits to protect the circuit and meet a
physical need for a circuit.
⚫ No logic function exists for a physical cell
⚫ List of Physical Cells
 Well Tap Cell
 Endcap cell
 Decap Cell
 Tie Cell
 Antenna Cell
WellTap Cell
⚫ Well Tap Cell
 Well tap cells are used prevent latch-up in cmos circuits.
 Supply is connected to n-well of Well tap cell
 Ground is connected to p-well of well tap cell

Supply

Ground
Latchup
Gate Gate
Bias Source Drain Source Drain
Bias

P+ N+ N+ P P N

N–Well

P – Substrate

Gate A Gate
VSS VDD
Z

P+ N+ N+ P P N

R-Well

R-sub
N–Well

P – Substrate
Latch Up Cont ..
VSS VDD
V in (Gate)

E C
B

C
B

⚫ A small pulse in Vin (Gate) will turn on the SCR.

⚫ A feedback loop is created, and it continues to remain “on” even after the removal of Gate Supply
which is called “latch-up”
⚫ A low impedance path is generated between VDD and VSS creating a short circuit and damages
the CMOS
Endcap Cell
⚫ Functional logic cell placed in the boundary may get damaged
during fabrication. To avoid such damages, endcap cells are
placed on the edges of each rows of the block.

Endcap Cell Endcap Cell placed for a block

Different Types of Nets in a design
⚫ Signal Nets
⚫ Clock Nets
⚫ Power and Ground Nets
Signal Nets

Data
D Q D Q Data Out

C C

Clock

Clock Net
Power Planning
⚫ Power planning is an essential step.
⚫ Power planning is the flow step where the power network is created which is
used to provide power to standard logic cells, IO cells and macros
⚫ Bad power planning will cause voltage drop (IR Drop) and electromigration.

Object Logical Physical

implementation implementation
Verilog Netlist
Timing Power Timing Power
Timing Constraints Logic gates Yes Yes No No

Library Abstract Views

Power Floorplan Memories Yes Yes No No
Planning DEF Macros Yes Yes No No
Library Timing Views
PG Nets NA NA NA Partial
Floorplan DEF Clock Nets No No No No

Technology Information Signal Nets Yes No No No

IR Drop
⚫ Drop in supply voltage over the length of the supply line
 A power connection to each gate is considered as a node.
 A resistance network is created for each gate connecting the power line
 An average current of each gate is considered.
 The matrix is solved to determine the IR-Drop

VDD
VDD
PAD
Electromigration
⚫ Electromigration is a gradual shift of metal atoms of a
conductor as a result of the current flowing through the
conductor.
⚫ Can cause an open on a wire or a short with an adjacent wire.
⚫ Even without open or short, EM can cause change in RC
values

Reference : https://www.synopsys.com/glossary/what-is-electromigration.html
Addressing IR Drop & Electromigration

⚫ More Power Lines - Pros

 Less Static IR Drop
 Less Dynamic IR Drop
 Less Electromigration

⚫ More Power Lines – Cons

 High Congestion
 Less Routing resources as power lines, consumes signal routing
resources
Power Distribution Network
⚫ Function of Power Distribution Network
 Cary current from pads to transistors
on chip
 Maintain stable voltage with low noise
 Provide average and peak power
demands
 Provide current return path for signals
 Avoid electromigration
 Consume little chip area and wire
 Easy to create layouts

VDD
⚫ How Power Distribution Network is VSS
created ?
 PG Ring
 PG Stripes
Placement
⚫ Placement is a stage of the physical design flow, where each
instance is given an exact location.
⚫ All the gates and IO cells are placed in the rows created
during floorplanning.
⚫ Cells placement are timing aware and physical aware.
Placement
Special Route Creation
Macro Placement
⚫ Macros are big blocks which needs to
be placed like standard cells (gates) Memories
 Memories
 PLL
 Clock Divider Circuit
⚫ Macros such has memories, can be
moved to the boundary area (edges).
 Memories are huge and have many
input and output pins.
 Placing them in the middle will reduce
resources to route the logic gates Flash
 Increase congestion as they have Analog IPs Mem
many io pins

https://www.eng.biu.ac.il/temanad/files/
2018/12/Lecture-7-Placement.pdf
Placement Regions
⚫ Sometimes due to design requirement or placement congestion, we
help the tool to place certain logic in a certain region.

⚫ Following types of regions can

be created using the tools
 Soft Guide – try to group the
cells together during placement.
 Guide – try to place the cells in
the defined region.
 Region – Must place all the
cells in the defined region, but
other cells may also be placed
in the region.
 Fence – Must place the cells in
the defined region and keep out
all the cells

https://www.eng.biu.ac.il/temanad/files/2018/12/Lecture-7-Placement.pdf
Placement Blockage and Halo
⚫ Placement Blockage and halos are created so that no cells
are placed in that region.
 Hard Blockage – No cells can be placed in the defined region
 Soft Blockage – Cannot be used during placement but can be
used during optimization.
 Partial Blockage – A region where minimal cells can be placed.
 Halo – A region around macros, that has no cells and used only
for routing the macro signals.
 IO Cell Placement
⚫ Types of IO Cells
 Digital IO Cells. Eg : MFIOs
 Analog IO Cells.
 Power IO Cells. Eg : Supply IOs
 Special IO Cells. Eg : LVDS
⚫ IO Row creation
 Similar to standard cell rows, IO
Rows are also created to place IO
Cells
IO Row

Verilog Netlist Object Logical Physical

implementation implementation

Timing Constraints Timing Power Timing Power

Floorplan Logic gates Yes Yes Yes Yes

Library Abstract Views Placement DEF Memories Yes Yes Yes Yes
Library Timing Views Macros Yes Yes Yes Yes

PG Nets NA NA NA Partial
Floorplan DEF
Clock Nets No No No No
Signal Nets Yes No No No
Clock Tree Synthesis (CTS)
⚫ Where we are now :
 The RTL is synthesized to gate level netlist.
 The floorplan for the design is completed.
 Each and every gate is placed on a site
⚫ Why we need to do CTS ?
 Clock nets are considered ideal (0 delay) during synthesis.
 Physical nets for the clocks are created during CTS
 During CTS, we ensure that all the flops of a clock group receive
the real clock.
 CTS is timing aware and require timing constraints to implement
clock tree
Clock Tree Synthesis (CTS)
⚫ Why can’t we route the clock net as any other signal net ?
 Clock nets have very high number of sinks. (Drives many flops)
 Clock nets run through out the block
 Impacts Timing, Power, Area etc.,
Timing Requirement
⚫ Basic Timing Requirement

 Max Delay : t + Δskew > tcq + tcombo + tsu + Δmargin

 Min Delay : tcq + tcombo - Δ margin > tho + Δ skew

Data
D Q D Q Data Out

Launch Clock Capture Clock

C C

Clock

Launch Clock
Min Delay Max Delay

Capture Clock
Different Clock Parameters
⚫ Clock Skew
 Difference in clock arrival time at Q1
two different flops
Clock
⚫ Clock Jitter
 Difference in clock period Q2

between different clock cycles

⚫ Clock Slew
 Rise and Fall transition of a clock
⚫ Insertion Delay
 Difference from clock source to
registers
Ideal timing path Clock Skew

Clock arrival
reduced timing path
at Q1
Skew
reduced timing path
Clock arrival
at Q2 Clock Jitter
Ideal clock arrival at Q1 and Q2 Flops t1 t2
t1 = t2
Why do clock skew and jitter arise
⚫ Clock Generation
⚫ Clock Distribution Network
 Cells in clock network
 Variation in transistors in
clock network
 Wire length
 Coupling effects
 Load effects
⚫ Environment Variation
 Temperature
 Supply Voltage
 What does Clock Skew and Jitter cause
⚫ Clock skew and jitter reduces the timing margins

Launch Clock

Ideal Max Delay

Ideal Min Delay

Capture Clock

Launch Clock

Capture Clock
with +ve skew
+ve Skew

Capture Clock Jitter

with -ve skew
-ve skew
Impact on Power
⚫ Dynamic Power
Pdyn = f . Ceff . Vdd2
Ceff = α . Ctot = αclock . Cclock + αsig . Csig

Activity (α) of the clock network is almost 100%

⚫ Clock Capacitance
 Clock Generation Cells
 Clock path cells
 Clock nets
 Clock load of sequential elements

⚫ Clock networks are huge and they are responsible for large portion
of total chip power
Impact on Area
⚫ All the clock elements such as clock generation cells, clock
path cells, clock nets consume huge area as the clock cells
are spread across the chip.
⚫ Clock nets consume large amount of routing resources
 Require low RC for transition and power
⚫ Needs clock shielding to avoid noise on clock network
Impact on Signal Integrity
⚫ Noise on the clock network can cause:
 In worst case scenario, it can cause additional clock edges
 Low coupling can deteriorate clock propagation
 Irregular clock edges can cause functional failures
⚫ Slow clock transition
 Susceptible to noise
 Poor flop performance, causes bad tcq, tsu, th
⚫ Fast clock transitions
 Overdesign impacting area, power
 Act as aggressor to other signals
⚫ Unbalanced drivers lead to increased skew
Building a Clock Tree
Requirement
⚫ Connect all the clock tree elements (sinks), to the respective
clock network so as to minimize
 Clock Skew
 Insertion Delay
 Wirelength
 Noise and Coupling effects
⚫ Challenge
 Synchronize millions of separate clock elements within a time
scale of ~10ps
 Within a spanning distance of 2-4 cms
Approaches to CTS
⚫ Clock Tree
⚫ Clock Mesh
Clock Trees
⚫ Routing clock net similar to signal net
 Route the net to each sink and balance
RC
 Consumes too much power
 Large RC of net causes signal integrity
issues

⚫ Using Buffered Tree

 Short nets reduces RC
 Buffers improves slew rates
 Lower insertion delay
 Reduces total switching cap
Building a Clock Tree
⚫ Balanced Approach:
 H-Tree
 One large central driver
 Recursive H-style to match wire lengths
 Halve the wire widths at branching
points

⚫ Standard Approach:
 Try to build a balanced tree
 Clock tree elements are not
balanced evenly
PLL
Clock Concurrent Optimization
What is the main requirement ?
Skew minimization and reducing insertion delay
or
Meeting timing (+ DRV constraints)

The new approach is called Clock Concurrent Optimization

(CCOpt)
CCOpt
⚫ CCOpt Methodology
 First build the clock tree in order to fix the DRVs
 DRV : max fanout, max capacitance, max transition and max length
 Minimize skew and insertion delay by buffering the nets
⚫ Why is this a good approach
 Mostly all timing paths are local
 Therefore, they come from the same clock and don’t need much
skew balancing initially
⚫ Advantages of less skew balancing
 Lower insertion delay (power, jitter)
 Fewer clock buffers (power, area)
 Distribution of peak current (less IR drop)
 Options of useful skew (performance)
Clock Net Routing
⚫ Clock nets are very important in terms of Signal Integrity
 In worst case, a glitch on a clock net will cause an additional
clock edge.
 Slow transitions will cause setup / hold failures
 Fast transitions acts as aggressors to other signals.

⚫ Hence:
 We will pre-route the clock nets during CTS
 Use higher and thicker metals for clock routing
 Offers low resistance
 Offers less cap with the substrate
 Apply shielding to clock nets
 Consider adding DECAPs close to clock buffers
Post CTS Optimizations
⚫ Delay cell insertions
⚫ Sizing of cells in the clock tree
⚫ Buffers re-location
⚫ Useful skew
⚫ Gate re-location
⚫ Buffer re-sizing

Object Logical Physical

implementation implementation

Timing Power Timing Power

Logic gates Yes Yes Yes Yes

Memories Yes Yes Yes Yes

Macros Yes Yes Yes Yes

PG Nets NA NA NA Partial

Clock Nets Yes Yes Yes Yes

Signal Nets Yes No No No
Routing
⚫ All the logical connection between components needs a
physical connection to be manufactured
⚫ Millions of wires existing should be given physical shapes
⚫ All these physical wires should be with minimum delay and
also minimum wire-wire interactions
⚫ 100% connectivity should be ensured with available routing
layers with minimum area and wirelength
⚫ All the physical wires should follow the design rules based on
width, spacing, area, antenna rules, etc .,
Understanding Tracks
VDD Track 1

Drain Source Drain

Track 2
B
Track 3

A Track 4
Source Drain

Source Drain Track 5

VSS

⚫ A track means 1 M1 pitch M1

M1 pitch
M1

Pitch : Centre to Centre

spacing between 2
adjacent M1 Layers
How routing is performed
⚫ Different Stages of Routing
 Global Routing
 Track Assignment
 Detailed Routing
 Search and Repair

⚫ Multiple routing methods are used by the EDA tools to perform

routing
 Eg : Maze Algorithm, Steiner Tree Algorithm, Manhattan Routing
Global Route
⚫ Global route is coarse-grain routing.
⚫ The routing block is divided into tiles called Gcells
⚫ Tile to Tile net connections are identified and lengths are
optimized without making any physical connections
⚫ The ability to route between gcells depends on routing tracks,
number of nets in that gcell area and routing blockages.
⚫ Every gcell has horizontal and vertical routing resources
⚫ When the required number of resources > available number of
resources, it leads to congestion.
⚫ Congestion map can be used to check the Horizontal and
Vertical over-flow
Track Assignment
⚫ After gcell estimation, both horizontal and vertical tracks are
assigned for each global route.
⚫ It replaces all global route with actual metal layers
⚫ The number of metal layers and direction depends on the
technology parameters
⚫ These routed nets will have many DRC, SI and timing
violations at this stage
Detailed Route
⚫ Detailed router uses the global routing plan and the tracks
assignment and uses metal layers to connect the pins with the
nets
⚫ The violations in the previous stage is fixed using multiple
iterations.
⚫ Detail route tries to achieve complete all the net routes without
any shorts or opens.
⚫ All special routing rules are also taken into account in this
stage.

⚫ Search and repair identifies shorts and spacing violations, and

reroutes the affected nets to fix all violations.
Routing Constraints
⚫ Routing Blockage
 Similar to placement blockage, blockages can be defined for
routing as well.
 Routing blockage is defined for a specific metal layer
⚫ NDR – Non-Default Rule
 Special routing rules are created using NDR for critical or special
nets
⚫ Shielding
 Shielding are defined for sensitive nets

Object Logical Physical

implementation implementation

Timing Power Timing Power

Logic gates Yes Yes Yes Yes

Memories Yes Yes Yes Yes

Macros Yes Yes Yes Yes

PG Nets NA NA NA Yes

Clock Nets Yes Yes Yes Yes

Signal Nets Yes Yes Yes Yes
Signal Integrity
⚫ Signal Integrity in routing is nothing but crosstalk
 A switching net may affect a neighboring net
 The net which is switching is called aggressor
 The net affected in a victim net
⚫ Effects of signal integrity
 Signal slows down when aggressor and victim switch in opposite
directions
 Signal speeds up with aggressor and victim switch in same
direction
⚫ Solutions for SI
 Reduce the length of parallel wires
 Spread the wires causing SI
 Shield special and sensitive nets
 Upsize the driver or add a buffer
Extraction
Extraction is the step where the R&C of the nets are extracted
based on the length, metal spacing and max surface area of the
metal layer.
Five Parasitic corners are:
1. Cbest – minimum capacitance,
minimum delay (Hold analyses)
2. Cworst – maximum capacitance,
maximum delay (Setup analyses)
3. RCbest – minimum RC product
(Long interconnects)
4. RCworst – maximum RC product
(Long interconnects)
5. Typical – nominal values of RC

Reference : Signoffsemi.com
Timing Sign-Off
1Sec
⚫ Best Case – Worst Case Timing
 Setup Checks :
 Data Path with max delay
 Clock Path with min delay
 Hold Checks : Open Open
 Data Path with min delay
 Clock Path with max delay Closed Closed

tcombo

Q D Q

tcq tsu
C C
Launch Path
Clock Net

Capture Path
On Chip Variation
On Chip Variation
 Process/Voltage/Temperature (PVT) variation
can affect different parts of the timing path in
opposite directions
 Adjust the worst possible scenarios with derates
 Setup Checks :
 Data Path with max delay + derate factor
 Clock Launch Path with min delay + derate factor
 Clock Capture Path with min delay – derate factor
 Hold Checks :
 Data Path with min delay – derate factor
 Clock Launch Path with min delay - derate factor
 Clock Capture Path with max delay + derate factor
Timing – Pessimism / Optimism
⚫ If you are too optimistic, your chip may not work
⚫ If you are too pessimistic, it is painful for timing closure
 Time-to-market increases
 Performance is hindered
 Less efficient in performance, power and area

⚫ Let us try to understand if bc-wc and OCV are pessimistic and

remove if any
Clock Reconvergence Pessimism Removal

D Q D Q

Launch Path C C

Clock Net

Capture Path

 Setup Checks :
 Data Path with max delay + derate factor ⚫ Applying CRPR limits the pessimism
 Clock Launch Path with min delay + derate factor of OCV
 Clock Capture Path with min delay – derate factor
 Hold Checks : ⚫ This removes the derating from the
 Data Path with min delay – derate factor clock path shared by both lauch and
 Clock Launch Path with min delay - derate factor
 Clock Capture Path with max delay + derate factor
capture paths
Advanced on-chip variation (AOCV)

https://vlsi-soc.blogspot.com/

⚫ Do all the paths derate the same way ?

⚫ Variation is statistical and hard to compute
⚫ Worst case variations in a path depend on
 Distance between the gates
 Depth (no of stages) of the path.
Parametric OCV
⚫ AOCV is better, but still too pessimistic
⚫ Variation is statistical, so we use Parametric OCV called LVF
(library variation format) which is statistical
Chip Finishing
⚫ Filler and Decap Insertion
 Fill the blank spaces with fillers / decaps to ensure continuous
well across the rows
⚫ Antenna Checking
 During etching of long metals, accumulated ions carry a huge
charge which can cause the damage to gate oxide
⚫ Metal Density Filling
 Very less area of metal in a square are will cause over-etching.
To avoid over-etching dummy metal fills are done.
⚫ IR and EM Analysis
⚫ Logic Equivalence Checking
 The equivalence between input and output design data is
checked in different stages to ensure the optimizations doesn’t
cause functional failures.
Chip Finishing
⚫ Physical Verification
 DRC
 The GDS extracted from the implementation tool are checked for
design rules, which ensures all physical geometries will be
manufactured properly.
 LVS
 LVS ensures that the LAYOUT (GDS) created from the physical
implementation tool is equivalent to the Schematic of the design.
 ERC
 Ensures there are no floating gates, floating wells in the design.
Few of the EDA tools used in Digital Design

Flow Steps Cadence Synopsys

Simulation Xcelium VCS
Synthesis Genus Design Compiler
Formal Check Conformal Formality
Place and Route Innovus ICC2
Timing Analysis Tempus Primetime
Power Analysis Voltus Primepower
Extraction Quantus StarRC
DFT Modus Tetramax
SignOff PVS IC Validator
Reference
⚫ Adam Teman lecture slides
⚫ CMOS VLSI Design
⚫ VLSI Physical Design – From Graph Partitioning to Timing
Closure
⚫ General web search links
 Thank you
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