Explain the working of a 4-bit parallel adder with the help of a block diagram.

Differentiate
between combinational and sequential Circuits based on at least five key points.

Parallel Adder

The parallel adder shown in Figure 1 is a 4-bit parallel adder as it can add two binary number of
4 bits. Although, we can design a parallel adder circuit for any number of bits by increasing the
number of full adders in the chain.

In the above parallel adder circuit, the bit A is representing the augend bits and B is
representing the addend bits. The first input carry bit to the parallel adder is Cin and the output
carry bit of the parallel adder is C4. The output sum bits are designated by S. We can also
construct a parallel adder in the form of an IC. For example, when the 4-bit parallel adder is
formed in the IC form, then it will have four terminals for augend bits, 4 terminals for addend
bits, 4 terminals for sum bits, and 2 terminals for input and output carry bits.

Working of Parallel Adder

The parallel adder shown in figure-1 performs the binary addition of two numbers as per the
following step −

Step 1 − Firstly, the full adder circuit FA1 adds the bits A1 and B1 along with the input carry bit
Cin to produce the sum bit S1, where it is the LSB (Least Significant Bit) of the output sum. At
this stage, a carry bit C1 is generated which is transferred to the next full adder circuit in the
chain.
Step 2 − The full adder circuit FA2 adds bits A2 and B2 along with the carry bit C1 from the
previous addition. It produces the sum bit S2 which is the second bit of the output sum, and a
carry bit C2 is also produced which again forwarded to the next full adder FA3.

Step 3 − The full adder circuit FA3 adds inputs bits A3 and B3 along with the carry bit C2 from
previous addition to produce sum bit S3 and carry bit C3.

Step 4 − The full adder FA4 adds input bits A4 and B4 along with the carry bit C3 forward from
FA3. It generates the last sum bit S4 and a last carry bit C4.

Step 5 − The output sum of the parallel adder is then given by,

Sout=C4S4S3S2S1

SR Latch

The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates with two inputs labelled S (for Set) and R (for Reset) and with two complementary outputs
Q and Q’.

SR latch using NOR gates

The SR latch constructed using two cross-coupled NOR gates is shown in Fig.1. The latch has two
useful states. When output Q=1 and Q’= 0, the latch is said to be in the Set state. When Q= 0
and Q’=1, it is in Reset state. Normally, outputs Q and Q’ are complement to each other.

Working of SR NOR latch

Case 1: When S=0 and R=1, then by using the property of NOR gate (if one of the inputs to the
gate is 1 then the output is 0), therefore the output Q=0 since R=1 and if Q=0 and S=0 then Q’
becomes 1, hence Q and Q’ are complement to each other. This is the Reset condition as output
Q=0 when R=1.

Now if R goes back to 0, the circuit remains in the Reset state i.e in another word if we remove
the inputs i.e. S=0 and R= 0, then let if Q’ =1 then again by using the property of NOR gate Q
becomes 0, it seems we get the previous output which gets stored in the latch, therefore S=0
and R=0 are called as memory condition.

Case 2: When S=1 and R=0, then by using the property of NOR gate, we get Q’ =0 and now if
R=0 and Q’ =0 then Q becomes 1 which is the condition for the Set state. Similarly, if S goes back
to 0, then the circuit will remain in the set state, i.e. S=0 and R=0 is the memory or hold state
which means latch is holding or storing the previous output.

Case 3: When S=1 and R= 1, then both the outputs Q and Q’ becomes 0 by using the property of
NOR gate, which violates the requirement that both the outputs must be complement of each
other. In normal operation, this condition is avoided by making sure that 1’s are not applied to
both the inputs simultaneously.

Explain the working of an SR (Set-Reset) Latch using NAND gates including the circuit diagram, truth table.
SR latch using NAND gates

The SR latch using two cross-coupled NAND gates is shown in Fig.2.

Fig. 2 SR Latch using NAND gate

Working of SR NAND latch

Case 1: When S=0 and R=1 then by using the property of NAND gate (if one of the inputs to the
gate is 0 then the output is 1), therefore Q becomes 1 as S=0, putting the latch in the Set state
and now since Q= 1 and R=1 then Q’ becomes 0, hence Q and Q’ are complement to each other.
Now when the S input goes back to 1, the circuit remains in the set state, which means when
S=1 and R= 1, the latch is in memory state i.e. holding the previous output.

Case 2: When S=1 and R=0 then Q’ becomes 1 and since Q’=1 and S=1 then Q goes to 0, putting
the latch in the Reset state and both the outputs Q and Q’ are complement to each other.
Similarly, when the R input goes back to 1, the circuit remains in the reset state, which simply
means when S=1 and R=1 the latch is in-memory state.

Case 3: When both the inputs S and R are 0 then by using the property of NAND gate we get
both the outputs Q and Q’ equals to 1, which violates our assumption of complementary
outputs, hence this condition is not used when operating with NAND SR latch.

The truth table of SR NAND latch is given below

What is a D Latch?
A D latch can store a bit value, either 1 or 0. When its Enable pin is HIGH, the value on the D pin
will be stored on the Q output. It builds upon the design of the S-R latch, with a few added logic
gates. You can see a D Latch circuit based on the S-R latch built with NAND gates below:

D Latch Circuit

The inverter on the input makes sure the S and the R inputs are always opposites, to avoid the
invalid state of both being 1. The two NAND gates create a new input, E (Enable), that lets you
control when you want to change the output to whatever is on the D input.

This means that the output Q can only change when the enable signal is 1. If it’s 0, the output is
unaffected by any changes on D.

You can also build a D Latch with AND and NOR gates as follows:

The D Latch can also be used to introduce delay in timing circuits, as a buffer, or for sampling
data at specific intervals
The truth table given below explains the operation of the D latch −

Inputs Outputs
Comment
D E Q Q'

0 0 Q Q' No change

0 1 0 1 Reset state

1 0 Q Q' No change

1 1 1 0 Set state

SR Flip Flop Construction using 2 NOR + 2 AND Gates:

SR Flip Fop
using two NOR and two AND Gates

SR Flip Flop Construction using 4 NAND Gates

SR Flip Flop using NAND Gate
Basic Block Diagram of SR Flip Flop

The basic block diagram contains S and R inputs, and between them is clock pulse, Q and Q' is
the complemented outputs.

SR Flip Flop basic Block diagram

Working of SR Flip Flop

 Case 1 : Let's say, S=0 and R=0 , then output of both AND gates will be 0 and the value of
Q and Q' will be same as their previous value, i.e, Hold state.

 Case 2 : Let's say, S=0 and R=1 , then output of both AND gates will be 1 and 0,
correspondingly the value of Q will be 0 as one of input is 1 and it is a NOR gate so it will
ultimately gives 0, hence Q gets 0 value, similarly Q' will be 1.

 Case 3 : Let's say, S=1 and R=0 , then output of both AND gates will be 0 and 1,
correspondingly the value of Q' will be 0 as one of input to NOR gate is 1, so output will
be 0 ultimately and this 0 value will go as input to upper NOR gate, and hence Q will
become 1.

 Case 4 : Let's say, S=1 and R=1 , then output of both AND gates will be 1 and 1 which is
invalid, as the outputs should be complement of each other.

Truth Table of SR Flip Flop

Given Below is the Truth Table of SR Flip Flop

Here, S is the Set input, R is the reset input,Qn+1 is the next state and State tells in which state
it enters

Function Table of SR Flip Flop

Given Below is the Function Table of SR Flip Flop

Here, S is the Set input, R is the reset input, Qn is the current state input and Qn+1 is the next
state outputs.

D Flip-Flop

Delay or D flip-flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters, shift registers, and input synchronization.

D Flip-Flop Circuit

In the D flip-flops, the output can only be changed at the clock edge, and if the input changes at
other times, the output will be unaffected.

Truth Table:

Clock D Q Q’
 ↓»0 0 0 1

↑»1 0 0 1

↓»0 1 0 1

↑»1 1 1 0

The change of state of the output is dependent on the rising edge of the clock. The output (Q) is
the same as the input and can only change at the rising edge of the clock.

Check the detailed explanation of D Flip Flop.