S.E.

[Information Technology]
Logic Design & Computer Organization
[214442]

Unit III Sequential logic design (06 Hrs)

 Title of Chapter: Sequential logic design
Contents: Introduction to sequential circuits: Difference between combinational circuits and
sequential circuits; Memory element – latch & Flip- Flop.
Flip- Flops: Logic diagram, truth table & excitation table of SR, JK, D, T flip flops; Study of flip flops
with regard to asynchronous and synchronous, Preset & Clear, Master Slave configuration ; Study of
7474, 7476 flip flop ICs.
Application of flip-flops: Counters- asynchronous, synchronous and modulo n counters, study of
7490, 74191 modulus n counter ICs & their applications to implement mod counters; Registers: shift
register types & applications ( SISO, SIPO, PISO & PIPO )
Unit Objectives
1.. Differentiate between combinational circuits and sequential circuits
2. Study of Flip- Flops and 7474, 7476 flip flop ICs.
3. Application of flip-flops
4. study of modulus n counter ICs & their applications to implement mod counters
5. Study of register types & applications

Unit outcomes: On completion the students will be able to

1. Differentiate between combinational circuits and sequential circuits
2. Study different types of Flip-flops and their applications

Mapping of Course Outcomes for Unit I: CO2

 Introduction to Sequential Circuits

• In many applications it is required to generate digital outputs in accordance

with the sequence in which the input signals are applied.
• Thus, these applications require that the outputs to be generated are not
only dependent on present input conditions. The outputs also depend upon
the past history of these inputs.
• The past history is provided by storing it in memory elements and
providing a feedback from the output back to the input.
• Such circuits are known as sequential circuits. Block diagram of a
sequential circuit is shown in next figure.
 Introduction to Sequential Circuits
Block diagram of sequential circuit
 Difference: Combinational & Sequential

• Digital circuits are broadly classified into two categories

1) Combinational & 2) Sequential.
I. In combinational logic circuits, output(s) at any instant of time depends on
the present input(s) applied at that instant of time.
In sequential circuits in which the output(s) not only depend on input(s),
but also depend upon the past history of input(s).
II. The combinational circuits are memoryless circuits while the sequential
circuits require memory for storing the past input(s).
III. Examples of combinational circuits are half adder, full adder, parity
generator, parity checker, multiplexers etc. while counters, registers,
sequence generators, sequence detectors are the examples of sequential
circuits.
 Difference: Combinational & Sequential

• The basic digital memory circuit is known as flip flop.

• Flip flop is developed from the circuit of cross coupled inverters which is
called as latch or one bit memory cell. So we shall start with latch / one
bit memory cell.
 Difference: Combinational & Sequential
Combinational Logic Circuits Sequential Logic Circuits
Output is a function of the present inputs Output is a function of clock, present inputs and
(Time Independent Logic). the previous states of the system.

Have memory to store the present states that is sent

Do not have the ability to store data (state). as control input (enable) for the next operation.

It does not require any feedback. It simply

It involves feedback from output to input that is
outputs the input according to the logic
stored in the memory for the next operation.
designed.

Used mainly for Arithmetic and Boolean

Used for storing data (and hence used in RAM).
operations.
Flip flops (binary storage device) are the
Logic gates are the elementary building blocks.
elementary building unit.
Independent of clock and hence does not Clocked (Triggered for operation with electronic
require triggering to operate. pulses).
Example: Counter [Previous O/P +1=Current O/P;
Example: Adder [1+0=1; Dependency only on
Dependency on present input as well as previous
present inputs i.e., 1 and 0].
state].
 What Exactly is Memory?

• A memory should have at least three properties.

1. It should be able to hold a value
2. You should be able to read the value that was saved
3. You should be able to change the value that’s saved
• We’ll start with the simplest case, a one-bit memory
1. It should be able to hold a single bit, 0 or 1
2. You should be able to read the bit that was saved
3. You should be able to change the value. Since there’s only a single bit,
there are only two choices:
• Set the bit to 1
• Reset, or clear, the bit to 0
 The Basic Idea of Storage

• How can a circuit "remember" anything, when it’s just a bunch of gates
that produce outputs according to the inputs?
• The basic idea is to make a loop, so the circuit outputs are also inputs
• Here is one initial attempt, shown with two equivalent layouts:

• Does this satisfy the properties of memory?

• These circuits "remember" Q, because its value never changes
(Similarly, Q' never changes either)
• We can also "read" Q, by attaching a probe or another circuit
• But we can’t change Q! There are no external inputs here, so we can’t
control whether Q=1 or Q=0
 Memory Element - Latch

• Latch / One bit memory cell, as the name suggests can store ‘one’bit (logic
0 or logic 1) information.
• It can be built using NAND or NOR gates.
• A one bit memory cell using NAND gates is as shown in the next figure
• It is also known as ‘S-R’(Set-Reset) latch.
• This circuit has two stable states: ‘1 state’ (output Q = 1) and ‘0 state’
(output Q = 0).
• ‘1 state’ is also called as ‘set state’ and the ‘0 state’ is known as ‘reset
state’. The digital information gets locked or latched in this circuit.
• Therefore it is known as S-R i.e. set-reset latch.
 The S-R Latch Circuit

• Let’s use NOR gates instead of inverters. The SR latch below has two
inputs S and R, which will let us control the outputs Q and Q'

• Here Q and Q' feed back into the circuit. They’re not only outputs,
they’re also inputs!
• To figure out how Q and Q' change, we have to look at not only the
inputs S and R, but also the current values of Q and Q':
Qnext = (R + Q'current)'
Q'next = (S + Qcurrent)'
• Let’s see how different input values for S and R affect this thing
 The S-R Latch Circuit
Storing a Value: SR = 00

• What if S = 0 and R = 0?
• The equations on the right reduce to:
Qnext = (0 + Q'current)' = Qcurrent
Q'next = (0 + Qcurrent)' = Q'current
• So when SR = 00, then Qnext = Qcurrent
Whatever value Q has, it keeps
Qnext = (R + Q’current )’
• This is exactly what we need to store values in Q’next = (S + Qcurrent)’
the latch
 The S-R Latch Circuit
Setting the Latch: SR = 10

• What if S = 1 and R = 0?
• Since S = 1, Q’next is 0, regardless of Qcurrent:
Q’next = (1 + Qcurrent)’ = 1’= 0
• Then, this new value of Q’ goes into the top NOR
gate, along with R = 0
Qnext = (0 + 0)’= 0’= 1
• So when SR = 10, then Q’next = 0 and Qnext = 1
• This is how you set the latch to 1. The S input Qnext = (R + Q’current)’
stands for “set” Q’next = (S + Qcurrent)’
• Once Qnext becomes 1, the outputs will stop
changing. This is a stable state
 The S-R Latch Circuit
Resetting the Latch: SR = 01

• What if S = 0 and R = 1?
• Since R = 1, Qnext is 0, regardless of Qcurrent:

Qnext = (1 + Q’current)’= 1’= 0

• Then, this new value of Q goes into the bottom

NOR gate, where S = 0

Q’next = (0 + 0)’= 0’= 1

• So when SR = 01, then Qnext = 0 and Q’next = 1Qnext = (R + Q’current)’

• This is how you reset, or clear, the latch to 0 Q’next = (S + Qcurrent)’
• The R input stands for “reset”
 The S-R Latch Circuit
What about SR = 11?
• Both Qnext and Q'next will become 0 Qnext = (R + Q’current)’
• This contradicts the assumption that Q and Q’next = (S + Qcurrent)’
Q’are always complements
• Another problem is what happens if we then
make S = 0 and R = 0 together 0 0
Qnext = (0 + 0)' = 1
Q’next = (0 + 0)' = 1
0 0
• But these new values go back into the NOR
gates, and in the next step we get:
Qnext = (0 + 1)' = 0
Q’next = (0 + 1)' = 0
0 1
• The circuit enters an infinite loop, where Q
and Q’ cycle between 0 and 1 forever
• This is actually the worst case, but the moral
is don’t ever set SR=11! 0 1
 S’R’ Latch

• There are several varieties of latches

• You can use NAND instead of NOR gates to get a S’R’latch
S’ R’ Q
1 1 No change
1 0 0 (reset)
0 1 1 (set)
0 0 Avoid!

• The input signals for the NAND latch are the complement of the
signals for the NOR latch, hence the name S’R’latch
• You can derive this table by writing equations for the outputs in terms
of the inputs and the current state, just as we did for the SR latch
 An SR Latch with a Control Input

• Here is an SR latch with a control input C

C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
 An SR Latch with a Control Input

• Notice the hierarchical design!

– The dotted blue box is the S’R’latch from the previous slide
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’latch
• The control input acts just like an enable. Latch can only change when C =
1, all other times the circuit remains in the same state no matter what values
are on the S and R inputs
 Combinational Logic Circuits

• The term "combinational" comes to us from mathematics which means an

unordered set where nobody cares which order the items came in
• With combinational logic, the circuit always produces the same output
solely by a given set of inputs , regardless of the order the inputs are
changed
– If there are m outputs and n inputs then there are m Boolean functions,
one describing each outputs
• The inside of a combinational circuit is made of logic gates and it does not
store any information (i.e. memoryless)
– There are circuits which depend on inputs and previous outputs. These
circuits are called sequential logic where we will discuss in later
chapter
• Combinational logic circuits are important components of digital systems
 Clocks and Synchronization

• A clock is a regular periodic signals whose output continuously

alternates between 0 and 1
duty cycle (in this case, 50%)

period
• The time between two consecutive ticks is called the clock period
• The clock frequency is the inverse of the clock period. The unit of
measurement for frequency is the hertz
• Clocks are often used to synchronize circuits
• Duty-cycle
– Fraction of the total period that a digital waveform is in the HIGH
state
– Usually expressed as % of period
 Clock Pulse Definition

• Edges can also be referred to as leading and trailing

 Flip-Flop vs. Latch

• The primary difference between a D flip-flop and D latch is the

EN/CLOCK input
• The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s is
designed to change its output at the edge (rising or falling) of a controlling
CLOCK input signal
• The latch’s EN input is level sensitive, meaning the latch’s output changes
on the level (high or low) of the EN input
 Edge Triggered Flip-Flops

• An edge triggered flip-flop changes state either at the positive edge (rising
edge) or a the negative edge (falling edge) of the clock pulse
• Its sensitive to inputs only at this transition of the clock
• Each flip-flop can be either positive edge triggered (no bubble at the C
input) or negative triggered (bubble at the C input)
 SR Flip Flop

• To overcome the drawback of the latch, a modified circuit with 2 input

NAND gates and two additional inverters is designed as shown in next
figure.
• It has 2 inputs S & R as shown therefore known as SR flip flop.
• It is called as one bit memory cell with provision for entering data as the
desired digital information can be entered in this circuit.
• This circuit is with 2 input NAND gates N1 and N2 and two additional
inverters N3 and N4 is as shown in figure.
• SR Flip Flop SR Flip Flop

• Clocked SR Flip Flop

 S-R Flip Flop: Preset & Clear Inputs

• The circuit of clocked S-R flip flop shown earlier switches to either set
state or reset state when the power is turned on i.e. the state of the circuit is
uncertain.
• In many applications it is required to define the initial state of the flip flop
when the power is turned on.
• This is accomplished by using the preset & clear inputs.
• Preset & clear inputs are known as asynchronous inputs as they do not
work in synchronism with the clock.
• Clocked S-R flip flop with preset & clear inputs can be obtained by using
N1 and N2 NAND gates as 3 input gates as shown in the next figure.
 S-R Flip Flop: Preset & Clear Inputs

• Logic symbol of clocked S-R flip flop is as shown below,

 JK Flip Flop

• We know that in case of clocked S-R flip flop, for the input condition S = R
= 1 both the outputs Q and Q# try to become 1, which is not allowed and
therefore this input condition is prohibited.
• This drawback can be eliminated by converting S-R flip flop into a JK flip
flop.
• The data input J is ANDed with Q# to obtain S input and the data input K is
ANDed with Q to obtain R input as shown in figure.
• When J = K = 0, output of both AND gates is 0. Therefore, S and R both
become 0. So next state output Qn + 1 remains same as that of present state
output Qn.
 JK Flip Flop

• When J = 0 & K = 1, the output of upper AND gate is 0, so S = 0. If the

present state output Qn = 0, the output of lower AND gate is also 0 & R
becomes 0. For the input condition S = R = 0 the next state output
remains unchanged. But if the present state output Qn = 1, the output of
lower AND gate becomes 1 i.e. R becomes 1. With S = 0 &R = 1 input
combination the next state output Qn + 1 is reset. Thus for J = 0 & K = 1
input condition, irrespective of the present state Qn, the next state output Qn
+ 1 be is 0 i.e. the flip flop is reset.
 JK Flip Flop
• Similarly for J = 1 & K = 0 input condition, the next state output Qn + 1 is
certainly 1 i.e. the flip flop is set.
Race around condition
• The race around condition occurs for the input combination J = K = 1.
• Let us assume that initially the output Q is 0. With this the output of lower
AND gate becomes 0 & upper AND gate becomes 1. Therefore S becomes
1 & R becomes 0. This input combination of S-R causes output Q to
become 1.Thus the output changes from 0 to 1 after the time interval ∆t
equal to the propagation delay through AND gate and S-R flip flop. Now
we have J = K = 1 and output Q = 1.
• After another time interval ∆t, the output Q will change back to 0 and the
cycle repeats till CLK=1.
 JK Flip Flop
• At the end of the clock pulse the output Q is uncertain and this situation is
known as race around condition. It is shown in figure below,

• The race around condition can be eliminated if tON is made smaller than the
propagation delay ∆t.
• It can also be eliminated using the master slave JK (MSJK) flip flop.
 JK Flip Flop

• The operation of JK flip flop can be expressed with the truth table.

Inputs Output
Jn Kn Qn + 1
0 0 Qn
0 1 0
1 0 1
1 1 Qn#

• The logic symbol of JK flip flop is shown in figure.

 Master Slave JK (MSJK) Flip Flop

• Master slave JK flip flop is a cascade of two S-R flip flops as shown in
figure
 Master Slave JK (MSJK) Flip Flop

• As shown in figure, outputs of slave are fed back to the inputs of master.
Also clock is directly applied to the master while it is inverted and then
applied to the slave.
• When CLK=1, the master is enabled and the slave is disabled. The outputs
of master Qm and Qm# respond to the inputs J and K according to the truth
table. As long as CLK=1, Q & Q# outputs do not change as the slave is
disabled and therefore the fed back inputs of master also do not change.
• When CLK= 0, the slave is enabled and the master gets disabled. The
outputs Q and Q# change according to the outputs of the master Qm and
Qm#. As long as CLK = 0, Qm and Qm# outputs do not change as the master
is disabled and therefore Q and Q# outputs also retain their new values.
• Thus the race around condition gets eliminated.
 Master Slave JK (MSJK) Flip Flop

• The state of the master slave JK flip flop, changes at the negative transition
of the clock pulse.
• The logic symbol of master slave JK flip flop is shown below,

• The symbol ‘>’ at the CLK input indicates that output changes when the
clock makes a transition.
• The bubble indicates that the output changes when there is a negative
transition of the clock (i.e. when the clock changes from 1 to 0).
 D Flip Flop

• The truth table of D flip flop is as shown below,

Input Output
Dn Qn + 1
0 0
1 1

• Here Dn represents the present state input and Qn + 1 represents the next
state output.
• From truth table, it is clear that output is same as that of input therefore it is
known as ‘data’flip flop.
 T Flip Flop

• The truth table of T flip flop is as below

Input Output
Tn Qn + 1
0 Qn
1 Qn#

• Here Tn represents the present state input, Qn represents the present state
output and Qn + 1 represents the next state output.
 Excitation Table of Flip Flop

• In the design of sequential circuits, it is often required to find input

conditions so that desired next state of the circuit is obtained from the
present state of the circuit.
• These input conditions can be obtained using the excitation table of a
flip flop.
• The truth table of a flip flop specifies its operational characteristic while
the excitation table of a flip flop gives an idea regarding the present
input conditions along with present state, to obtain the desired next
state.
• Construction of excitation table is discussed here.
 Excitation table of S-R flip flop
• Let the present state of the S-R flip flop be Qn = 0 and the desired next
state be Qn + 1 = 0.
• As there is no change in the state of the flip flop (present state & next
state is same), from the first row of the truth table of S-R flip flop we
obtain the input condition as Sn = 0 & Rn = 0.
• Similarly from the third row of the truth table of S-R flip flop, it is clear
that whatever may be the present state, the next state of the flip flop is
certainly 0 for the input condition Sn = 0 & Rn = 1.
• By combining these two input conditions we conclude that, Sn input
must be 0 while Rn input can be 0 or 1 i.e. Rn input can be X (don't
care), to obtain next state Qn + 1 = 0 from the present state Qn = 0. This
gives first row of the excitation table of S-R flip flop.
 Excitation table of S-R flip flop

• Similarly input conditions can be found for remaining three combinations

of present state & next state. The excitation table is given below,

Flip flop inputs

Qn Qn + 1 Sn Rn

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0
 Excitation table of S-R flip flop

SR truth table Next state table

S R Qn+1 Qn Qn+1 S R
0 0 Qn 0 0 0 0
0 1 0 0 0 0 1
1 0 1 0 1 1 0
1 1 ? 0 1 1 0

SR excitation table 1 0 0 1
1 0 0 1
Qn Qn+1 S R
1 1 0 1
0 0 0 X
1 1 1 1
0 1 1 0
1 0 0 1
1 1 X 0
 J K Flip Flop

JK truth table Next state table

J K Qn+1
Qn Qn+1 J K
0 0 Qn
0 0 0 0
0 1 0
0 0 0 1
1 0 1
0 1 1 0
1 1 Qn’
0 1 1 1
JK excitation table 1 0 0 1
1 0 1 1
Qn Qn+1 J K
1 1 0 0
0 0 0 X
1 1 1 0
0 1 1 X
1 0 X 1
1 1 X 0
 D Flip Flop

D truth table Next state table

D Qn+1 D Qn Qn+1
0 0 0 0 0
1 1 0 1 0
1 0 1
1 1 1
D excitation table
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
 T Flip Flop

T truth table Next state table

T Qn+1
0 Qn T Qn Qn+1
1 Qn’ 0 0 0
0 1 1
T excitation table 1 0 1
1 1 0
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
 Study of IC 7474

• The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL).
• It is a 14 - pin IC which consists of two D flip-flops.
• The two flip-flops have separate preset and clear inputs.
• The 74AHC/AHCT74 dual positive-edge triggered, D-type
• flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and
reset (RD) inputs; also complementary Q and Q outputs.
• The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
 Study of IC 7474

• Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse.
• The D inputs must be stable one set-up time prior to the
• LOW-to-HIGH clock transition for predictable operation.
• The logic symbol of the two flip-flops with pin numbers is as shown
in figure.
 Study of IC 7474

PINNING
 Study of IC 7474

• FUNCTION TABLES
 Study of IC 7476

• This device contains two independent positive pulse triggered

J-K flip-flops with complementary outputs.
• It is called as Dual MSJK flip-flop IC.
• It is 16 - pin IC which consists of two master slave JK (MSJK) flip-flops.
• The two flip-flops have separate clear and preset inputs.
• While the clock is LOW the slave is isolated from the master. On the
positive transition of the clock, the data from the J and K inputs is
transferred to the master.
• While the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave.
 Study of IC 7476

• The logic state of J and K inputs must not be allowed to change while the
clock is HIGH.
• The data is transferred to the outputs on the falling edge of the clock pulse.
A LOW logic level on the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
• The logic symbol of two flip-flops with pin numbers is as shown in next
figure.
 Study of IC 7476

• Pin Diagram:
 Study of IC 7476

• Function Table
Inputs Outputs
PR CLR CL K J K Q Q#
L H X X X H L
H L X X X L H
L L X X X H H
(Invalid output)
H H same as
L L present state
H H L H L H
H H H L H L
H H H H Toggle
 Application of flip-flops
Counters
• A circuit that counts electrical pulses, applied as input to it is known
as counter.
• In practice, these circuits are used as event counters i.e. to count
number of events occurred. Electrical pulses are generated
corresponding to the occurrence of an event and these pulses are
given as input to the counters.
• A counter with n flip flops has 2n possible states. Therefore a three
bit up counter can count from 0 to 7 while a four bit down counter
can count from 15 down to 0.
• A n bit counter is built with n flip flops. Therefore a three bit
counter circuit has three flip flops.
 Counters

• Number of distinct states in the operation of counter is known as modulus

of that counter and that counter is called as mod 2n counter. In case of three
bit counter, the number of distinct states is 23= 8. Therefore modulus of
three bit counter is 8 and it is also called as modulo 23 that is modulo 8 or
simply mod 8 counter.
• Counters are broadly classified into two categories
1) asynchronous counters & 2) synchronous counters.
All the flip flops are clocked simultaneously for synchronous counters while
external clock input is applied to one flip flop and output of previous stage is
connected as clock input of next stage in case of asynchronous counters.
• Based on output sequence the counters are also classified into three
categaries-1) up counter 2) down counter and 3) up/down counter
 Counters

• Up counter- If the decimal equivalent of the counter output increases

with successive clock pulses, it is called as up counter. For example in
a three bit up counter output goes from 0 to 7.
• Down counter- If the decimal equivalent of the counter output
decreases with successive clock pulses, it is called as down counter.
For example in a four bit down counter output goes from 15 down to 0.
• Up/down counter- A counter which can count in any direction ie. up
or down, depending upon status of direction control input is called as
up/down counter.
 Counters

• In asynchronous counter the first flip-flop is clocked by the external clock

pulse & then each successive flip-flop is clocked by the Q or /Q’ output of
the previous flip-flop i.e. clock (pulses) applied ripple from stage to stage
(LSB to MSB) hence asynchronous counters are called as ripple
counters.
 Design of asynchronous counter

• Asynchronous counters are also known as ripple counters.

• In these counters all the flip flops are not clocked simultaneously.
• They are slower than synchronous counters.
• They are designed to generate straight binary sequences in up or down
directions.
• Their design is simpler as compared with synchronous counter. We shall
discuss the design of asynchronous counters in the following examples.
 Mod 8 Ripple Up Counter

• Truth Table:
Q2 Q1 Q0 State of
counter

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7
 Mod 8 Ripple Up Counter

Circuit Diagram:
 Mod 8 Ripple Up Counter
Waveforms:
 Mod 8 Ripple Down Counter

• Truth Table:
Q2 Q1 Q0 State of
counter

1 1 1 7

1 1 0 6

1 0 1 5

1 0 0 4

0 1 1 3

0 1 0 2

0 0 1 1

0 0 0 0
 Mod 8 Ripple Down Counter
Circuit Diagram:
 Mod 8 Ripple Down Counter
Waveforms:
4 Bit Up Down Counter
4 bit Controlled Asynchronous Up / Down counter :

• As name indicates an up/ down counter which can count both in upward &
downward direction.
• It is also called as forward/backward counter or bidirectional counter so a
control signal or a mode signal M is required to choose the direction of
counting.
• When M=1 Q0 is transmitted to clock of FF 1 and so on which results in
up counting & when M=0 Q0 is transmitted to clock of FF 1 and so on
which results in down counting.
Mod 5 Ripple Up Counter
BCD Ripple Up Counter
 Drawbacks of ripple counter

• The clock ripples through the circuit, like the ripple in water. Therefore
asynchronous counters are known as ripple counters.
• The asynchronous counters are slower than synchronous counters.
• Another drawback of asynchronous counters is that they can generate
straight binary sequences in up or down direction while synchronous
counters can be designed for any count sequence.
• Also we have to use JK or T flip flops only in the design of asynchronous
counters.
 Applications of Asynchronous Counters

• Counting device
• Digital clock
• Frequency divider circuits
 Counters

• Counters are broadly classified into two categories

1) asynchronous counters & 2) synchronous counters.
All the flip flops are clocked simultaneously for synchronous counters while
external clock input is applied to one flip flop and output of previous stage is
connected as clock input of next stage in case of asynchronous counters.
• Based on output sequence the counters are also classified into three
categaries-1) up counter 2) down counter and 3) up/down counter
 Design of synchronous counter

• For the design of synchronous counter, first find out the number of flip
flops required.
• Then prepare a table consisting of present state, next state and
determine the flip flop inputs which must be present to obtain the next
state using the excitation table of the flip flop.
• Prepare k-map for each flip flop input and obtain the simplified
expressions from which complete the circuit diagram.
 3 Bit Synchronous Counter

• State table for synchronous up counter:

Present state Next state Flip flop 3 Flip flop 2 flip flop 1

Q2 Q1 Q0 Q2 Q2 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 x 0 X 1 x

0 0 1 0 1 0 0 x 1 X x 1

0 1 0 0 1 1 0 x x 0 1 x

0 1 1 1 0 0 1 x x 1 x 1

1 0 0 1 0 1 x 0 0 X 1 X

1 0 1 1 1 0 x 0 1 X x 1

1 1 0 1 1 1 x 0 x 0 1 X

1 1 1 0 0 0 x 1 x 1 x 1
 3 Bit Synchronous Counter

K-Map
Q1Q0 00 01 11 10 Q1Q0 0 01 11 10 Q1Q0 0 01 11 10
0 0
Q2 Q2 Q2
0 0 0 1 0 0 X X X X 0 0 1 X X
1 X X X X 1 0 0 1 0 1 0 1 X X

J2= Q1Q0 K2= Q1Q0 J1= Q0

Q1Q0 0 01 11 10
Q1Q0 0 01 11 10
0 0
Q1Q0 0 01 11 10 Q2
Q2
0 0 X 1 1 X
Q2 0 1 X X 1
1 1 X X 1 1 X 1 1 X
0 X X 1 0
1 X X 1 0
K1= Q0 J0 = 1 K 0= 1
3 Bit Synchronous Counter
Logic Diagram:
 3 bit Synchronous down counter:
This is used to count from 7-0 i.e.(111-000).for this also 2 IC’s of
7
State table for synchronous down counter :
Present state Next state Flip flop 3 Flip flop 2 Flip flop 1

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 1 1 1 1 0 X 0 X 0 X 1

1 1 0 1 0 1 X 0 X 1 1 X

1 0 1 1 0 0 X 0 0 X X 1

1 0 0 0 1 1 X 1 1 X 1 X

0 1 1 0 1 0 0 X X 0 X 1

0 1 0 0 0 1 0 X X 1 1 X

0 0 1 0 0 0 0 X 0 X X 1

0 0 0 1 1 1 1 X 1 X 1 X
 3 bit Synchronous down counter:

• K-Map :

Q1Q0 0 01 11 10
Q1Q0 0 01 11 10 Q1Q0 0 01 11 10 0
0 Q2
Q2 0
Q2 0 1 0 X X
0 1 0 0 0 0 X X X X 1 1 0 X X
1 X X X X 1 1 0 0 0

J2= Q1Q0 K2=Q1Q0 J1= Q0

Q1Q0 0 01 11 10 Q1Q0 0 01 11 10
Q1Q0 0 01 11 10
0 0
0 Q2 Q2
Q2 0 X 1 1 X
0 X X 0 1 0 1 X X 1
1 1 X X 1 1 X 1 1 X
1 X X 0 1

• K1= Q0 J0= 1 K 0= 1
3 bit Synchronous down counter:

Logic Diagram :
 3 bit Controlled up / down synchronous counter:
• State Table for 3 bit Controlled Up-Down Synchronous
Counter.
Control Present State Next State Input for Flip-flop
input M
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 1 1 1 1 1 0 X 0 1 X 1 X
1 1 1 0 1 0 1 X 0 X 0 X 1
1 1 0 1 1 0 0 X 0 X 1 1 X
1 1 0 0 0 1 1 X 1 0 X X 1
1 0 1 1 0 1 0 0 X 1 X 1 X
1 0 1 0 0 0 1 0 X X 0 X 1
1 0 0 1 0 0 0 0 X X 1 1 X
1 0 0 0 1 1 1 1 X 1 X X 1
 3 bit Synchronous down counter:
• K MAPs: 00 01 11 10 0 0 1 1
Q1Q0 Q1Q0 Q1Q0 0 1 1 0
1
00 01 11
MQ2 0 MQ2 MQ2
00 1 X X 1 00 X 1 1 X 00 0 1 X X
01 1 X X 1 01 X 1 1 X 01 0 1 X X
11 1 X X 1 11 X 1 1 X 11 1 X 0 X
10 1 X X 1 10 X 1 1 X 10 1 X 0 X

J0 = 1 K0 = 1 J1 = M Q0 + M Q0
 3 bit Synchronous down counter:

Q1Q 0 1
Q1Q 0 1 0 00 11
1 0 Q1Q 0 1
0 00 11
1 0 0 00 11
MQ2 1 0
MQ2
00 0 0 1 0 MQ2
00 X X 1 0 01 X X X X 00 X X X X
01 X X 1 0 11 X X X X 01 0 0 1 0
11 X 0 X 1 10 1 0 0 0 11 1 0 0 0
10 X 0 X 1
10 X X X X
K1 = M Q0 + M Q0 J2 = M Q0 Q1 + M Q0 Q1 KC = M Q0 Q1 + M Q0 Q
3 bit Synchronous down counter:
Logic Diagram:
 Advantage of synchronous counter

• Clock impulses are given are same for all the flip flops so it is very easy to
design any circuit.
• Performance of synchronous is much better.
• Circuit is more liable and portable.
• Propagation delay time is reduced.
• Can operate at a much higher frequency than the asynchronous counters
 Applications of Synchronous Counters

• Digital clock
• Frequency divider circuits
• Frequency counters
• Used in analog to digital converters
 List the Synchronous Counter ICs

• IC 74160 : Decade Up Counter

• IC 74161 : 4 bit binary Up Counter
• IC 74162 : Decade Up Counter
• IC 74163 : 4 bit binary Up Counter
• IC 74168 : Decade Up/Down Counter
• IC 74169 : 4 bit Binary Up/Down Counter
• IC 74190 : Decade Up/Down Counter
• IC 74191 : 4 bit Binary Up/Down Counter
• IC 74192 : Decade Up/Down Counter
 Differences

Asynchronous Counter Synchronous Counter

• Output of the first flip flop • No connection between output of
drives the clock for the next first flip flop and clock input of
flip flop. the next flip flop.
• All the flip flops are not • All the flip flops are clocked
clocked simultaneously. simultaneously.
• Logic circuit is very simple. • Logic circuit is complex.
• These counters are slow • These counters are fast.
because of propagation
delay.
 Modulus n Counter

• IC 7490 is a TTL MSI (medium scale integration) decade counter. It

contains 4 master slave flip flops internally connected to provide MOD-2
i.e. divide by 2 and MOD-5 i.e. divide by 5 counters. MOD-2 and Mod-5
counters can be used independently or in cascading.
• It is a 4-bit ripple type decade counter. The device consists of 4-
master slave flip flops internally connected to provide a divide by two and
divide by 5 sections. Each section has a separate clock i/p to initiate state
changes of the counter on the high to low clock transition.
 Modulus n Counter

• Since the o/p from the divide by 2 section is not internally connected to
the succeeding stages. The device may be operated in various counting
modes. In a BCD counter the CP1 input must be externally connected to
QA o/p. The CP0 i/p receives the incoming count producing a BCD count
sequence. It is also provided with additional gating to provide a divide
by 2 counter and binary counter for which the count cycle length is
divide by 5. The device may be operated in various counting modes.
• There are 2 reset inputs R0(1) and R0(2) both of which need to be
connected to the ‘logic 1’for clearing all flip flops.
Basic internal Structure of IC 7490:
Pin diagram of IC 7490
Function tables of IC 7490
• Function Table of MOD-2 counter:
Input A Output Count
clock

0 0

1 1

• Function Table of MOD-5 counter:

Input B Output
clock Q QC QB
Cou
D
nt
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
 Design of MOD-10 counter using IC 7490:
• The QA o/p the first flip flop is connected to the input B which is clock i/p
of internal MOD-5 ripple counter. Due to cascading of Mod-2 and Mod-5
counters, the overall configuration the decade counters count from 0000 to
1001. After 1001 mod-5 resets to 0000 and next count after 1001 is 0000.
• When QA o/p is connected to B i/p, we have the Mod-2 counter
followed by Mod-5 counter. The count sequence obtained is shown in the
table. It may be noted that QA changes from 0 to 1 the state of Mod-5
counter doesn’t change, whereas when QA changes from 1 to 0 the Mod-5
counter goes to the next state.
Logic Diagram MOD-10 counter using IC 7490:
 Function table:
I/p clock Output

QD QC QB QA Count

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9
 Timing diagram of mod10:

CLK

QA

QB

QC

QD
 Design of Mod-7 Counter using IC 7490:

• Mod-7 counter counts through seven states from 0 to 6 counters and it

should reset as soon as the count becomes 7.
• The o/p of reset logic should be 1 corresponding to invalid states.
• The reset logic o/p should be applied to pin 2 and 3.
 Truth Table of Reset Logic:
QD QC QB QA Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
Logic Diagram Mod 7 Counter using IC 7490
 Function table:

I/p clock Output

QD QC QB QA Co
unt

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6
 Design of Mod-99 using IC 7490

• For Mod-99 two IC 7490’s will be required.

• Hence to implement a divide by 99 counter we have to use two decade
counters IC’s.
• A divide by 99 counter counts 99 states from 0 to 98 and the counter
should reset as soon as the count becomes 99.
• So in order to reset the counter of 99 connect the Q o/p which are equal to
1 in the count of 99 to an ‘And’ gate & then connect and o/p to the reset i/p
of both IC’s.
Logic Diagram Mod 99 Counter using IC 7490
Mod 100 Counter
 IC74191

• IC74191 is 4-bit binary synchronous, reversible, up down counter.

• It contains 4 master slave flip flops with internal gating and steering logic to
provide asynchronous reset and synchronous count up/down operations, its
asynchronous parallel capability permits the counter to be preset to any desire
number D0 to D3 are the parallel data inputs.
• Information present on the parallel data inputs D0 to D3 is loaded into the
counter and appears on the output when the load PL input is low.
 IC74191

• This operation overrides the counting function .Counting is inhabited by

the high level on the enable G input, when G input is low internal state
changes are initiated synchronously by the low to high transitions of the
clock inputs the up/down input signal determines the direction of input.
 IC74191
Function Table :
Operating Outputs
mode Inputs

PL U/D G CLK Dn

Parallel load L X X X L L

L X X X H H

Count up H L 0 ↑ X Count up

Count down H H 0 ↑ X Count down

Hold(No
H X H X X No change
change)
Pin Diagram :
Function table of IC 74191
 Pin details

• D0 to D3 input lines, PL parallel load

• G is Enable input – enabling the counting.
• Q0 to Q3 output lines.
• Down/up determines the direction of counting.
• Clk- clock input for counter.
• Terminal Count : Max(1111) min(0000). For these states signal goes high
for 1clock pulse.
• Ripple clock: Clock input for next higher state.
 Up counter- Truth Table

Clk Pulses QA QB QC QD

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 1 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1
 Logic Diagram

no connection
NC

Clock
D3 D2 D1 D0 PL
14 9 10 1 15 11
IC 74191
G RC NC
U/D MAX / MIN NC

UP/Down 5
13 RC
G4
7 6 2 3 12
Q3 Q2 Q1 Q0
TC Outputs

Connect the circuit as shown above.

Apply clock i/p to pin no.14
Connect U/D to GND.
Verify the output according to truth table.
 Down counter- Truth Table

CLK Pulses Q3 Q2 Q1 Q0

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 0 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
 Logic diagram of down counter

no connection
vcc vcc

U/D D3 D2 D1 D0
PL
Clk
Clock IC 74191
G
RC
NC
MAX / MIN NC
G

Q3 Q2 Q1 Q0
TC

Outputs
 Steps-

• Connect the circuit as shown above.

• Apply clock i/p to pin no.14
• Connect U/D to VCC.
• Verify the output according to truth table.
 Truncated up/down counter

• With the help of IC74191 we can implement truncated up/down counter by

using following logic –
• Connect data input line to particular count you want to load
• According to requirement make Truth table
• Draw the K-map
• Find out Boolean expression
• Draw the logic diagram and that is the combinational logic for your count and
apply the output of that circuit to PL
• According to requirement we get the UP and down counting
 Presetable up/down counter

Preset Count

CLOCK D3 D2 D1 D0

TC
U/D 74191
RC
G
PL
Up/down Q3 Q2 Q1 Q0 PL

Q3 Q2 Q1 Q0

Combinational Circuit
 Mod 10 counter

• Load Data on data lines D0 to D3 (0101).

• Counter will go through the states from 0101 ,0110,…1111 in up
counter and 1001 to 0000 in down counter.
• The logic circuit should be designed in such a way that only when all the
outputs are high, output of the reset circuit should be low and the counter
should jump to state 5. It should again start counting from 1001 to 0000.
• IC 74191 is 4 bit counter. Thus it counts 0000 to 1111 different 16 states.
• For MOD10 counter we require different 10 states so 6 steps must be
skipped from 16 states. We get MOD10 by presetting counter to value 6
.
 State Table: Up Counter
Counter state / Q3 Q2 Q1 Q0

Clock pulse

1 0 1 0 1

2 0 1 1 0

3 0 1 1 1

4 1 0 0 0

5 1 0 0 1

6 1 0 1 0

7 1 0 1 1
8 1 1 0 0
9 1 1 0 1
10 1 1 1 1
11 1 1 1 1
Mod 10 Counter
 Registers

• A register is a collection of flip-flops that act as an extension of a flip-

flop which can store multiple bits
• It has two basic functions: Data Storage and Data Movement
• A shift register provides the data movement function where it is
capable of shifting their binary contents in one or both directions
(shifting data to the left or right)
---- It “shifts” its output once every clock cycle
 Buffer Register
• Register, which is used to hold the inputs till they are used by the
next stage circuit
• Parallel out register can be used as buffer register.
Input Input Input

D Q D Q D Q

Q Q Q

Output Output Output

 A Basic Register

• Basic registers are easy to build. We can store multiple bits just by putting a
bunch of flip-flops together.
• A 4-bit register with its internal implementation is as shown below
– This register uses D flip-flops
– All the flip-flops share a common CLK and CLR signal

142
 Shift Registers

• A shift register "shifts" its output once every clock cycle.

• SI is an input that supplies a new bit to shift "into" the register

 Shift Registers
• For example, if on some positive clock edge we have:
• SI = 1

Q0-Q3 = 0110 then the next state will be:

Q0-Q3 = 1011
• The current Q3 (0 in this example) will be lost on the next cycle

Q0(t+1) = SI
Q1(t+1) = Q0(t)
Q2(t+1) = Q1(t)
Q3(t+1) = Q2(t)

Dept. of Information Digital Electronics & Logic Design 144

Technology
 Shift Registers
This register will result in the following output waveforms. Notice how the
data is “shifted” after each stage by one clock cycle and that the data at each
stage is available as well.
 Basic Shift Register Operation

• Some basic data movements are illustrated here:

Data in

Data in Data out Data out Data in

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
 Data Movement

• Block diagrams for shift registers with various input/output options:

 Serial Transfer vs. Parallel Transfer

• Serial transfer
– Information is transferred one bit at a time
– Shifts the bits out of the source register into the destination register
• Parallel transfer:
– All the bits of the register are transferred at the same time
• For example:
– Older printers use parallel data transfer
– USB devices use serial data transfer
 Parallel Data Transfer

Parallel data transfer moves data from one register to another at one time

Reg. A Reg. B

clock

When clock occurs, all bits of A are copied to B

 Serial Data Transfer

One application of shift registers is converting between "serial data" and

"parallel data"
Serial transfer moves data bits from A to B one bit per clock Rx and Tx have
single wire between the two
For ‘n’bit registers, it takes ‘n’clocks for data move

1 bit
signal
Reg. A Reg. B

clock
Usual implementation is with a shift register
 Serial Data Transfer (Cont.)

• Typical serial transfer is a multi-step process

– Load transmit shift register with data to send
– Shift data bit by bit from transmit to receive shift register
– Transfer received data to other registers
• The transmit shift register must have parallel load
– This is known as parallel to serial shift register
• The receive shift register must have parallel outputs
– This is known as serial to parallel shift register
• Other control/timing signals usually needed
 Serial Data Transfer (Cont.)

Parallel
Transmit
Data
‘n’ bits
load 1 bit signal
(serial data)
L
S Reg. A (P to S) Reg. B (S to P)

‘n’ bits
clock
Parallel
Receive
Data