SEMESTER 1 2024/2025
ASSIGNMENT 2:
Design and Application of a Decimal Counter in Digital Systems
COURSE:
Digital Circuit (EEE3821)
PROGRAMME:
Bachelor of Electrical and Electronics Engineering with Honours
LECTURER:
Prof. Ir. Ts. Dr. Suhaidie bin Shafie
STUDENT’S NAME MATRICS NO
MUHAMMAD RIFHAN HAKIMIE BIN 225361
ROSLI
TANVIR BIN ABDULLAH 226130
DANIEAL HAQEEM BIN HASHIMI 222472
SUBMISSION DATE: 24th January 2024, Thursday
TABLE OF CONTENTS
Introduction to Decimal Counters: ...................................................................................................3
Structure and Functionality ..........................................................................................................3
Modulus and Reinitialization ........................................................................................................3
Schematic Design: ...........................................................................................................................4
Simulation Results: ..........................................................................................................................6
Conclusion: ......................................................................................................................................8
Introduction to Decimal Counters:
Decimal counters are a category of digital counters employed in digital logic circuits to
enumerate in decimal format (base-10). In contrast to binary counters that operate in binary
(base-2), decimal counters progress through ten unique states, ranging from 0 to 9, before
reverting to 0. These counters are frequently utilized in applications necessitating decimal-
based counting, including clocks, frequency counters, and digital meters.
Structure and Functionality
Decimal counters are generally constructed using flip-flops, which are essential components in
sequential logic circuits. A flip-flop is a bistable circuit that can retain a single bit of information.
Decimal counters can be constructed to count sequentially from 0 to 9 by interconnecting
numerous flip-flops in a designated arrangement.
There exist two primary categories of decimal counters:
Asynchronous (Ripple) Decimal Counter: In this configuration, the output of one flip-flop
functions as the clock input for the subsequent flip-flop. The cascading effect induces a delay in
the transmission of the clock signal throughout the circuit, potentially constraining the counter's
speed.
Synchronous Decimal Counter: In a synchronous counter, all flip-flops are activated
concurrently by a shared clock signal. This eradicates the ripple effect observed in
asynchronous counters, rendering synchronous counters more expedient and dependable.
Modulus and Reinitialization
A decimal counter, referred to as a Mod-10 counter, possesses a modulus of 10, indicating it
completes a full cycle after 10 states. Upon reaching a count of 9, the counter resets to 0. The
reset can be accomplished by supplementary combinational logic that observes the JK flip-flop
outputs and produces a reset signal upon the counter attaining the specified state.
Schematic Design:
The design of the decimal counter will be using Synchronous Decimal Counter design where all
flip-flop will be activated by a singular clock signal, and it is an application for which to be used
as a a stopwatch that counts from 0 to 9.
The counter is made using JK flip-flops, which are set up to form a 4-bit counter that counts
from 0 to 9 in binary.
The diagram contains 4 JK flip-flops connected in a sequence. Each flip-flop will represent a
single bit of the binary count (from 0000 to 1001, which is 0 to 9 in decimal).
The J and K inputs of the flip-flops are connected in a specific way to ensure the proper
counting behavior, with each flip-flop being triggered by a clock signal.
The logic gates ensure that the counting is synchronized, meaning all flip-flops change their
state at the same time based on the clock pulse.
Figure 1.0 Synchronous 0-9 JK Decimal Counter designed in Logisim
Figure 2.0 Decoder circuit for translating binary to 7 segments display designed in
Logisim
Figure 3.0 Full circuit of Synchronous 0-9 JK Decimal Counter
Simulation Results:
Figure 4.0 Timing Diagram of Synchronous Decade Counter
The timing diagram of the synchronous 0-9 JK decimal counter shows how the counter
progresses through its counting sequence. It consists of four JK flip-flops, each representing
one bit of a 4-bit binary number. The clock signal is responsible for triggering the flip-flops to
change their state, and each rising edge of the clock pulse causes the flip-flops to toggle
according to their input conditions.
At the start of the diagram (Cycle 1), all flip-flops are in the 0 state, representing the binary value
0000, which corresponds to 0 in decimal. As the clock pulse moves to the next cycle (Cycle 2),
the first flip-flop (Q0) toggles from 0 to 1, resulting in the state 0001, representing the decimal
number 1. This process continues with each clock pulse triggering the flip-flops to toggle in a
controlled manner. For example, in Cycle 3, Q0 toggles back to 0, while Q1 toggles to 1,
resulting in the binary state 0010, which represents 2 in decimal. This toggling process
continues sequentially, with the state of the counter advancing from 0 through 9.
By Cycle 9, the state is 1001, which represents 9 in decimal. At this point, the counter resets
due to the design of the system, where once the counter reaches the binary representation for 9
(1001), it resets to 0000. This reset occurs after the 10th clock pulse, at which point the counter
starts from 0 again. This behavior allows the counter to continuously cycle from 0 to 9, resetting
after reaching the decimal value of 9 and restarting the sequence.
Clock Pulse Q3 Q2 Q1 Q0 Binary Decimal
1 0 0 0 0 0000 0
2 0 0 0 1 0001 1
3 0 0 1 0 0010 2
4 0 0 1 1 0011 3
5 0 1 0 0 0100 4
6 0 1 0 1 0101 5
7 0 1 1 0 0110 6
8 0 1 1 1 0111 7
9 1 0 0 0 1000 8
10 1 0 0 1 1001 9
11 0 0 0 0 0000 0
Table 1.0 Count Sequence
Conclusion:
Analyzing the timing diagram of the synchronous 0-9 JK decimal counter has significantly
deepened my understanding of digital circuits and counting mechanisms. By examining how JK
flip-flops are used to build a counter, I’ve gained a better grasp of binary counting and the
process of converting between binary and decimal systems. This assignment also highlighted
the importance of synchronization in digital circuits, showing how all flip-flops update their states
simultaneously in response to the clock signal, which ensures that the entire system operates
smoothly and predictably.
One of the most important takeaways for me was the reset functionality—after the counter
reaches 9, it automatically resets to 0. This helped me see how counters in real-world
applications, like digital clocks or timers, maintain a continuous loop. Additionally, I learned the
significance of the clock pulse in triggering state changes and how flip-flops toggle based on the
inputs they receive.
Through this assignment, I also realized how such counters form the foundation of more
complex digital systems. By understanding how a simple counter works, I can build on that
knowledge to explore more advanced concepts in digital logic and electronics. This hands-on
experience has made the theoretical concepts more tangible, reinforcing my learning and
making me more confident in applying these principles in future studies or projects.
