1.What types of connections are common to all memory devices?

A. All memory devices have address, data, and control connections.

2. List the number of words found in each memory device for the following numbers
of
address connections:
(a) 8
(b) 11
(c) 12
(d) 13
(e) 20
A. (a) 256 (b) 2K (c) 4K (d) 8K (e) 1M
3. List the number of data items stored in each of the following memory devices and
the number of bits in each datum:
(a) 2K 4
(b) 1K l
(c) 4K 8
(d) 16K 1
(e) 64K 4
A. (a) 2048 four bit numbers
(b) 1024 one bit numbers
(c) 4096 eight bit numbers
(d) 16,384 one bit numbers
(e) 65,536 four bit numbers
4. What is the purpose of the or pin on a memory component?
A. Select the memory device
5. What is the purpose of the pin on a memory device?
A. It causes the memory device to read data from a location.
6. What is the purpose of the pin on a SRAM?
A. Cause a write to occur
7. How many bytes of storage do the following EPROM memory devices contain?
(a) 2708
(b) 2716
(c) 2732
(d) 2764
(e) 27512
A. (a) 1K
(b) 2K
(c) 4K
(d) 8K
(e) 128K
8. Why won’t a 450 ns EPROM work directly with a 5 MHz 8088?
A. The microprocessor allows 460 ns for memory at 5 MHz, but because there is a
small delay in the connections to the memory, it would be best not to use a 450 ns
memory device in such a system without one wait state.
9. What can be stated about the amount of time needed to erase and write a location
in a flash
memory device?
A. Flash memory requires an extended amount of time to accomplish an
erase and write.
10. SRAM is an acronym for what type of device?

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 A. Static random access memory
11. The 4016 memory has a pin, an pin, and a pin. What are these pins used for in
this RAM? A. The G input cause a read, the W
input causes a write, and the S input selects the chip.
12. How much memory access time is required by the slowest 4016?
A. 250 ns
13. DRAM is an acronym for what type of device?
A. Dynamic random access memory.
14. The 256M DIMM has 28 address inputs, yet it is a 256M DRAM. Explain how a 28-
bit
memory address is forced into 14 address inputs.
A. The address inputs to many DRAMs are multiplexed so one address input accepts
two different address
bits, reducing the number of pins required to address memory in a DRAM.
15. What are the purposes of the and inputs of a DRAM?
A. These inputs strobe the column and row addresses into a DRAM.
16. How much time is required to refresh the typical DRAM?
A. Generally the amount of time is equal to a read cycle and represents only a small
amount of time in a modern memory system.
17. Why are memory address decoders important?
A. Memory rarely fills the entire memory, which requires some form of
decoder to select the memory device for a specific range of memory
addresses.
18. Modify the NAND gate decoder of Figure 10–13 to select the memory for address
range
DF800H–DFFFFH.

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 A.

19. Modify the NAND gate decoder in Figure 10–13 to select the memory for address
range
40000H–407FFH.
A

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 20. When the G1 input is high and both and are low, what happens to the outputs of
the 74HCT138 3-to-8 line decoder?
A. One of the eight outputs becomes a logic zero as dictated by the address inputs.
21. Modify the circuit of Figure 10–15 to address memory range 70000H–7FFFFH.
G2A G2B
CAS RAS
GSW
WE
OE
CS CE

A.
22. Modify the circuit of Figure 10–15 to address memory range 40000H–4FFFFH.

A.
23. Describe the 74LS139 decoder.
A. The 74LS139 is a dual 2-to-4 line decoder
24. What is VHDL?
A. Verilog hardware description language
25. What are the five major keywords in VHDL for the five major logic functions (AND,
OR,

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 NAND, NOR, and invert)?
A. and or nand nor not
26. Equations are placed in what major block of a VHDL program?
A. The architecture block between begin and end
27. Modify the circuit of Figure 10–19 by rewriting the PLD program to address
memory at
locations A0000H–BFFFFH for the ROM.
A. begin
ROM <= A19 or (not A18) or A17 or MIO;
RAM <= A18 and A17 and (not MIO);
AX19 <= not A19;
end V1;
28. The and minimum mode control signals are replaced by what two control signals
in
the 8086 maximum mode?
A.

29. Modify the circuit of Figure 10–20 to select memory at location 60000H–77FFFH.
A.

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 30. Modify the circuit of Figure 10–20 to select eight 27256 32K 8 EPROMs at
memory locations 40000H–7FFFFH.

A.
31. Add another decoder to the circuit of Figure 10–21 so that an additional eight
62256 SRAMs
are added at locations C0000H–FFFFFH.
A.
32. The 74LS636 error-correction and detection circuit stores a check code with each
byte of
data. How many bits are stored for the check code?
A. 5
33. What is the purpose of the SEF pin on the 74LS636?
A. Single bit error flag
34. The 74LS636 will correct ________ bits that are in error.
A. 1
35. Outline the major difference between the buses of the 8086 and 8088
microprocessors. A. The main differences
are the data bus size and the I/O, memory control signal.

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 36. What is the purpose of the and A0 pins on the 8086 microprocessor?
A. BHE selects the upper memory bank and A0 selects
the lower memory bank.
37. What is the pin and what other pin has it replaced?
A. Bank low enable has replaced the A0 pin.
38. What two methods are used to select the memory in the 8086 microprocessor?
A. Separate decoders and separate write signals
39. If is a logic 0, then the ________ memory bank is selected.
A. Upper memory bank
40. If A0 is a logic 0, then the ________ memory bank is selected.
A. Lower memory bank
41. Why don’t separate bank read ( ) strobes need to be developed when interfacing
memory
to the 8086?
A. It does not matter if 16-bit or 8-bit are read because the microprocessor
just ignores any data bus bits that are not needed.
42. Modify the circuit of Figure 10–30 so that the RAM is located at memory range
30000H–4FFFFH.
A.
43. Develop a 16-bit-wide memory interface that contains SRAM memory at locations
200000H–21FFFFH for the 80386SX microprocessor.
A.

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 44. Develop a 32-bit-wide memory interface that contains EPROM memory at
locations
FFFF0000H–FFFFFFFFH.
A.

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 45. Develop a 64-bit-wide memory for the Pentium–Core2 that contains EPROM at
locations
FFF00000H–FFFFFFFFH and SRAM at locations 00000000H–003FFFFFH.
A.
46. On the Internet, search for the largest size EEPROM you can find. List its size and
manufacturer. A.
47. What is an -only cycle?
A. . A cycle that does not read data, it only refreshes a row of memory.
48. Can a DRAM refresh be done while other sections of the memory operate?
A. Yes, as long as a memory location on the DRAM is not accessed.
49. If a 1M 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed,
no more
than ________ of time must pass before another row is refreshed.
A. 15.625 µs
50. How wide is the data bus in the Intel Itanium?
A. 128 bits wide
51. Scour the Internet to find the largest DRAM currently available.
A.
52. Write a report on DDR memory. (Hint: Samsung makes them.)
A.
53. Write a report that details RAMBUS RAM. Try to determine why this technology
appears to
have fallen by the wayside.
A.

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