Course Code: B20EC3101

SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R 20

III [Link]. I Semester MODEL QUESTION PAPER
INTERNET OF THINGS
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
a). Explain the typical Embedded system architecture with
1. 1 2 7
relevant diagram?
b). Illustrate an application-specific Embedded system with
1 2 7
suitableexamples?
OR
2. a). Explain the characteristics of embedded systems 1 2 7
b). Discuss about Real time clock with respect to an Embedded
1 2 7
Hardware?

UNIT-II
a). Explain about serial communication devices and parallel device
3. 1 2 7
ports?.
b). Discuss the significance of Watchdog timer in an Embedded
1 2 7
System.
OR
a). What is a Device Driver? Explain different types of device
4. 2 2 7
drivers and use of them
b). Explain about memory organization in Embedded system 2 2 7

UNIT-III
a). Draw and explain about Physical Design & Logical Design of
5. 1 2 7
IoT
b). Define IoT and mention different Characteristics of IoT 1 2 7
OR
6. a). Explain in details about IoT protocols 1 2 7
b). Differences and Similarities between M2M and IoT. 1 2 7

UNIT-IV
a). Name and explain in detail about any two communication
7. concepts 3 2 7

Page 1 of 23
 b). Explain about the following a) Ultrasonic Sensor b) IR Sensor c)
3 2 7
Temperature & Humidity
OR
Explain the Basic building blocks of an IoT Device & relate it
8. 3 3 14
with exemplary device.

UNIT-V
a). Explain in detail about Web Application Messaging
9. 4 3 7
Protocol (WAMP).
b). Demonstrate the role of Cloud based communication & Data
4 3 7
Analytics In IoT
OR
10. Analyze IoT Design Methodology with a use case. 4 4 14
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 2 of 23
 Course Code: B20EC3102
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R 20
III [Link]. I Semester MODEL QUESTION PAPER
ANTENNAS & WAVE PROPAGATION
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
1. a). Derive expressions for the EM fields radiated by an λ/2 Dipole. 1 3 7
b). Compute the directivity of a λ/4 Monopole. 1 3 7
OR
2. a). Compute the radiation resistance of a half wave dipole. 1 3 7
b). Explain about different types of current distribution on linear
1 2 7
antennas.

UNIT-II
3. a). What are Broadside and End-fire arrays? Obtain expressions for
2 3 7
BWFN and HPBW in both cases.
b). A Broadside array has a BWFN of 40deg. Compute the BWFN in
2 4 7
degrees if the same array is excited in End-fire fashion.
OR
4. a). Show that in a uniform linear array, the first side lobe is down the
2 4 7
principal Maximum by 13.5dB.
b). Explain the technique of pattern multiplication with examples. 2 2 7

UNIT-III
5. a). With a neat diagram, explain the operating principles of Rhombic
3 2 7
antenna. List out the disadvantages of a Rhombic antenna.
b). Compute the optimum values of length, height and tilt angle of a
Rhombic antenna if the angle of elevation alpha at which the 3 4 7
EMenergy leaves the antenna is 30deg.
OR
6. a). Explain in detail about the various feed mechanisms of antennas with
3 2 7
Parabolic reflectors.
b). Derive an expression for the expression of the impedance of the Slot
3 3 7
antenna.

UNIT-IV

Page 3 of 23
 7. a). Explain in detail about the slotted line method of antenna input
impedance measurement. 4 2 7
b). Explain the method of measuring the radiation pattern of an
antenna. 4 2 7
OR
8. a). 4 2 7
Explain one method of measurement of antenna gain.
b).
Explain the method of measurement of polarization of an antenna. 4 2 7

UNIT-V
9. a).
Derive an expression for the refractive index of the Ionosphere. 5 3 7
b).
Explain ground wave propagation in detail. 5 2 7
OR
10. a). Derive an expression for the field strength of a Space wave.
5 3 7
b).
Explain the terms Critical frequency, MUF and Skip distance. 5 2 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 4 of 23
 Course Code: B20EC3103
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. I Semester MODEL QUESTION PAPER
DIGITAL COMMUNICATION
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
a). Explain about delta modulation (DM) systems and design an
1. Adaptive Delta Modulation system to eliminate the drawbacks 1 2 7
generated in the DM system.
b). Consider that the signal cos2𝑟tis quantized into 16 levels. The
sampling rate is 4Hz. Assume that the sampling signal consists of
pulses each having a unit height and duration dt. & the pulses occur
every t=k/4sec, -∞ < k < ∞. 1 3 7
a. Sketch the binary signal representing each sample voltage.
b. How many bits are required per sample?
OR
a). Explain about the operation of a PCM system. What is
2. 1 2 7
Companding?
b). With the help of an example explain about the operation of
1 3 7
synchronous TDM-PCM system(T1-Digital System)

UNIT-II
a). Explain how a binary signal can be transmitted and received by
3. 2 2 7
using a BPSK system?
b). With the help of an example, explain the method of generating a
2 2 7
phase continuous MSK signal.
OR
a). Explain the role of a QPSK transmitter and receiver in serial data
4. 2 2 7
transmission and reception
b). In a DPSK Receiver, the received bit sequence b(t) is
01101100 then i) Find reconstructed bit sequence d(t) ii) Due to
2 3 7
presence of noise b(t) is recovered as 01111100 then detect d(t)
and identify thebits which are wrongly detected. Use EX-OR logic.

UNIT-III

Page 5 of 23
 a). Explain about linear filtering and calculate noise power output of
5. 3 2 7
RC low pass filter, differentiator and an integrator
b). Explain about frequency domain representation of noise. Define
3 2 7
noise power spectral density.
OR
a). Explain some sources of noise and narrow band representation of
6. 3 2 7
noise.
b). What is the effect of filtering on power spectral density of noise
and obtain the relation between H(f) ,i/p noise psd Gni(f) & o/p 3 2 7
noise PSD Gno(f)

UNIT-IV
a). What is the function of a baseband signal receiver and derive its
7. 4 3 7
probability of error ?
b). By deriving expression for Pe for BPSK and BFSK systems,
4 3 7
compare the performance of these two data transmission systems.
OR
a). Derive the expressions for Probability of error Pe and transfer
8. 4 3 7
function H(f) for an optimum filter
b). A signal is either S1(t) = A Cos 2πfot or S2(t) = 0 for an interval
T=n/fo ,with n being an integer. Find the error probability Pe of 4 3 7
thematched filter.

UNIT-V
a). Derive the expressions for output SNR when the binary signal
9. 5 3 7
is transmitted using BPSK in a PCM system
b). Compare the noise performance of PCM and DM systems 5 2 7
OR
a). How a CDMA system uses DS Spread Spectrum to provide multiple
10. 5 3 7
access communication.
b). Explain the methods of generating PN sequence. 5 2 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 6 of 23
 Course Code: B20EC3104
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. I Semester MODEL QUESTION PAPER
DATA COMMUNICATIONS AND COMPUTER NETWORKS
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
Explain various signal encoding methods and write NRZ codes and
1. a). 1 2 7
RZ codes for the following data streams 01011010 and 11001011.
Discuss various types of MODEM’s and explain with block
b). 1 3 7
schematic diagram DPSK modulator and demodulator
OR
Explain various types of data multiplexers and write about
2. a). 1 2 7
Statistical Time Division Multiplexer.
Differentiate the three categories of Networks LAN, MAN and
b). 1 3 7
WAN.

UNIT-II
3. a). Explain the need for layered architecture. 2 3 7
Determine which of network topologies is the most cost effective
b). 2 2 7
for setting up a LAN. Explain the reasons.
OR
4. a). Compare connection oriented and connectionless service. 2 3 7
Compare the functions of Network layer and Data link layer of OSI
b). model in transferring data between source and destination separated 2 2 7
by multiple networks.

UNIT-III
The frame received by the receiver is 10111101100. Using the
5. a). generator polynomial G(x) = + 1, verify if the frame is correct or 3 3 7
damaged.
With a neat flow diagram explain the selective repeat ARQ
b). 3 2 7
protocol.
OR
Describe various CSMA protocols. Compare their throughput
6. a). 3 3 7
performance.
b). Describe the MAC sub layer frame format of IEEE standard 802.4. 3 2 7

Page 7 of 23
 UNIT-IV
Distinguish the characteristics of virtual circuit and Datagram
7. a). 4 2 7
subnet.
b). Differentiate the working of ethernet switch and router. 4 3 7
OR
Explain the operation of Leaky Bucket Algorithm. Determine its
8. a). 4 3 7
advantages over the Token Bucket Algorithm.
b). Explain about IPV4 Addressing Scheme. 4 2 7

UNIT-V
9. a). Explain about elements of Transport protocols. 5 2 7
Explain the operation of UDP with the help of its header format.
b). 5 2 7
List the applications.
OR
10. a). Describe the main function of DNS. 5 2 7
b). Explain about the World wide web. 5 2 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 8 of 23
 Course Code: B20EC3105
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. I Semester MODEL QUESTION PAPER
CONTROL SYSTEMS
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks: 70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
Differentiate open-loop and closed loop control systems with
1. a). 1 3 7
examples.
For the given mechanical system, obtain the transfer function,
Y1(s)/F(s) and draw its electrical analog based on f-i analogy.

b). 1 4 7

OR
Find the transfer function C/R for the following system by using block
diagram reduction technique

2. a). 1 3 7

Obtain the transfer function y6/y1 for the given SFG using Mason’s
gain rule.

b). 1 3 7

Page 9 of 23
 UNIT-II
Distinguish between type and order of a system. What are the various
3. a). 2 3 7
error constants and how they are related to the type of the system?
Derive the expression for unit-step response of a standard second-order
b). system which is under-damped. Also, describe the transient response 2 4 7
specifications
OR
Discuss the standard input signals used to test control systems. Which
4. a). 2 3 7
one is used mostly and why?
A unity feedback system is characterized by an open-loop transfer
function G(s) = K/S(S+10). Determine the value of gain K such that the
b). system has a damping ratio of 0.5. With this value of K, find the 2 4 7
settling time, percent overshoot and steady state error for a unit-ramp
input.

UNIT-III
Explain why all the poles of a closed loop system must lie in the left-
5. a). 3 3 7
half of the s-plane for the system to be stable.
Using R-H criterion, find the range of K for the closed loop system to
be stable. The open loop transfer function of the system is
b). 3 4 7

OR
Explain how ‘Relative stability’ of a system can be assessed using RH
6. a). 3 3 7
criterion?
Obtain the Root-locus for the system

b). with 3 4 7
What value of K makes the closed loop system marginally stable?

UNIT-IV
What are the frequency domain specifications? A second order system
7. a). step response shows 25% overshoot. What is its resonant peak in 4 3 7
frequency response?
Obtain the Bode plots for the system having OL transfer function

b). 4 3 7

Determine the Gain Margin and Phase Margin.

OR
The open loop transfer function of a unity feedback system is given by
8. a). 4 4 7
Sketch the polar plot.

Page 10 of 23
 Draw Nyquist diagram and determine the stability of a closed loop
control system with open-loop transfer function
b). 4 3 7

UNIT-V
Construct the SS model for the following transfer function.
9. a). 5 4 7

Obtain the transfer function model for the following system

b). 5 3 7

OR
Find the state transition matrix for the given system.

10. a). 5 3 7

Test the controllability and observability for the following SS model

b). 5 4 7

Page 11 of 23
 Course Code: B20EC3106
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. I Semester MODEL QUESTION PAPER
ELECTRONIC MEASUREMENTS AND INSTRUMENTATION
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
Discuss briefly the different types of static errors of a measuring
1. a). 1 2 7
instrument
List out different AC voltmeters and explain the working of any
b). 1 2 7
one voltmeter in detail.
OR
Explain the following terms in detail (i) Accuracy (ii) Resolution
2. a). 1 2 7
(iii) Precision (iv) Expected value
Explain the working of a true RMS voltmeter with the help of a
b). 1 2 7
suitable block diagram.

UNIT-II
What is Thermistor and explain it’s importance along with
3. a). 5 2 7
advantages of it
Explain the principle of operation of strain gauges with the help of
b). 5 3 7
neat diagrams.
OR
4. a). Draw the LVDT and explain it’s operation in detail. 5 2 7
What are the modes of operation of piezo electric crystals? Explain
b). 5 2 7
in detail.

UNIT-III
5. a). Draw the Block diagram of simple CRO and explain it’s working. 3 3 7
Draw the circuit diagram of Dual trace oscilloscope and explain it’s
b). 3 3 7
operation in detail.
OR
Explain the measurement procedure of Lissajous patterns with one
6. a). 3 3 7
example.
Explain the concept of Digital storage oscilloscope along with
b). 3 3 7
circuit diagram.

Page 12 of 23
 UNIT-IV
Explain the operation of Maxwell’s bridge and derive the condition
7. a). 4 2 7
for balance of a bridge.
Draw the circuit diagram of Schering’s bridge and explain the
b). 4 3 7
operation of it.
OR
Derive the equations of balance for an Anderson bridge? discuss the
8. a). 4 2 7
advantages of the bridge.
Draw the circuit of Wein bridge and derive the expression for
b). 4 3 7
bridge balance

UNIT-V
9. a). Discuss Square wave and Pulse generator with neat block diagrams. 2 2 7
b). Explain the working principle of a harmonic distortion analyzer. 2 3 7
OR
Illustrate the working of a function generator with a neat block
10. a). 2 3 7
diagram.
Draw the block diagram of random noise generator and explain
b). 2 2 7
with neat waveforms.
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 13 of 23
 Course Code: B20EC3107
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. I Semester MODEL QUESTION PAPER
DIGITAL SYSTEM DESIGN USING HDL
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
1. a). What are levels of Abstraction in VHDL? 1 2 7
b). Distinguish between signals and variables in VHDL. 1 2 7
OR
Explain about concurrent and sequential statements with suitable
2. a). 1 2 7
examples.
With the help of a block diagram, explain the program structure of
b). 1 2 7
VHDL.

UNIT-II
Realize 16:1 multiplexer with 4:1 multiplexer in VHDL
3. a). 1 3 7
programming.
Define Flip Flop ? Design any sequential circuit using VHDL
b). 1 3 7
programming.
OR
4. a). Design sequential 3-bit counter using VHDL programming. 1 4 7
b). Develop VHDL Code for Half Adder and Full Adder 1 4 7

UNIT-III
5. a). Explain verilog Data Types and operators. 2 2 7
Develop the verilog HDL source code and logic diagram for 1-bit
b). 2 4 7
full adder using dataflow style.
OR
6. a). Realize 4-bit full adder in Verilog HDL using structural modeling. 2 2 7
What are the primitive gates supported by Verilog HDL? Develop
b). 2 3 7
the Verilog HDL statements to instantiate all the primitive gates.

UNIT-IV
Design a negative edge-triggered D-flip flop (D_FF) with
7. a). 3 4 7
asynchronous clear, active high. Use behavioral statements only.

Page 14 of 23
 (Hint: Output q of D_FF must be declared as reg). Design a clock
with a period of 10 units and test the D_FF.
What are rise, fall and turn-off delays in verilog? How are they
b). 3 2 7
specified in verilog?
OR
With syntax explain conditional branching and loop statements
8. a). 3 2 7
available in Verilog HDL behavioural description.
b). Design 4-bit Shift Register using HDL Language 2 4 7

UNIT-V
9. a). Explain the state machine coding. 3 3 7
b). Describe BIST with the help of LFSR. 4 2 7
OR
Design a Modulo -8 counter using a sequential circuit approach
10. a). 3 4 7
using D-flipflop.
b). Explain scan- path technique in sequential circuit testing. 4 3 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 15 of 23
 Course Code: B20EC3201
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III B. Tech II Semester Regular Examinations
MICROPROCESSORS AND MICROCONTROLLERS
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
1 Determine the features and architecture of INTEL 8085 Microprocessor 1 2 14
OR
2 a). Explain the addressing modes of 8085 with examples 1 2 7
b). Indicate flag register of 8085 microprocessor 1 3 7

UNIT-II
3 Draw and explain the functional block diagram INTEL 8086 Microprocessor 2 2 14
OR
4 a). Illustrate the generation of a 20-bit physical address in 8086 with an example. 2 2 7
b). Draw the flag register of 8086 and explain the function of each flag in detail. 2 2 7

UNIT-III
a). Draw the programmable register array of 8086 and explain the function of
5 3 2 7
each Register
b). Write an 8086-assembly language program to find the largest 3 2 7
OR
6 a). Explain any five addressing modes of 8086 with suitable example 3 2 7
b). Write an assembly language program for 8086 to find if given number is
evenor odd 3 2 7

UNIT-IV
7 Outline the features and internal block diagram of 8051 microcontroller 4 3 14
OR
8 a). Compare Microprocessors & Microcontrollers 4 3 7
b). Outline the internal RAM Structure of 8051 Microcontroller 4 3 7

UNIT-V
9 a). Explain addressing modes of 8051 microcontroller with examples 5 2 7
b). Explain assembler directives of 8051 microcontroller 5 2 7

Page 16 of 23
 OR
10 a). Explain the stack memory operation using PUSH and POP instructions, 5 2 7
b). Explain with examples arithmetic instructions of 8051 microcontroller 5 2 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 17 of 23
 Course Code: B20EC3202
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R 20
III [Link]. II Semester MODEL QUESTION PAPER
DIGITAL SIGNAL PROCESSING
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
a). Find the Z-transform of the signal xn=2nun-3nu-n-1 and itsregion
1 1 3 7
of convergence
b). Realize the series & parallel canonical realizations of the following
digital transfer function 1 3 7
XZ=z2+2z+4z-8(z2-0.9z+0.14)
OR
a). Compute the response of the system yn=0.7yn-1-0.12yn-2+xn-
2 1+xn-2 to the input xn=u(n). Discuss the stability of theabove DT 1 3 7
system?
b). Find the inverse Z transform of Xz= z2z2-2rzcosθ+r2 1 3 7

UNIT-II
a). Compute the DFT of the following sequence using Radix–2DIT
3 FFT algorithm. Show the all intermediate stage results: 2 3 7
xn={0,1,2,0,2,1,0,2}
b). Find the DFT of the sequence x(n) = {3, 2, 5, 4}, Using this result,
2 3 7
find the DFT of {25, 20, 15, 10}. State the property of DFT used?
OR
a). Obtain linear convolution of the two sequences given below using
4 circular convolution 2 3 7
x1n=1,2, 3,1 ,x2n=2,3, 0,4, 2
b). Compute the inverse DFT of the given sequence
2 3 7
X(k) ={8, 0, -8+-4j, 0, 0, 0, -8+4j, 0} using DIF-FFT algorithm

UNIT-III
5 a). Compare Chebyshev and Butterworth analog filters ? 3 2 7
b). Design digital Butterworth lowpass IIR filter using BLT method.
The filter specifications are given by i) -3dB cutoff frequency at 3 3 7
0.5π rad, ii) at least 15dB attenuation at 0.75π rad
OR

Page 18 of 23
 a). Compare Impulse invariance and Bilinear transformation methodsof
6 3 2 7
IIR digital filter design
b). Convert the following analog filter with transfer function using
impulse invariance method 3 3 7
HaS=s+0.2s+0.2)2+25

UNIT-IV
a). Design a linear-phase low pass FIR digital filter to meet the
following specifications: (i) Pass band = 0 to 10 kHz (ii) Sampling
7 4 3 7
frequency = 100 kHz(iii) Filter order =10. Compute the impulse
response of the desired FIR digital filter using Hamming window
b). What is Gibb’s phenomenon? Discuss the selection criteria ofwindows
4 2 7
with respect to FIR filter design
OR
8 a). Show that FIR filters provide constant group delay and phase delay? 4 2 7
b). Design a linear-phase band pass FIR digital filter to meet the
following specifications:
(i) Pass band = 100Hz to 200Hz (ii) Sampling frequency = 1000Hz 4 3 7
(iii) No. of samples =11. Compute the impulse response of the desired
FIR digital filter using Rectangular and Hamming windows.

UNIT-V
a). Explain how Sub band coding of speech signals reduces the bit rate
9 5 2 7
.
b). Illustrate the operation of up-sampler, down-sampler, Interpolator
5 2 7
and Decimator in time and frequency domains with neat sketches
OR
10 a). Discuss the effects of finite word length registers. 5 2 7
b). Explain about DTMF signal detection 5 2 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 19 of 23
 Course Code: B20CE3203
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R 20
III [Link]. II Semester MODEL QUESTION PAPER
VLSI DESIGN
Electronics and Communication Engineering
Time: 3 Hrs. Max. Marks:70
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT-I
1. a). Explain the CMOS fabrication steps with neat diagrams. 1 2 8
Write a Brief note on Various aspects of MOS transistor threshold
b). 1 2 6
voltage.
OR
2. a). With neat diagrams explain the process of N-well CMOS Inverter. 1 3 8
b). Compare CMOS , BiCMOS and Bipolar technologies. 1 3 6

UNIT-II
Draw the stick diagrams and layouts for
(a)Y=(A+BC)
3. a). 2 2 8
(b)CMOS inverter
(c)2 Input NAND and NOR gates
b). Define Buried contact, Butting contact and Via contact. 2 2 6
OR
With a neat sketch, Explain 1.2µm Double Metal, Double Poly
4. a). 2 3 7
CMOS rules
b). Draw the layout diagram for OAI logic using CMOS. 2 2 7

UNIT-III
Write a note on the concept of Sheet Resistance applied to MOS
5. a). 3 2 7
transistors and Inverters with an example.
b). Explain various limitations of scaling. 3 3 7
OR
What are Scaling models and derive all scaling factors for device
6. a). 3 2 7
parameters.
b). Calculate total on resistance of CMOS inverter where ZPU/ZPD=8/1 3 2 7

UNIT-IV
Sketch a 3 input NAND and NOR gate using Ratioed and Pass
7. a). 3 4 7
transistor logic

Page 20 of 23
 b). Write a short note on Bi-stability principle. 3 2 7
OR
8. a). Explain Master-Slave (edge-triggered) S-R flip-flop 3 3 7
b). Give a brief explanation about Latches and registers. 3 2 7

UNIT-V
9. a). Explain the basic FPGA Architecture 4 3 7
b). Write a short note on Built-in self test (BIST). 4 2 7
OR
Write various steps to be followed for test mode in Scan Design
10. a). 4 2 7
Techniques?
b). Explain the Internal Architecture of Xilinx XC4000. 4 3 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

Page 21 of 23
 Course Code: B20HS3202
SAGI RAMA KRISHNAM RAJU ENGINEERING COLLEGE (A) R20
III [Link]. II Semester MODEL QUESTION PAPER
UNIVERSAL HUMAN VALUES-2 : UNDERSTANDING HARMONY
(Common to CIVIL, ECE, EEE)
Time: 3 Hrs. Max. Marks: 70 M
Answer ONE Question from EACH UNIT
All questions carry equal marks
Assume suitable data if necessary
CO KL M
UNIT - I
1. a). Discuss natural acceptance 1 2 7
b). Differentiate prosperity and deprivation 1 2 7
OR
2. a). Write a note on physical facilities. 1 2 7
b). Deliberate the right understanding in perspective to self exploration. 1 2 7

UNIT – II
3. a). Illustrate coexistence of "I" and "Body ". 1 2 7
b). Explain doer, seer and enjoyer. 1 2 7
OR
4. a). Discuss Characteristic activities of Harmony with "I". 1 2 7
b). Explain Sanyam and Health. 1 2 7

UNIT – III
5. a). Write a note on human-human relationship as regarding harmony. 2 2 7
b). Differentiate intention and competence. 2 2 7
OR
6. a). Discuss salient values in relationship. 3 2 7
b). Illustrate universal Harmonious Society - an Undivided society. 3 2 7

UNIT – IV
7. Discuss orders of life in nature and its significance self-regulation of 4 2 14
individual
OR
8. Illustrate existence of human being as coexistence with universe in 4 2 14
perspective of space

UNIT – V
9. Discuss importance of professional competence for augmenting 5 3 14
universal human order.

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 OR
10. a). Case study of typical holistic technologies. 5 3 7
b). Role of engineer in promoting harmony in society 5 3 7
CO-COURSE OUTCOME KL-KNOWLEDGE LEVEL M-MARKS

NOTE : Questions can be given as A,B splits or as a single Question for 14 marks

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