metrically located with respect to VCO free running frequency f, (R/2) KA 3.28 PLL lock-in range and capture range a jgnal outside the capture range, but once captured, if will hold s beyond the lock-in range. ple : 3.2 APLL base five running frequency of 300 KHz and the bandwidth of the low pass filter as 30 He. Check whether the loop acquires lock for an input signal of 320 KHz. ‘The sum frequency of the phase detector output = (300+320) KHz. = 620 KHz ‘The difference frequency = (320-300) KHz = 20 KHz. Given bandiwaith of low pass fikteris 30 KHz, which is greater than the difference frequency of20 KHz, the PLL can acquire lock. 3.14. PLL APPLICATIONS The IC565 PLL is used fo- applications such as () Frequency Multiplication’ Division, (ii) AM Detection © scanned with OKEN ScannerLinear Integrated Circuits (iii) PM Detection (iv) FSK modulation/Demodulation (v) Frequency synthesizing 3.14.1 Frequency multiplication / division. Phase — >| LPF [—> Amplifier comparator} {> Output {,=Nis 3.29 Frequency multiplication using PLL divide by N network is inserted between the VCO output and phase comparator input. In the locked state, the VCO output frequency f, is given by f, = NfB. The multiplication factor can be obtained by selecting a proper scaling factor N of the counter. This circuit ean also be used for frequency division, Since the VCO output (a square wave) 's rich in| armonics itis possible to lock the m th harmonic of the VCO output with the input signal f. The output, for VCO is = m 3.14.2 Frequency Translation “schematic for shifting the frequency of an oscillator bya small factor is shown in Fig.3.30 Hcan be seen that a mixer and a LPP are connected ext The signal of which has to be shi input’s to the mixer. The output of the mis the output of LPF contains only the dit remely to PLL. ted and the output freq 'Xer contains the sui fer weney f,at the VCO are applied as im and diffe ree inl ge ference of f and /,, However © scanned with OKEN ScannerJog Multiplier andl PLL Anal yp Matter Phase r comparator F ottset reat veo —> olp f=1.+4, Fig3.30 Frequency translation The translation or offset frequency f,(f;< ro PLL FVC0 output Fig.3.31 PLL used as AM demodulator The PLL is locked to carrier frequency of the incoming AM signal. The output of VCO has the same frequency as the carrier, but unmodulated to fed to multiplier. Since VCO signal under the locked condition, the in phase by 90° before being fed to multiplier. This makes both the signals applied to the multiplier in same phase. The output of the rence signals, the demodulated output is obtained after y the LPF. Since the PLL responds only o carrer frequencies a high degree of selectivity and immunity. © scanned with OKEN Scanner3.42 Linear Integrated Circuits 3.14.4 FSK Modulation / Demodulation odulation, in which the The frequency shift keying (FSK) is a type of frequency m ; : shifted between binary data or code is transmitted by means of a carrier frequency that : ing logic 0 and fe representing logic 1. two fined frequency values namely fi repres: | are called mark and space The frequencies corresponding to logic 0 and lo} respectively. The block diagram shown in Fig.3.32 shows a FSK demodulator using PLL. The PLL is designed to remain in lock, with the FSK signal for both the frequencies f and f,, Then the VCO control voltage fed to comparator is given by Ach (3.103) (3.104) and V2 The difference between the two control voltage level is (3.105) av, Lod The two inputs V,, and Vp are applied to comparator. One of the inputs passed through a second LPF-2. The filter is designed for a time constant which is longer than the FSK pulse durat’ n to obtain a de voltage This de voltage wili have a value midway between V, and Vw When the FSK signal V, is applied to the input, the loop gets locked to the input frequency and tracks it inbetween the two frequency is f, and f,. The corresponding de shift at the output i made logic compatible by adjusting the saturation voltages of the voltage comparator. LPF: = Data output Vv, Ve Fsk nese prt A cial fetector Comparator | co LPF - Low Pass Filter Fig.3.32 (a) FSK demodulator using PLL @ scanned with OKEN ScannerAnalog id PLL 3.43 3.14.5 FM detection If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of the input signal. The filtered error voltage which controls the VCO and maintain lock with the input signal s the demodulated FM output. The control vol tage of vCO isa linear function of the instanceous frequency deviation, Hence, the FM signal is demodulated, almost without any distortion. The VCO transter characteristics determine the linearity of the demodulated output. Since, VCO used in IC PLL is highly linear, it is possible to realize highly linear FM demodulators. 7 Phase |_,J towpass|_J nor H ‘ampli FMsignar [ steetor fiter a veo =r. { Vo Fig.3.33 PLL as a FM detector 3.15 FREQUENCY SYNTHESIZER AND CLOCK SYNCHRONIZATION - The PLL can be used as basis for frequency synthesizer that can produce a precise series of frequencies that are derived from a stable crystal controlled oscillator. Fig.3.34 shows the block diagram of frequency synthesizer. Itis similar to frequency multiplier circuit except that divided by M network is added at the input of phase lock loop. The frequency of the crystal-controlled oscillator is divided by an integer factor M by divider netrowk to produce a frequency f,,./M, where f.,, is the frequency of the crystal controlled oscillator. The VCO frequency fy. is similarly divided by factor N by divider network to give frequency equal to f,.,/N. When the PLL is locked in on the divided-down oscillator frequency, we will have folM = fyeo/N, $0 that fgg = (N/M) fcc Divided by M network. Phase Lowpass Error detector filter 7 Dwided by network | foc= (NIM) fo 34 Block diageam of frequency synthesizer @ scanned with OKEN ScannerUnear tntexratert €), Ly adjusting divider counts ty desied vation large mumber of freq can ty produced, all derived fom the crystal controled axel tater MASA Clock Synehronteation A phase-locked foop (PLL) is a feedback cirenit designed to allow one circuit boar to xymehronize the phave of its on board clock with an external Hming signal PLLcirenit, operate by comparing the phase of an external signal to the phase of a elock signal produceg by a voltage controtted crystal oscillator (VOXOD ronizing signals, aphase-tocked loop can track ay quency that is a multiple of the input fi These properties are used for computer clock synchronization, demodulation, and frequency Consequently, in addition to sy input Mrequeney, or it ean generate a f uency synthesis wet), low clock skew When the PLL is enabled, (the PEN bit in the POTL regi between PNTAL and CLKOUT is guaranteed if ME <5, CLKOU! clock are fully synchronized. and the internal device System clock synchronization using phinye-locked loop A digital phase-locked loop is employed. The phase-locked loop may include a counter ‘which is incremented by a local device system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal, The phase-locked loop may alternatively include « counter that reflects the level of data stored in receive and/or transmit FIFO buffers, ‘The loop output signal controls the frequency of the system clock oscillator, Zo10 Adjust 140 110 130, Loop 7 Countor| eine L(y: Loop Gawt>—»} DAC |_| voxo |__, 100) 100 Hes ? 150, 160 170 Fig. Ss © A wireless receiver which receives digital data from a remote transmitter vit # radio frequency communications link compr frames dof a plurality of da with a count input that is derive! the countet Which wireless receiver is comprised of:a count from a system clock signal generated within the wireless receiv © scanned with OKEN ScannerAnalog Multiplier and PLL, 3.45 so including a latch i a latch in, i generated duri Put that is derived from a fi i g luring each data frame: a frame synchronization signal e A loop filter with an input derived from the counter with ived from th output; « A loop gain block, wi » Which gai Fienes gain block receives an input derived from the loop « A frequency-tuneable osci ee ee neni which receives the output of the loop gain block eee oe vin signal, the frequency of the system clock signal ee aT loop gain block output; wherein the loop gain block eee 7 a Wifeenes between the output of the loop filter and a ¢ it . value,whereby the fr y' k sis oo ee er ae requency of the system clock signal 2 3 a — S a T T > Frame n Framen+1 i Framen+2 | Frame nt+3 Time Handset Rx FIFO Level Fig.3.36 PLL and Clock Generator ase Locked Loop (PLL) clock generator in its central internal clock frequency The DSP56300 core features Ph The processing module. The PLL allows the processor t derived from a low-frequency clock input, a feature that offers lower frequency clock input reduces the overall electromagnetic interferen system. The ability to oscillate at different frequencies reduces costs by eliminatin: toadd additional oscillators to 4 system. Figure 3.36, shows the two main blocks of the clock generator in the DSP56300 core: operate at a high two immediate benefits. ce generated by a .gthe need Phase Locked Loop (PLL) that performs: — Clock input division —~ Frequency . multiplication — Skew elimination eT @ scanned with OKEN ScannerLinear Integrated Cir, Low-power division © Clock Generator (CLKGEN) that performs Interna and external clock generation Taw Power] Pu Divider Out] | Fextal ME2 POF OF loiviae} By2 OF = 2 102" Fig.3.37 PLL Clock Generator Block Diagram PLL and Clock Signals The PLL and clock pin configuration for each DSP56300 family member is available in the device-specific technical data sheet. The following pins are dedicated to the PLL ang clock operation: + PCAP: Connects an off-chip capacitor to the PLL filter. One terminal of the capacitor connects to PCAP, the other connects to VCCP. The value of this capacitor depends on the PLL Multiplication Factor (MF). * — CLKOUT: Provides a 50 percent duty cycle output clock synchronized to the internal Processor clock when the PLL is enabled and locked. When the PLL is disabled, the output clock at CLKOUT is derived from EXTAL, and has half the frequency of, EXTAL. This pin is operational in all device processing states except when the PLL Control I(PCTL1) Register Clock Out Disable (COD) bit is set, and during the tap state, When the device is in the Wait state, the CLKOUT pin continues to provide signal. + PINIT: During assertion of hardware reset, the value of the PINIT input pin is writen into the PCTLI PLL Enable (PEN) bit. After hardware reset is deasserted, the PLL ignores the PINIT pin, and it can have a different function in the device * PLOCK: Originates from the Phase Detector, The device asserts PLOCK when the PLL is enabled and locked. When the device deasserts PLOCK output, the PLL cnabled but not locked. PLOCK is also asserted when the PLL is disabled, PLOCK’S a reliable indicator of the PLL lock state only after exiting the hardware reset stat: © scanned with OKEN Scanner