Lecture 2

Introduction (Part II)

VLSI Physical Design Fundamentals Course

Phil Hoang
Tresemi
ASIC Development Flow
(How a chip is built - simplified)
What does the chip do?
Market Research Marketing Requirement Document (MRD) How fast does it need to operate?
Specs

How much power will it consume?

How big will it be?
Chip Specification Product Requirement Document (PRD)
How much will it cost?
Front-End Design

Architectural Design Does the chip have all the required

Architectural Level functionalities?
Micro-architecture Design Is the design adequate for meeting
Register-Transfer
performance goals?
Level (RTL)
RTL Design

Does the chip meet all the required

Back-End Design

Logic Synthesis Gate Level performance specifications?

Circuit Design Transistor Level

Physical Design Physical Level Levels of Abstraction

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.2

IC Design Conceptual Flow

Specifications Verification Physical Design Fabrication / Packaging Testing

RTL Design Synthesis Signoff Devices

Front-End Design Back-End Design

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.3

IC Development Flow (Simplified)
Simulations & Signoff
Market Research Marketing Requirement Document (MRD) System Verification

Functional Simulations Simulation Dump Files ATPG

Chip Specification Product Requirement Document (PRD)
Test Benches
FPGA Prototyping Test Patterns
Constraints
Front-End Design

Architectural Design Behavioral Models Static Timing Analysis EMIR Analysis Logic Equivalence Check

Power Analysis Dynamic Timing Analysis Physical Verification

Micro-architecture Design Functional Models

RTL Design RTL Netlists Tape Out

Manufacturing & Testing

Back-End

Logic Synthesis Gate-Level Netist Silicon

Design

Mask Making Fabrication Packaging Validation

Physical Design Physical Layout Delivery

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.4

Digital Design System Example Design
Automation
Infrastructure IMPLEMENTATION
• Compute Infrastructure Infrastructure
• Design Environment EDA
• Project Directory Structure Tools
• Revision Control

Design
Re-use
(IP)

EDA
Flows
DESIGN

Image source: Skyworks

SIGN-OFF
© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.5
Digital Implementation Flow Examples

Initialize
Project/Workspace

Internal
Logic Synthesis, DFT Prepare Reference Data Memory Built-In-Self-Test

Place and Route Sign-Off

Post-Synthesis Analysis

Design Image source: Skyworks

© Tresemi 2024
Automation VLSI Physical Design Engineering Fundamentals p.6
Place and Route (P&R) Flow
• Read and check Import DB • Inputs are valid
Gate Level
Import quality of inputs • Constraints are complete
Netlist
• Design is routable
• Define Boundaries • IR drop is below limits
Cell Abstracts • Set up placement • Timing closure is feasible
areas for different
Floorplanning Floorplan DB
types of components
Timing • Create the Power • Design is routable
Constraints Distribution Structures • No timing violations
• Power consumption is minimized
Physical
Constraints
Placement • Place all components Placement DB • Clock trees are optimized
for timing and power
Inputs
Clock Tree Synthesis • Build the clock trees CTS DB • Design is free of design
rule errors
Routing • Route all signals Route DB • No timing violations
• IR drop is below limits
• Power is within budget
Gate Level Netlist • Design is reliable
• Design is manufacturable
Layout
Export • Write outputs
QOR Reports • Design is ready for
FAB
verification and then
Steps Outputs on to Manufacturing

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.7

 Primary Goals of Physical Design

The primary goals of physical design encompass optimizing integrated circuits for superior
performance, minimizing power consumption, and efficient chip area utilization.

▪ Reliability and
▪ PPA Optimization: finding the right Robustness:
balance among these 3 factors to PPARMP − Ensure proper functionality
achieve an optimal design for a under all operating
specific application or use case: More Powerful conditions and
− Performance environmental factors.
• Enhance overall processing
capabilities. Longer Battery Life
▪ Manufacturability:
• Meeting timing constraints. − Optimize the design for
manufacturability to improve
− Power Better Thermal the yield of the
• Minimize power consumption for manufacturing process.
extended battery life, reduced energy
costs, and effective thermal Less Expensive
▪ Productivity:
management. − Achieve rapid closure of all
− Area design goals, contributing to
• Minimize chip area to enhance cost the successful delivery of
efficiency in mass production. high-quality ICs.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.8

Performance

PPARMP

Performance
Understanding Delays

Power

Area
Does the design meet all the Understanding Timing
timing constraints? Constraints
Reliability
Robustness

Manufactura
bility

Productivity

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.9

Understanding Delays
Performance

Delays

Timing
Delays
Constraints

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Gate Delay

Performance
a.k.a.
Cell Delay
Delays

Timing
Constraints

More on this
later

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.11

Net Delay

a.k.a.
Wire Delay
Interconnect Delay

Performance

Delays

Timing
Constraints

More on this
later

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.12

Synchronous Design

Performance

Delays

Timing
Constraints

What is a register?

Timing
Constraints

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Static Timing Analysis (STA)

Performance

Delays

Timing
Constraints

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Timing Constraints

Performance

Delays

Timing
Constraints

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Clock Terminologies – Period, Duty Cycle, Edges

Delays
Clocks
Timing
Constraints
Period

Edges

Duty
Cycle

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Creating a Clock or Generated Clock
Performance

Delays

Timing
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.17

Clock Skews

Delays

Timing
Constraints
Skews

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.18

Clock Uncertainty – Clock Latency

Performance

Delays

Timing
Constraints

Uncertainty Latency

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Setup & Hold Time

Delays
Setup
Timing
Constraints
Time

Hold
Time

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.20

Max Delay / Min Delay

Delays

Timing
Constraints

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Setup (Max) Constraint

Delays

Timing
Constraints

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Hold (Min) Constraint

Delays

Timing
Constraints

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Setup/Hold Summary

Delays

Timing
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.24

I/O Constraints
Performance

Delays

Timing
Constraints

I/O

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.25

I/O Constraints Summary

Performance

Delays

Timing
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.26

Case Analysis / Design Rules

Performance

Delays

Timing
Constraints

Case

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.27

Multi-Cycle Paths

Performance
Timing
Delays
Exceptions
Timing
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.28

False Paths

Performance
Timing
Delays
Exceptions
Timing
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.29

Multi-Mode Multi-Corner (MMMC)

Delays
Design Modes &
Contraints Corners
Timing
Constraints

SDC

TCL

More on this
later

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.30

MMMC Examples

create_library_set -name ls_slow –timing [list libs/lib/sc_slow.lib libs/mem_slow.lib]

create_library_set -name ls_fast –timing [list libs/lib/sc_fast.lib libs/mem_fast.lib]

P&R create_constraint_mode -name cm_func -sdc_files [Link]

Inputs
create_constraint_mode -name cm_test -sdc_files [Link]
Design
Netlist
create_rc_corner -name rc_max –cap_table libs/captbl/worst/capTable
Cell
Abstracts
create_rc_corner -name rc_min –cap_table libs/captbl/best/capTable

Timing
Constraints
create_delay_corner -name dc_max –library_set ls_slow –rc_corner rc_max
create_delay_corner -name dc_min –library_set ls_fast –rc_corner rc_min
Physical
Constraints
create_analysis_view -name av_func_max –delay_corner dc_max –constraint_mode func
create_analysis_view -name av_test_min –delay_corner dc_min –constraint_mode test

set_analysis_view -setup [list av_func_max] -hold [list av_test_min]

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.31

Timing Derates

Examples:
P&R
▪ Add 3% to all max delays:
Inputs − set_timing_derate –delay_corner dc_max –cell_delay –late 1.03
Design
Netlist ▪ Subtract 3% to all min delays:
Cell
− set_timing_derate –delay_corner dc_min –cell_delay –early 0.97
Abstracts

Timing
More on this
Constraints later

Physical
Constraints
On-Chip Variation
OCV

Statistical Timing
Analysis

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.32

 Time to Timing Closure

The primary goals of physical design encompass optimizing integrated circuits for superior
performance, minimizing power consumption, and efficient chip area utilization.

▪ PPA Optimization: finding the right PPARMP ▪ Reliability and

balance among these 3 factors to Robustness:
achieve an optimal design for a − Ensure proper functionality
specific application or use case: More Powerful
under all operating
− Performance conditions and
• Enhance overall processing Longer Battery Life
environmental factors.
capabilities.
• Meeting timing constraints. ▪ Manufacturability:
− Power Better Thermal
− Optimize the design for
manufacturability to improve
• Minimize power consumption for the yield of the
extended battery life, reduced energy manufacturing process.
costs, and effective thermal Less Expensive
management. ▪ Productivity:
− Area − Achieve rapid closure of all
• Minimize chip area to enhance cost design goals, contributing to
efficiency in mass production. the successful delivery of
Time to Timing Closure! high-quality ICs.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.33

References

▪ CMOS VLSI Design – Weste-Harris ▪ asic back-end - [Link]

▪ Digital Integrated Circuits – Jan Rabaey ▪ System-on-Chip Design – Anand Raghunathan
▪ 2011 Lecture Notes - David Money Harris ▪ Physical Design Flow – Mohammad Kakoee
▪ Digital VLSI Design – Adam Teman ▪ Team VLSI Blog – “[Link]”
▪ Principles of VLSI Design – Jim Plusquellic ▪ Cadence Online Support Site and YouTube Videos
▪ Digital Integrated Circuits – YuZhuo Fu ▪ Reliability of segmented edge seal ring for RF devices
- J. Gambino, et al.
▪ VLSI Back-End Adventure, ASIC Blog – “SoC
Physical Design” ▪ A Reliable I/O Ring For A Reliable SoC – Abdelliah
Bakhali
▪ VLSI Physical Design For Fresher –
“[Link]” ▪ Apply Wire bonding PBGA or Flip Chip PBGA? -
Fiona Zhang
▪ VLSI Begin… Blog - “[Link]”
▪ Floorplan Strategies for Macro Dominating Blocks –
▪ SoC Physical Design – “physicaldesign- Team VLSI
[Link]”
▪ Floorplan Guidelines for Sub-Micron Technology
▪ VLSI Expert – “[Link]” Node for Networking Chips - Dhaval S. Shukla
▪ ASIC-System on Chip-VLSI Design – “asic- ▪ Internet search and many more…
[Link]”
▪ From Logic to Layout – Rob Rutenbar

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.34