SQ4850EY

[Link]
Vishay Siliconix
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
FEATURES
PRODUCT SUMMARY
• TrenchFET® power MOSFET
VDS (V) 60
RDS(on) (Ω) at VGS = 10 V 0.022 • 100 % Rg and UIS tested
RDS(on) (Ω) at VGS = 4.5 V 0.031 • AEC-Q101 qualified
ID (A) 12 • Material categorization:
Configuration Single for definitions of compliance please see
Package SO-8 [Link]/doc?99912

SO-8 Single D
D
D 5
D 6
D 7
8
G

4
S
3 G
2 S
1 S N-Channel MOSFET
S
Top View

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 60
V
Gate-Source Voltage VGS ± 20
TC = 25 °C 12
Continuous Drain Current ID
TC = 125 °C 6.9
Continuous Source Current (Diode Conduction) IS 6.2 A
Pulsed Drain Current a IDM 48
Single Pulse Avalanche Current IAS 23
L = 0.1 mH
Single Pulse Avalanche Energy EAS 26 mJ
TC = 25 °C 6.8
Maximum Power Dissipation a PD W
TC = 125 °C 2.2
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +175 °C

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL LIMIT UNIT
Junction-to-Ambient PCB Mount b RthJA 85
°C/W
Junction-to-Foot (Drain) RthJF 22
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. When mounted on 1" square PCB (FR4 material).

S15-1878-Rev. F, 17-Aug-15 1 Document Number: 68878

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 SQ4850EY
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Vishay Siliconix

SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 60 - -
V
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.5 2 2.5
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VGS = 0 V VDS = 60 V - - 1.0
Zero Gate Voltage Drain Current IDSS VGS = 0 V VDS = 60 V, TJ = 125 °C - - 50 μA
VGS = 0 V VDS = 60 V, TJ = 175 °C - - 150
On-State Drain Current a ID(on) VGS = 10 V VDS ≥ 5 V 30 - - A
VGS = 10 V ID = 6 A - 0.017 0.022
VGS = 10 V ID = 6 A, TJ = 125 °C - 0.029 0.037
Drain-Source On-State Resistance a RDS(on) Ω
VGS = 10 V ID = 6 A, TJ = 175 °C - 0.037 0.047
VGS = 4.5 V ID = 5 A - 0.025 0.031
Forward Transconductance b gfs VDS = 15 V, ID = 6 A - 21 - S
Dynamic b
Input Capacitance Ciss - 1000 1250
Output Capacitance Coss VGS = 0 V VDS = 25 V, f = 1 MHz - 185 235 pF
Reverse Transfer Capacitance Crss - 75 95
Total Gate Charge c Qg - 20 30
Gate-Source Charge c Qgs VGS = 10 V VDS = 30 V, ID = 6 A - 2.9 - nC
Gate-Drain Charge c Qgd - 4.4 -
Gate Resistance Rg f = 1 MHz 0.3 - 2.1 Ω
Turn-On Delay Time c td(on) - 7 11
Rise Time c tr VDD = 30 V, RL = 30 Ω - 9 14
ns
Turn-Off Delay Time c td(off) ID ≅ 1 A, VGEN = 10 V, Rg = 1 Ω - 23 35
Fall Time c tf - 9 14
Source-Drain Diode Ratings and Characteristics b

Pulsed Current a ISM - - 48 A

Forward Voltage VSD IF = 1.7 A, VGS = 0 - 0.8 1.2 V
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

S15-1878-Rev. F, 17-Aug-15 2 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 SQ4850EY
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
40 40
VGS = 10 V thru 5 V

32 VGS = 4 V 32
I D - Drain Current (A)

I D - Drain Current (A)

24 24

16 16
TC = 25 °C

8 8
VGS = 3 V TC = 125 °C

VGS = 2 V TC = -55 °C
0 0
0 2 4 6 8 10 0 1 2 3 4 5
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

50 0.10

TC = -55 °C
40 0.08
R DS(on) - On-Resistance (Ω)
g fs - Transconductance (S)

TC = 25 °C
30 0.06

20 0.04
TC = 125 °C
VGS = 4.5 V

10 0.02
VGS = 10 V

0 0.00
0 5 10 15 20 25 0 8 16 24 32 40
I D - Drain Current (A) ID - Drain Current (A)

Transconductance On-Resistance vs. Drain Current

1500 10

ID = 6 A
VGS - Gate-to-Source Voltage (V)

8
Ciss
C - Capacitance (pF)

1000 VDS = 30 V
6

4
500

Coss 2

Crss
0 0
0 10 20 30 40 50 60 0 5 10 15 20
VDS - Drain-to-Source Voltage (V) Qg - Total Gate Charge (nC)

Capacitance Gate Charge

S15-1878-Rev. F, 17-Aug-15 3 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 SQ4850EY
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
2.5 100

ID = 6 A
R DS(on) - On-Resistance (Normalized)

2.1 10
TJ = 150 °C

I S - Source Current (A)

VGS = 10 V

1.7 1

TJ = 25 °C
1.3 0.1

0.9 0.01

0.5 0.001
-50 -25 0 25 50 75 100 125 150 175 0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ - Junction Temperature (°C) VSD - Source-to-Drain Voltage (V)

On-Resistance vs. Junction Temperature Source Drain Diode Forward Voltage

0.15 0.6

0.3
0.12
R DS(on) - On-Resistance (Ω)

VGS(th) Variance (V)

0
0.09

-0.3
ID = 5 mA
0.06
-0.6
TJ = 125 °C
ID = 250 µA
0.03
-0.9

TJ = 25 °C
0.00 -1.2
0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 175
VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C)

On-Resistance vs. Gate-to-Source Voltage Threshold Voltage

75

ID = 1 mA
VDS - Drain-to-Source Voltage (V)

72

69

66

63

60
-50 -25 0 25 50 75 100 125 150 175
TJ - Junction Temperature (°C)

Drain Source Breakdown vs. Junction Temperature

S15-1878-Rev. F, 17-Aug-15 4 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 SQ4850EY
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)

IDM Limited
100

100 μs
Limited by RDS(on)*

ID - Drain Current (A)

10
1 ms

1 10 ms

100 ms
1s
0.1 10 s, DC
TC = 25 °C BVDSS Limited
Single Pulse
0.01
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified

Safe Operating Area

Duty Cycle = 0.5

Normalized Effective Transient
Thermal Impedance

0.2

0.1 Notes:
0.1
PDM
0.05
t1
t2
t1
0.02 1. Duty Cycle, D =
t2
2. Per Unit Base = R thJA = 85 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10 -4 10 -3 10 -2 10 -1 1 10 100 1000
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

S15-1878-Rev. F, 17-Aug-15 5 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 SQ4850EY
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)

Duty Cycle = 0.5

Normalized Effective Transient
Thermal Impedance

0.2

0.1
0.1
0.05

0.02

Single Pulse
0.01
10 -4 10 -3 10 -2 10 -1 1 10
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see [Link]/ppg?68878.

S15-1878-Rev. F, 17-Aug-15 6 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 SQ4850EY
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Vishay Siliconix

REVISION HISTORY a

REVISION DATE DESCRIPTION OF CHANGE

F 04-Aug-15 • Revised Rg minimum limit
Note
a. As of April 2014

S15-1878-Rev. F, 17-Aug-15 7 Document Number: 68878

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 Ordering Information
[Link]
Vishay Siliconix
SO-8
Ordering codes for the SQ rugged series power MOSFETs in the SO-8 package:

DATASHEET PART NUMBER OLD ORDERING CODE a NEW ORDERING CODE

SQ4182EY SQ4182EY-T1-GE3 SQ4182EY-T1_GE3
SQ4184EY SQ4184EY-T1-GE3 SQ4184EY-T1_GE3
SQ4282EY SQ4282EY-T1-GE3 SQ4282EY-T1_GE3
SQ4284EY SQ4284EY-T1-GE3 SQ4284EY-T1_GE3
SQ4401EY SQ4401EY-T1-GE3 SQ4401EY-T1_GE3
SQ4410EY SQ4410EY-T1-GE3 SQ4410EY-T1_GE3
SQ4425EY SQ4425EY-T1-GE3 SQ4425EY-T1_GE3
SQ4431EY SQ4431EY-T1-GE3 SQ4431EY-T1_GE3
SQ4435EY SQ4435EY-T1-GE3 SQ4435EY-T1_GE3
SQ4470EY SQ4470EY-T1-GE3 SQ4470EY-T1_GE3
SQ4483BEEY SQ4483BEEY-T1-GE3 SQ4483BEEY-T1_GE3
SQ4483EY - SQ4483EY-T1_GE3
SQ4532AEY - SQ4532AEY-T1_GE3
SQ4840EY SQ4840EY-T1-GE3 SQ4840EY-T1_GE3
SQ4850EY SQ4850EY-T1-GE3 SQ4850EY-T1_GE3
SQ4917EY SQ4917EY-T1-GE3 SQ4917EY-T1_GE3
SQ4920EY SQ4920EY-T1-GE3 SQ4920EY-T1_GE3
SQ4937EY SQ4937EY-T1-GE3 SQ4937EY-T1_GE3
SQ4940AEY SQ4940AEY-T1-GE3 SQ4940AEY-T1_GE3
SQ4946AEY SQ4946AEY-T1-GE3 SQ4946AEY-T1_GE3
SQ4949EY SQ4949EY-T1-GE3 SQ4949EY-T1_GE3
SQ4961EY SQ4961EY-T1-GE3 SQ4961EY-T1_GE3
SQ9407EY SQ9407EY-T1-GE3 SQ9407EY-T1_GE3
SQ9945BEY SQ9945BEY-T1-GE3 SQ9945BEY-T1_GE3

Note
a. Old ordering code is obsolete and no longer valid for new orders

Revision: 25-Aug-15 1 Document Number: 66624

For technical questions, contact: automostechsupport@[Link]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT [Link]/doc?91000
 Package Information
Vishay Siliconix

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

8 7 6 5

E H

1 2 3 4

D h x 45
C
0.25 mm (Gage Plane)
A
All Leads

q 0.101 mm
e B A1 L
0.004"

MILLIMETERS INCHES
DIM Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q 0° 8° 0° 8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

Document Number: 71192 [Link]

11-Sep-06 1
 VISHAY SILICONIX

TrenchFET® Power MOSFETs Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050 0.088
been been modified to provide the heat transfer capabilities 1.27 2.25
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains 0.088
0.027 2.25
the same. 0.69

See Application Note 826, Recommended Minimum Pad 0.078 0.2

1.98 5.07
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, ([Link] for the Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power With Copper Spreading
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make The minimum recommended pad patterns for the
two connections: an electrical connection and a thermal
single-MOSFET SO-8 with copper spreading (Figure 1) and
connection, to draw heat away from the package.
dual-MOSFET SO-8 with copper spreading (Figure 2) show
In the case of the SO-8 package, the thermal connections the starting point for utilizing the board area available for the
are very simple. Pins 5, 6, 7, and 8 are the drain of the heat-spreading copper. To create this pattern, a plane of
MOSFET for a single MOSFET package and are connected copper overlies the drain pins. The copper plane connects
together. In a dual package, pins 5 and 6 are one drain, and the drain pins electrically, but more importantly provides
pins 7 and 8 are the other drain. For a small-signal device or planar copper to draw heat from the drain leads and start the
integrated circuit, typical connections would be made with process of spreading the heat so it can be dissipated into the
traces that are 0.020 inches wide. Since the drain pins serve
ambient air. These patterns use all the available area
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The underneath the body for this purpose.
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a Since surface-mounted packages are small, and reflow
large thermal impedance. Also, heat spreads in a circular soldering is the most common way in which these are
fashion from the heat source. In this case the drain pins are affixed to the PC board, “thermal” connections from the
the heat sources when looking at heat spread on the PC planar copper to the pads have not been used. Even if
board. additional planar copper area is used, there should be no
APPLICATION NOTE

problems in the soldering process. The actual solder

0.288
7.3
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
0.050
drain pins, the solder mask generation occurs automatically.
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
0.027
The absolute minimum power trace width must be
0.69 determined by the amount of current it has to carry. For
0.078 0.2
thermal reasons, this minimum width should be at least
1.98 5.07 0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
Figure 1. Single MOSFET SO-8 Pad
from the device.
Pattern With Copper Spreading

Document Number: 70740 [Link]

Revision: 18-Jun-07 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172
(4.369)
0.028
(0.711)
(6.248)

(3.861)
0.246

0.152
(1.194)
0.047

0.022 0.050
(0.559) (1.270)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

[Link] Document Number: 72606

22 Revision: 21-Jan-08
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12 1 Document Number: 91000