SQ4953EY

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Vishay Siliconix
Automotive Dual P-Channel 30 V (D-S) 175 °C MOSFET
FEATURES
PRODUCT SUMMARY
• TrenchFET® Power MOSFET
VDS (V) - 30
• AEC-Q101 Qualifiedc
RDS(on) () at VGS = - 10 V 0.045
• 100 % Rg and UIS Tested
RDS(on) () at VGS = - 4.5 V 0.085
• Material categorization:
ID (A) per leg - 6.6
For definitions of compliance please see
Configuration Dual www.vishay.com/doc?99912

SO-8 S1 S2

S1 1 8 D1

G1 2 7 D1 G1 G2
S2 3 6 D2

G2 4 5 D2

Top View D1 D2
P-Channel MOSFET P-Channel MOSFET

ORDERING INFORMATION
Package SO-8
Lead (Pb)-free and Halogen-free SQ4953EY-T1-GE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 30
V
Gate-Source Voltage VGS ± 20
TC = 25 °C - 6.6
Continuous Drain Current ID
TC = 125 °C - 3.8
Continuous Source Current (Diode Conduction) IS -3 A
Pulsed Drain Currenta IDM - 26
Single Pulse Avalanche Current IAS - 17
L = 0.1 mH
Single Pulse Avalanche Energy EAS 14 mJ
TC = 25 °C 3.3
Maximum Power Dissipationa PD W
TC = 125 °C 1.1
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 175 °C

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL LIMIT UNIT
Junction-to-Ambient PCB Mountb RthJA 110
°C/W
Junction-to-Foot (Drain) RthJF 45
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. When mounted on 1" square PCB (FR-4 material).
c. Parametric verification ongoing.

S12-1845-Rev. B, 30-Jul-12 1 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 30 - -
V
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 1.5 - 2.0 - 2.5
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VGS = 0 V VDS = - 30 V - - -1
Zero Gate Voltage Drain Current IDSS VGS = 0 V VDS = - 30 V, TJ = 125 °C - - - 50 μA
VGS = 0 V VDS = - 30 V, TJ = 175 °C - - - 150
On-State Drain Currenta ID(on) VGS = - 10 V VDS- 5 V - 20 - - A
VGS = - 10 V ID = - 4.9 A - 0.035 0.045
VGS = - 10 V ID = - 4.9 A, TJ = 125 °C - - 0.066
Drain-Source On-State Resistancea RDS(on) 
VGS = - 10 V ID = - 4.9 A, TJ = 175 °C - - 0.076
VGS = - 4.5 V ID = - 3.7 A - 0.065 0.085
Forward Transconductanceb gfs VDS = - 15 V, ID = - 4.9 A - 9 - S
Dynamicb
Input Capacitance Ciss - 557 670
Output Capacitance Coss VGS = 0 V VDS = - 25 V, f = 1 MHz - 126 190 pF
Reverse Transfer Capacitance Crss - 90 115
Total Gate Chargec Qg - 15 22
Gate-Source Chargec Qgs VGS = - 10 V VDS = - 15 V, ID = - 4.9 A - 2.1 nC
Gate-Drain Chargec Qgd - 3.5 -
Gate Resistance Rg f = 1 MHz 2.60 5.26 8.50 
Turn-On Delay Timec td(on) - 3 5
Rise Timec tr VDD = - 15 V, RL = 6.8  - 9 14
ns
Turn-Off Delay Timec td(off) ID  - 1 A, VGEN = - 10 V, Rg = 1  - 20 30
Fall Timec tf - 9 14
Source-Drain Diode Ratings and Characteristicsb
Pulsed Currenta ISM - - - 26 A
Forward Voltage VSD IF = - 2 A, VGS = 0 V - - 0.8 - 1.2 V
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.

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Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

S12-1845-Rev. B, 30-Jul-12 2 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SQ4953EY
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)

30 30
VGS = 10 V thru 6 V TC = 25 °C

24 VGS = 5 V 24
ID - Drain Current (A)

ID - Drain Current (A)

18 18

12 VGS = 4 V 12

6 6
TC = 125 °C
VGS = 3 V
TC = - 55 °C
0 0
0 2 4 6 8 10 0 2 4 6 8 10
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)
Output Characteristics Transfer Characteristics

10 0.15

8 0.12
RDS(on) - On-Resistance (Ω)
ID - Drain Current (A)

VGS = 4.5 V
6 0.09

4 TC = 25 °C 0.06

2 0.03
VGS = 10 V
TC = 125 °C TC = - 55 °C
0 0.00
0 1 2 3 4 5 0 6 12 18 24 30
VGS - Gate-to-Source Voltage (V) ID - Drain Current (A)
Transfer Characteristics On-Resistance vs. Drain Current

1000 10

800 8 ID = 4.9 A
VGS - Gate-to-Source Voltage (V)

VDS = 15 V
C - Capacitance (pF)

Ciss
600 6

400 4
Coss

200 2
Crss

0 0
0 5 10 15 20 25 30 0 3 6 9 12 15
VDS - Drain-to-Source Voltage (V) Qg - Total Gate Charge (nC)

Capacitance Gate Charge

S12-1845-Rev. B, 30-Jul-12 3 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SQ4953EY
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)

2.0 100

ID = 4.9 A
RDS(on) - On-Resistance (Normalized)

1.7 10
VGS = 10 V TJ = 150 °C

IS - Source Current (A)

1.4 1
VGS = 4.5 V

1.1 0.1
TJ = 25 °C

0.8 0.01

0.5 0.001
- 50 - 25 0 25 50 75 100 125 150 175 0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ - Junction Temperature (°C) VSD - Source-to-Drain Voltage (V)

On-Resistance vs. Junction Temperature Source Drain Diode Forward Voltage

0.25 1.0

0.20 0.7 ID = 250 μA

RDS(on) - On-Resistance (Ω)

VGS(th) Variance (V)

0.15 0.4

ID = 5 mA
0.10 0.1
TJ = 150 °C

0.05 - 0.2
TJ = 25 °C

0.00 - 0.5
0 2 4 6 8 10 - 50 - 25 0 25 50 75 100 125 150 175
VGS - Gate-to-Source Voltage (V) TJ - Temperature (°C)

On-Resistance vs. Gate-to-Source Voltage Threshold Voltage

- 30

ID = 1 mA
VDS - Drain-to-Source Voltage (V)

- 32

- 34

- 36

- 38

- 40
- 50 - 25 0 25 50 75 100 125 150 175
TJ - Junction Temperature (°C)

Drain Source Breakdown vs. Junction Temperature

S12-1845-Rev. B, 30-Jul-12 4 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SQ4953EY
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)

100
IDM Limited

10

ID - Drain Current (A)

100 μs

1 ms
1
Limited by RDS(on)* 10 ms
100 ms
1s
0.1 10 s, DC
TC = 25 °C BVDSS Limited
Single Pulse

0.01
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified

Safe Operating Area

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2
Notes:
0.1
0.1 PDM

0.05
t1
t2
t1
1. Duty Cycle, D =
0.02 t2
2. Per Unit Base = R thJA = 110 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10- 4 10- 3 10- 2 10- 1 1 10 100 600
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

S12-1845-Rev. B, 30-Jul-12 5 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SQ4953EY
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1
0.1
0.05

0.02

Single Pulse

0.01
10 -4 10 -3 10 -2 10 -1 1 10
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72169.

S12-1845-Rev. B, 30-Jul-12 6 Document Number: 72169

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
Vishay Siliconix

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

8 7 6 5

E H

1 2 3 4

D h x 45
C
0.25 mm (Gage Plane)
A
All Leads

q 0.101 mm
e B A1 L
0.004"

MILLIMETERS INCHES
DIM Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q 0° 8° 0° 8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

Document Number: 71192 www.vishay.com

11-Sep-06 1
 VISHAY SILICONIX

TrenchFET® Power MOSFETs Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050 0.088
been been modified to provide the heat transfer capabilities 1.27 2.25
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains 0.088
0.027 2.25
the same. 0.69

See Application Note 826, Recommended Minimum Pad 0.078 0.2

1.98 5.07
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power With Copper Spreading
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make The minimum recommended pad patterns for the
two connections: an electrical connection and a thermal
single-MOSFET SO-8 with copper spreading (Figure 1) and
connection, to draw heat away from the package.
dual-MOSFET SO-8 with copper spreading (Figure 2) show
In the case of the SO-8 package, the thermal connections the starting point for utilizing the board area available for the
are very simple. Pins 5, 6, 7, and 8 are the drain of the heat-spreading copper. To create this pattern, a plane of
MOSFET for a single MOSFET package and are connected copper overlies the drain pins. The copper plane connects
together. In a dual package, pins 5 and 6 are one drain, and the drain pins electrically, but more importantly provides
pins 7 and 8 are the other drain. For a small-signal device or planar copper to draw heat from the drain leads and start the
integrated circuit, typical connections would be made with process of spreading the heat so it can be dissipated into the
traces that are 0.020 inches wide. Since the drain pins serve
ambient air. These patterns use all the available area
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The underneath the body for this purpose.
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a Since surface-mounted packages are small, and reflow
large thermal impedance. Also, heat spreads in a circular soldering is the most common way in which these are
fashion from the heat source. In this case the drain pins are affixed to the PC board, “thermal” connections from the
the heat sources when looking at heat spread on the PC planar copper to the pads have not been used. Even if
board. additional planar copper area is used, there should be no
APPLICATION NOTE

problems in the soldering process. The actual solder

0.288
7.3
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
0.050
drain pins, the solder mask generation occurs automatically.
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
0.027
The absolute minimum power trace width must be
0.69 determined by the amount of current it has to carry. For
0.078 0.2
thermal reasons, this minimum width should be at least
1.98 5.07 0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
Figure 1. Single MOSFET SO-8 Pad
from the device.
Pattern With Copper Spreading

Document Number: 70740 www.vishay.com

Revision: 18-Jun-07 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172
(4.369)
0.028
(0.711)
(6.248)

(3.861)
0.246

0.152
(1.194)
0.047

0.022 0.050
(0.559) (1.270)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

www.vishay.com Document Number: 72606

22 Revision: 21-Jan-08
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12 1 Document Number: 91000