Microelectronics Reliability 133 (2022) 114526

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Double-node-upset aware SRAM bit-cell for aerospace applications☆

Govind Prasad *, Bipin Chandra Mandi , Maifuz Ali
Department of Electronics and Communication Engineering (ECE), IIIT Naya Raipur, Chhattisgarh, India

A R T I C L E I N F O A B S T R A C T

Keywords: In aerospace applications, the continuous scaling of CMOS technology makes SRAM cells more and more sus­
Aerospace applications ceptible to soft errors. To overcome this issue, a radiation-hardened-based (RHBD) 13T SRAM cell has been
Critical charge proposed in this paper. The proposed cell has several benefits over other standard RHBD cells. The proposed cell
Low power
can not only recover from SNUs induced at any of its sensitive nodes but also from DNUs induced at any of its
Soft errors
SRAM
sensitive node pairs. It has the lowest hold, total power cost, the highest critical charge, moderate area overhead,
Stability and better stability. To improve speed, the proposed cell uses a unique feedback path among its internal nodes.
Finally, the figure of merit (FOM), SNU probability of failure (POF) comparison of cells validate that the pro­
posed cell is a better choice for sub-nanometer aerospace applications.

1. Introduction particles [16]. Single or multiple nodes upset may have a significant
impact on the dependability of security applications, particularly in
Satellite communication used in military operations, broadcasting, extreme radiation environments like aerospace applications [17–19].
and disaster monitoring are present everywhere in the modern world Researchers had reported many RHBD SRAM cells in the last few years.
[1]. To reduce the maintenance and manufacturing costs, lightweight The standard RHBD DICE-12T SRAM cell had been proposed in [20],
satellites need to be built [2–4]. In the satellite control and processing uses the interlocked connection to protect the cell from soft errors of
unit, SRAM-based memory is used because of its superior packing den­ both polarities as shown in Fig. 1(a). However, DICE gives more hold
sity and logic performance [5,6]. power and area cost. Authors in [21] had proposed QUATRO-10T as
In space applications, the weak geomagnetic field gives high energy shown in Fig. 1(b), which can provide soft error tolerance at the ‘1’
particles, radiation, and temperature fluctuations [7]. If the energy storing node. However, the QUATRO-10T shows write failure [22]. To
particle touches any sensitive node of a circuit, it provides extra overcome failure issue, QUATRO-12T had been proposed in [22] as
electron-hole pairs. Due to this pairs, the accumulated charges at sen­ shown in Fig. 1(c). Further, a few more cells RHBD-12T and QUCCE-
sitive nodes generate a transient voltage pulse [8]. If the transient 12T, were presented in [23,24] to provide soft error recovery, as
voltage is more than the threshold voltage of MOS, then the stored value shown in Figs. 1(d) and (e), respectively. However, QUATRO-12T,
at a sensitive node may flip [9]. The scaling of technology decreases RHBD-12T, and QUCCE-12T provide significant power loss and less
node capacitance and supply voltage, lowering the Qc. This makes the Qc. The RHBD-13T was proposed in [25], as shown in Fig. 1(f), offers
SRAM cell more sensitive to radiation particles and causes soft errors better robustness among many standard RHBD cells, but its low writing
like single and double node upsets [10]. The soft errors are the major speed and write margin limit RHBD-13T applicability for many appli­
problems of the SRAM-based memory used for modern sub-nanometer cations. Another RHBD-14T cell, as shown in Fig. 1(g), had been pro­
technologies in radiation environments like in aerospace applications posed in [26], its read delay and read stability are low due to the use of
[11]. more PMOSs. The radiation-hardened speed and power-optimized
Over the years, layout-level [12], system-level [13], and circuit-level (RSP)-14T as shown in Fig. 1(h) had been presented in [27] and it
[14] based methods have been used to protect the circuit from soft er­ gives better write speed and less static power due to stacked PMOSs.
rors. Out of all the techniques, the circuit level method is the best way to However, the RSP-14T cell is observed ‘0’ to ‘1’ SNU sensitive at node
reduce soft errors [15]. The conventional 6T SRAM gives low Qc and its QB and provides poor read stability. Moreover, the RHBD-14T and RSP-
positive feedback on inverters, making it more sensitive to energy 14T use layout optimization techniques to eliminate the charge sharing

☆
This work was carried out at Research Lab, IIIT Naya Raipur, India
* Corresponding author.
E-mail addresses: govindp317@[Link] (G. Prasad), maifuzali@[Link] (M. Ali).

[Link]
Received 9 September 2021; Received in revised form 7 March 2022; Accepted 21 March 2022
0026-2714/© 2022 Elsevier Ltd. All rights reserved.
G. Prasad et al. Microelectronics Reliability 133 (2022) 114526

effect which gives more area overhead and power consumption. in Fig. 2. The proposed 13T cell consists of eight PMOSs and five NMOSs.
To address the above-discussed issue, a RHBD-13T SRAM cell has The access transistor P1 placed between the bit line (BL) and node “A” is
been proposed. This cell has been designed and verified using 5000 driven by a word line (WL). Similarly, P2 placed between BLB and node
Monte Carlo (MC) simulations. It has been designed using thirteen “B” is driven by WL. The PMOS access transistors (P1, P2) are used to
transistors (five NMOS and eight PMOS transistors). The primary improve reliability, but they can reduce the read access time. Hence, in
advantage of the proposed cell is that, due to its structural design, it is the proposed cell, the separate read access transistor N5 is used between
capable of self-recovery from DNUs. The proposed cell uses separate read bit line (RBL) and node “C” operated by read word line (RWL).
read and write circuits to improve the speed of operation. Overall, the The proposed cell uses low threshold voltage (Vth) operated an NMOS
proposed cell offers the following benefits:: transistor N1 between P3 and N3. Similarly, the low threshold voltage-
operated an NMOS transistor N2 is used between P4 and N4. The tran­
1) The proposed cell can self recover at all the sensitive nodes from all sistors P6, P8, N1, and N2 (N3, N4) in the proposed cell are taken as high
the possible SNUs of both polarities. It has the highest SNU critical (low) Vth MOSs. The use of low Vth transistors (N1, N2) in the proposed
charge among all considered cells. cell increases the voltage swing of the output. Simultaneously, the high
2) The proposed cell can self recover at all the sensitive node pairs from Vth NMOSs (N3, N4, P6, P8) reduce the leakage current, reduce power
all the possible DNUs of both polarities. loss, and improve stability. The junctions between PMOSs P5, P6, and P1
3) The proposed cell has better stability due to the lower body effect, (P7, P8, P2) in the proposed cell are denoted as node “A” (“B”). Simi­
feedback path, and transistors size selection. larly, the junctions between NMOSs N1, N3, N5 (N2, N4) in the proposed
4) The proposed cell dissipates the lowest hold and total power cost due cell are marked as node “C” (“D”). The nodes “A” and “B” are ‘1’ to ‘0’
to stacked structure and weak PMOS transistors in the pull-down
path.
5) The write and read speed are also improved compared to other cells
due to lower body effect, feedback path, and extra access transistors
(N5).

Further, Sec. 2 illustrates the schematic, complete operation,

robustness, and implementation of the proposed cell. Sec. 3 provides the
evaluations of the considered SRAM cells. Finally, Sec. 4 concludes the
paper.

2. Proposed SRAM bit-cell

The conventional popular RHBD SRAMs like DICE-12T, QUATRO.-

10T, QUATRO.-12T, RHBD-12T, QUCCE-12T, RHBD-13T, RHBD-14T,
and RSP-14T are shown in Fig. 1(a), (b), (c), (d), (e), (f), (g), and (h)
respectively. The schematic, operation and implementation of the pro­
posed cell are explained as follows:

2.1. Schematic of proposed cell

Fig. 2. Schematic of the 13T proposed SRAM cell.
The circuit diagram of the proposed RHBD-13T bit-cell is presented

Fig. 1. Reviewed RHBD SRAMs (a) DICE-12T [20], (b) QUAT.-10T [21], (c) QUAT.-12T [22], (d) RHBD-12T [23], (e) QUCCE-12T [24], (f) RHBD-13T [25], (g)
RHBD-14T [26] (h) RSP-14T [27].

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flip immune as nodes are surrounded by PMOSs. Similarly, nodes “C”

and “D” are ‘0’ to ‘1’ flip immune as NMOSs are surrounded them [28]-
[31].

2.2. Read, hold, and write capability analysis

1. Write operation: Let us assume the ‘0’ stored state (i.e., state ‘0’ at
node “A”). Now to write state ‘1’, the RWL, WL and BLB are fixed to
state ‘0’ whereas BL is fixed to state ‘1’, as presented in Fig. 3(a). This
state will switch ON the transistors P1, P2, P3, P6, P7, N1, N2, and
N4. At the same time, transistors P4, P5, P8, N3, and N5 will be in an
OFF state. As a result, node “A” (“B”) is pulled up (pulled down) to
state ‘1’ (‘0’) as delineated in Fig. 3(a). Similarly, the state ‘0’ write
operation is also performed. The responses of the proposed cell for
write ‘1’ and ‘0’ is shown in Fig. 4.
2. Hold operation: In the hold mode, the WL and RWL are set to state ‘1’
and ‘0’, respectively. Assume ‘0’ hold state for the proposed cell (“A”,
“D” and “B”, “C” are at state ‘0’ and ‘1’, respectively). Under this
condition, the transistors P3, P6, P7, N1, N2, and N4 (P1, P2, P4, P5,
P6, P8, N3, and N5) are switched ON (OFF), and the proposed cell
hold the stored value as delineated in Fig. 3(b). Similarly, the state ‘1’
hold operation is also performed. The simulated response of the
proposed cell for hold ‘0’ and ‘1’ is delineated in Fig. 4.
3. Read operation: To read ‘0’ from the proposed cell, let us assume ‘0’
stored state (node “A”, “D” and “B”, “C” are at state ‘0’ and ‘1’,
respectively). The RBL is precharged to state ‘1’ also RWL and WL are
fixed to state ‘1’. Under this condition, the transistors N5 (N3) are Fig. 4. Simulated response of the proposed cell.
switched ON (OFF). Hence, there will be no current flow through N5
and N3. As a result, the sense amplifier detects zero voltage differ­
the SRAM. The model is expressed by Eq. (1) [8], where Is is the peak
ence between RBL and reference voltage (VDD) and gives state ‘0’ at
current of the current pulse (415 μA for the proposed cell), t1 is the
the output. To read ‘1’ (node “A”, “D” and “B”, “C” are at state ‘1’ and
collection time constant of the junction (200ps), t2 is the ion track
‘0’, respectively) from the cell, the RBL, RWL, and WL are fixed to
establishing time constant (50ps) [8] [38]. In this model, the double
state ‘1’. This will switch ON the N5 and N3. Therefore, current flows
exponential current source (DECS) has to be added at any or multi-node
through read access transistor N5 due to voltage differences between
of the SRAM cell to check the soft error tolerance. The fault injection
node “C” and RBL. As a result, the difference voltage between RBL
circuit of a negative pulse, i.e., a DECS, is connected at the drain of
and reference voltage (VDD) is detected by the sense amplifier and
NMOS to mimic a ‘1’→‘0’ transient. Similarly, the fault injection circuit
gives ‘1’ at the output as delineated in Fig. 3(c). The simulated re­
of a positive pulse, i.e., DECS, is connected at the drain of PMOS to
sponses of the proposed cell for read ‘1’ and ‘0’ is shown in Fig. 4.
mimic a ‘0’→‘1’ transient. For multi-node fault injection simulation, the
DECS has been added at multiple circuit nodes to mimic the transient or
2.3. SNU and DNU self-recovery analysis charge sharing effect [28].
( ) ( )
When a high-energy particle touches any reverse-biased drain junc­ I t = Is × e− t/t1 − e− t/t2 (1)
tion of the MOS transistor, it produces a current spike due to charge
In the proposed cell, the storage node “A” (“C”) and “B” (“D”) are
movement towards the junction. Hence, the radiation instigated soft
surrounded only by PMOSs (NMOSs). Hence, the energy particle can
error can be occurred [8]. The critical charge (Qc) is a straightforward
cause only ‘0’ to ‘1’ flip (‘1’ to ‘0’) at “A” (“C”) and “B” (“D”). To
indicator of soft error. The Qc is the minimum charge required to
replicate a node upset, a double exponential current pulse is introduced
accumulate at the node to change its stored value. One of the popular
at a node of the SRAM. Assume the stored value in the proposed cell is ‘0’
models to calculate Qc is a double exponential current pulse (DECP) [8]
(“A”=“D”= 0, “B”=“C”=1). Nodes “A” and “B” are ‘1’ to ‘0’ flip immune.
[38]. The DECP model is employed to emulate the effect of radiation in

Fig. 3. (a) Write, (b) Hold, and (c) Read operation of the proposed cell.

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Similarly, nodes “C” and “D” are ‘0’ to ‘1’ flip immune. Hence, nodes “A” sensitive nodes (“A” =‘0’ and “C” =‘0’). Hence, by excluding the “B” and
and “C” are the two sensitive nodes in the proposed cell. The SNU re­ “D” immune nodes, the proposed cell has only “A” and “C” for DNU
covery of nodes “A” and “C” of the proposed cell are discussed in Case 1 analysis. As a consequence, the proposed cell only contains one sensitive
and Case 2. node pair (A-C). The DNU recovery of node pair A-C of the proposed cell
is discussed in Case 4.
1) Case 1 (A radiation particle strikes node “A”): When the energy par­
ticle strike on node “A” (state ‘0’), it produces a positive transient 4) Case 4 (A radiation particle strikes node pair “A-C”:) When the energy
pulse (‘0’ to ‘1’). As a result, the PMOSs P7 and P3 will be temporally particle strikes nodes “A” (‘0’) and “C” (‘1’) at the same time. Ac­
switched OFF. Now the unaffected node “D” (state ‘0’) will switch cording to physical phenomena, the only negative (positive) tran­
ON the P6, and node “A” is rolled back to its initial value (Vth of sient is possible due to the capacity effect when an energy particle
transistor P6). strikes the OFF NMOS (PMOS) transistor [28–31]. Hence node “C”
2) Case 2 (A radiation particle strikes node “X”/“Y”): If the energy par­ will be changed from ‘1’ to ‘0’, node “A” will be changed from ‘0’ to
ticle strikes node “X” (‘1’), it produces a negative transient pulse (‘1’ ‘1’, node “B” will be changed from ‘1’ to ‘1’, and node “D” from ‘0’ to
to ‘0’). This pulse will force node “C” to discharge to ‘0’. According to ‘0’. Hence, the N4, P7, and P3 will be switched OFF. However, the
physical phenomena, the only negative transient is possible due to unchanged node “D” (‘0’) will switch ON the P6, and node “A” will
the capacity effect when an energy particle strikes the OFF NMOS recover to the original value state ‘0’ (Vth of P6). Subsequently, state
transistor [29]. Hence node “C” will be changed from ‘1’ to ‘0’ and ‘0’ at node “A” will switch ON the P3, and node “C” will also be rolled
node “D” from ‘0’ to ‘0’. As a result, the PMOSs P6, P8, and N4 will be back to its original value (‘1’). To evaluate the DNU tolerance ca­
temporally switched ON and OFF, respectively. At the same time, pacity of the proposed cell, which has four nodes (“A”, “B”, “C”, “D”),
node “A” (state ‘0’) will switch ON the P3, and node “X” is rolled back six possible node pairs (“A-B”, “A-C”, “B-C”, “B-D”, “C-D”, “A-D,”) are
to the initial value (state ‘1’). Similarly, if the energy particle strike realized. The DNU recovery of the proposed cell is illustrated in
on node “Y” (state ‘0’), it produces a positive transient pulse (‘0’ to Fig. 6. However, it is observed that a very high energy particle strike
‘1’). This will force node “D” to charge to state ‘1’. According to can upset the node pair A-C.
physical phenomena, the only negative transient is possible due to
the capacity effect when an energy particle strikes the OFF NMOS 2.4. Implementations of SRAM Cells
transistor [29]. Hence node “D” will be changed from ‘0’ to ‘0’. As a
result, the P4 and N4 will be temporally switched OFF and ON, The simulation of SRAM cells has been analyzed in the Cadence tool
respectively. Hence, node “Y” is rolled back to the initial value. at VDD equal to 1.1 V with 45 nm CMOS technology. For the proposed
3) Case 3 (A radiation particle strikes node “C”:) When the energy par­ cell, the W/L ratio of transistors N3, P6, P8, and N4 (P3, P4, P5, P7) are
ticle strike node “C” (state ‘1’), it produces a negative transient pulse fixed to 140 nm/45 nm (190 nm/45 nm). The W/L of other transistors
(‘1’ to ‘0’). According to physical phenomena, the only negative (N1, N2, P1, P2, N5) of the proposed cell is fixed to 120 nm/45 nm. The
transient is possible due to the capacity effect when an energy par­ NMOSs N1 and N2 of the proposed cell are taken as high Vth MOSs to
ticle strikes the OFF NMOS transistor [29]. Hence node “C” will be improve the stability and reduce the power loss. Similarly, the N3, N4,
changed from ‘1’ to ‘0’ and node “D” from ‘0’ to ‘0’. As a result, the P6, and P8 are taken as low Vth driven MOSs to improve the voltage
PMOSs P8 and N4 will be temporally switched ON and OFF, swing. The transistors size for DICE [20] and RHBD-12T [23] are the
respectively. At the same time, node “A” (state ‘0’) will switch ON the same (1×). For RSP-14T, the W/L of the PMOSs (P0, P1, P2, P3, P4, P5,
P3, and node “C” is rolled back to the initial value. The simulated P6, P7) and NMOSs (N0, N1, N2, and N3) are 1× and 1.3×, respectively
responses of SNU recovery at all nodes of the proposed cell is [27]. The transistors size for RHBD-13T is the same (1×) except for P1
delineated in Fig. 5. and N1 (2.2×) [25]. For QUCCE, the cell ratio (CR) and pull-up ratio
(PR) is fixed to be 1.7 and 2.1, respectively [24]. However, in the We-
Due to physical phenomena, the surrounded PMOSs (NMOSs) QUATRO, all the transistors have the same (1×) except N5, N6, N7,
around nodes “A”(“C”) and “B” (“D”) in the proposed cell give only two and N8 (1.5×) [22]. For RHBD-14T, the transistor’s size is the same (1×)
except for P3 and P4 (2.1×) [26].

Fig. 5. Simulated responses for SNU self-recovery of the proposed cell. Fig. 6. Simulated responses for DNU recovery of the proposed cell.

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3. Evaluations
∑
n
POF = Pi × Pif (2)
3.1. Radiation tolerance comparison i=1

The probability of particle strike (Pi) at the sensitive area is the ratio
The critical charge (Qc) is one of the crucial parameters to judge of the sensitive area to the total layout area of the cell [33]. The Pi of the
SRAM radiation tolerance. The higher SRAM's Qc leads to increased proposed cell is less than other cells, and the comparison among them is
radiation tolerance for a design. The value of SNU/DNU Qc with com­ presented in Table 1. The probability of SNU/DNU occurrence (Pif) is the
parisons of cells is reported in Table 1. From Table 1, it can be observed ratio of the number of upsets to the total number of simulations (5000).
that the proposed cell gives the highest SNU/DNU Qc than other cells. The Pif comparison of all the cells is reported in Table 1 for Qc of 15 fC.
The We-QUATRO cell is observed as ‘1’ to ‘0’ immunes at all the The probability of failure (POF) of the SRAM cell is calculated by Pif and
nodes, but it is found that We-QUATRO at node “B” is sensitive when it Pi as presented in Eq. (2) [33], where n is the number of sensitive node
stores ‘0’ at node “B”. The RSP-14T cell is observed as ‘1’ to ‘0’ immunes pairs. The Pi and POF comparison of all the cells is reported in Table 1.
at all the nodes but susceptible to ‘0’ to ‘1’ upset at node “B” due to The proposed is the only one-bit cell providing zero POF at DNU critical
PMOS P7. It is observed that the DICE, RHBD-12T, RHBD-13T, RHBD- charge of 15 fC.
14T, and proposed cells are immune to a single event upset at all
nodes for all the possibilities (‘0’ to ‘1’ and ‘1’ to ‘0’). For DNU analysis, 3.2. Comparison cost of the proposed cell
the sensitive node pair and their respective Qc of SRAMs are reported in
Table 1. In the RHBD-12T, the two nodes “C” and “D” are surrounded by 1. Power and area comparison: The leakage current is a primary source
PMOS and NMOS hence two-node pairs B-C (A-C) and B-D (A-D) are of total power loss. The proposed cell has less leakage current due to
found DNU sensitive when state ‘1’ (‘0’) is stored at node “A”. Similarly, leakage paths from supply to ground through its two stacked in­
the RSP-14T has six sensitive node pairs for DNU analysis, as all the four- verters in their ideal state. The high Vth-driven MOSs (N3, P6, P8, N4)
node are surrounded by both PMOS and NMOS. However, in the pro­ are also responsible for reducing the leakage current. The reduction
posed cell, nodes “A” (“C”) and “B”(“D”) are surrounded by PMOSs of leakage current gives less static and total power cost among all the
(NMOSs). Hence only one node pair A-C (B-D) is sensitive for DNU cells. The power cost comparison of SRAMs is reported in Table 2.
analysis when state ‘0’ (‘1’) is stored at node “A”. Hence, the DNU Qc of
the proposed cell is 1.8×, 1.2×, 1.7×, 1.9×, 1.7×, 1.6×, and 1.5× more The layout of all the considered cells is designed in the Cadence tool
compared to RSP-14T, RHBD-14T, RHBD-13T, QUCCE-12T, RHBD-12T, with 45 nm CMOS technology. The proposed cell’s layout is designed
QUATRO.-12T, and DICE-12T, respectively. Thus, the proposed cell’s using 1-polysilicon and 3-metal layers as delineated in Fig. 7. The supply
soft error tolerance is superior to other cells. voltage (VDD), WL, RWL, and GND are designed vertically, and other
control pin-like BL, BLB, and RBL are designed horizontally in the
1) Probability of failure for DNU: The sensitive area is one of the crucial layout. The layout area comparison of the cells is reported in Table 2.
parameters in the SRAM to judge the occurrence of SNU/DNU The proposed cell’s area cost is less than DNU tolerant RHBD-13T,
[32,33]. The less sensitive area in the SRAM gives a less SNU/DNU RHBD-14T, and RSP-14T cells.
occurrence rate [32]. The no. of sensitive node pairs for SNU/DNU in
the SRAMs is reported in Table 1. According to [23] sensitive area is 2. Write and read speed comparison: In the proposed cell, two-ended
the area of drain junctions of the node, and the total area is the layout write circuitry is used to bias the data, as shown in Fig. 2. For
area of the SRAM cell. The sensitive area of the integrated circuit is writing ‘1’ or ‘0’, the write access transistors P1 and P2 will be turned
the drain area of OFF transistors [23]. Two or three sensitive node ON, and the nodes will start charging or discharging through PMOSs,
pairs exist for all considered SRAMs except the proposed SRAM. The respectively. The RHBD-13T [25] cell uses a single-ended write cir­
proposed SRAM has only one sensitive node pair (“A-C”). Hence, the cuitry to write the data. On the other hand, in DNU tolerant RSP-14T
sensitive area of the proposed SRAM is the least compared to all the cell [27], the dependency of output on each other and circuit
considered SRAMs. The sensitive area of all the SRAMs is reported in complexity is responsible for higher WAT. Hence, the WAT of DNU
Table 1. The proposed SRAM has the lowest sensitive area, highest tolerant cells like RHBD-13T [25] and RSP-14T [27] are increased
SNU/DNU critical charge. Hence the proposed SRAM has the lowest compared to the proposed cell, as reported in Table 2.
SNU/DNU occurrence compared to other SRAMs.

Table 1
Reliability comparisons of SRAMS.
SRAM cells No. of sensitive No. of sensitive SNU Qc DNU Qc No. of failures at Sensitive Probability of Failure POF for
nodes for SNU node-pairs for (fC) (fC) DNU Qc 15fC area (μm2) particle strike (Pi) Probability (Pif) DNU Qc of
DNU 15fC

Proposed- 0 1 62.23 16.02 0 0.12 0.075 0% 0

13T
RSP-14T 1 3 21.02 8.93 5000 0.30 0.168 100% 0.168
[27]
RHBD-14T 0 3 55.23 12.93 5000 0.32 0.188 100% 0.188
[26]
RHBD-13T 0 2 52.89 9.03 5000 0.23 0.137 100% 0.137
[25]
QUCCE12T 2 3 36.23 8.15 5000 0.28 0.189 100% 0.189
[24]
RHBD-12T 0 2 50.62 9.41 5000 0.21 0.147 100% 0.147
[23]
QUAT.-12T 1 3 49.23 9.82 5000 0.26 0.174 100% 0.174
[22]
DICE-12T 0 3 51.73 10.12 5000 0.25 0.158 100% 0.158
[20]

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Table 2
Overhead comparisons of SRAMS.
SRAM cells SNUR DNUR Static power (nW) Total power (μW) Area (μm2) RAT (ps) WAT (ps) Percentage reduced cost of proposed cell (%)

ΔSP ΔTP ΔA ΔR ΔW

Proposed-13T √ √ 26.83 2.12 1.596 78.11 11.93 – – – – –

RSP-14T [27] √ √ 33.02 2.71 1.778 88.78 13.36 18.75 21.77 10.24 12.02 10.70
RHBD-14T [26] √ √ 34.21 2.64 1.701 93.51 11.89 21.57 19.69 6.17 16.47 − 0.33
RHBD-13T [25] √ √ 45.32 2.98 1.672 85.01 21.02 40.79 28.86 4.54 8.12 43.24
QUCCE12T [24] × × 41.02 4.51 1.478 81.52 19.23 34.59 52.99 -7.39 4.18 37.96
RHBD-12T [23] √ × 32.82 2.56 1.432 91.32 10.23 18.25 17.18 − 10.3 14.46 − 14.2
QUAT.-12T [22] × × 38.23 3.73 1.492 76.13 16.81 29.82 43.16 − 6.52 − 2.53 29.03
DICE-12T [20] √ × 36.52 2.93 1.581 83.30 14.21 26.53 27.64 − 0.94 6.23 16.04

SNUR: single node upset resilience, DNUR: double node upset resilience

Fig. 7. The layout of the RHBD-13T proposed cell.

Fig. 8. (a) RAT comparison of SRAMs at various supply voltage, (b) RSNM comparison of SRAMs.

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The proposed cell has better RAT than other cells due to separate performance is required. To determine any circuit or device’s relative
read decouple circuitry i.e., NMOS N5. The separate N5 transistor is used utility, the figure of merits (FOM) is a crucial parameter. The power
at node “C” to read the data, as presented in Fig. 2. QUATRO-12T, consumption, access time, and area cost of the circuit should be lower.
RHBD-12T, QUCCE-12T, RHBD-14T, and RSP-14T cells are not using Similarly, the static noise margin and the critical charge should be high
separate read decouple circuits to read the data. Hence, the proposed [42]. Hence, here the novel FOM is presented by Eq. (3). There, the
cell’s RAT is reduced compared to the above-reported cells. The RHBD- terms R, H, W, TP, Qc, A, WT, and RT, are the RSNM, HSNM, WSNM,
13T cell uses decouple circuit to read the data, but it has more load total power, critical charge, area, write and read access time, respec­
capacitance at storing node, which increases the RAT of cell compared to tively. The FOM of the proposed cell is ×6.1, ×2.3, ×4.4, ×9.1, ×1.8,
the proposed cell. Hence, the RAT of the proposed cell is better than ×5.8, and ×5.7 higher compared to RSP-14T, RHBD-14T, RHBD-13T,
other cells, as shown in Table 1. QUCCE-12T, RHBD-12T, QUATRO.-12T, and DICE-12T, respectively.

3. Write, read, and hold stability comparison: The stability of the SRAM 3.4. Statistical analysis
cell is defined by hold SNM (HSNM), read SNM (RSNM), and write
SNM (WSNM) in the hold, read, and write mode, respectively The transistor's internal properties (like length, width, and thickness)
[34–38]. The RAT comparisons of cells at various voltage and but­ are subject to change throughout the manufacturing process [11]. The
terfly curves of cells during read mode are shown in Fig. 8 (a) and (b), mean (μ) and standard deviation (σ) of the output parameters are given
respectively. Similarly, the WAT comparisons of cells at various by the MC Simulation result. The designer may opt to adjust the design
voltage and butterfly curves of cells during write mode are delin­ based on the variance in output. Foundry companies provide a model
eated in Fig. 9 (a) and (b), respectively. The comparison of stability file for MC Simulation to determine output variation [11,38]. Also, to
(SNMs) is presented in Table 3. There, ΔH, ΔR, and ΔW mean relative check the process, voltage, and temperature (PVT) variations on SNU
HSNM, RSNM, and WSNM comparisons among the proposed and and SEDNU of bit-cells, the MC simulation has been performed [15].
considered cells, respectively. Gaussian variation is applied to the widths, lengths, and threshold
voltages of all-transistor with 3σ variation is used to perform 5000 MC
The WL and RWL are fixed to ‘1’ and ‘0’, respectively, to calculate the simulations [38]. The impact of variation on Qc variability caused by
HSNM of the proposed cell. The high Vth- driven MOSs are not affected different 3σ gate length (Lgate) and threshold voltage (Vth) variations has
by the smaller noises [39–41]. The proposed cell gives the highest HSNM been performed 45 nm CMOS technology. For 3%, 6%, and 9% of 3σ
among all the compared cells (except RHBD-14T) due to the more sig­ variation of Vth the 3σ variation of Qc are 3.6%, 2.2%, and 0.92%,
nificant feedback path during hold mode and high threshold pull-down respectively. Similarly, for 4%, 8%, and 12% of 3σ variation of Lgate the
transistors (N1, N4, P6, P8). To calculate the WSNM of the proposed cell, 3σ variation of Qc are 5.3%, 3.8%, and 2.9% respectively.
WL and RWL are fixed to ‘0’ and ‘1’, respectively. The WSNM of the
proposed cell is better among all the cells due to the high Vth pull-down 4. Conclusion
transistors and less driving voltage of nodes due to the higher length of
the write path. The WL and RWL are fixed to ‘0’ and ‘1’, respectively, to In this paper, the RHBD-13T SRAM cell has been presented to recover
calculate the RSNM of the proposed cell. The stronger pull-down tran­ from all the possible single and double node upsets with a better balance
sistors reduced driving voltage at nodes and increased length of the read of all other parameters. The main significant advantage of the proposed
path improved the RSNM of the proposed cell. Also, the separate disturb- cell is its highest critical charge, lowest power cost, and better stability
free read decouples circuitry in the proposed cell gives the highest RSNM among all other standard-considered cells. The speed of the proposed
compared to all other considered cells. Hence, the proposed cell is not cell is also better among many considered cells. The better FOM of the
only SNU/DNU tolerant but also provides better stability. proposed cell among all the cells proves that the proposed cell is a better
choice for critical aerospace applications where the DNUs are a severe
R × H × W × Qc
FOM = (3) issue.
TP × WT × RT × A
CRediT authorship contribution statement
3.3. Figure of merit (FOM)
Govind Prasad: Conceptualization, Formal analysis, Writing –
SRAM cells are used in space applications based on their effective Qc.
original draft. Bipin Chandra Mandi: Writing – review & editing,
Other essential design criteria include static noise margin (SNM), hold
Conceptualization. Maifuz Ali: Writing – review & editing,
power, area, and latency (read and write delay). However, improving
Conceptualization.
one design metric may necessitate lowering others. Increasing VDD may
enhance SNM, Qc, and latency. However, increasing VDD increases
power usage. By increasing transistor size also improves Qc, but in­
creases area overhead. Thus, a parameter to assess an SRAM cell’s total

Fig. 9. (a) WAT comparisons of SRAM cells at different supply voltage, (b) Butterfly curve of SRAM cells in Write mode (WSNM).

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G. Prasad et al. Microelectronics Reliability 133 (2022) 114526

Table 3
Stability comparisons of RHBD SRAM cells.
Stability RHBD14T [26] RSP14T [27] RHBD13T [25] DICE12T [20] We-QUATRO.12T [22] QUCCE12T [24] RHBD12T [23] Proposed13T

HSNM 401 254 361 238 277 304 383 395

ΔHM − 1.49% 35.69% 8.61% 39.75% 29.87% 23.04% 3.04% –
RSNM 179 157 162 191 173 186 192 182
ΔRM 1.65% 13.74% 10.99% − 4.71% 4.94% 2.15% − 5.21% –
WSNM 203 231 177 180 228 193 240 242
ΔWM 16.11% 4.54% 26.86% 25.62% 5.79% 20.25% 0.83% –

Declaration of competing interest [16] R. Giterman, L. Atias, A. Teman, A robust hardened latch featuring tolerance to
double-node-upset in 28nm CMOS for space borne application, IEEE Trans. Very
Large Scale Integr. (VLSI) Syst. 67 (9) (Sep. 2020) 1619–1623.
All authors have participated in the design and approval of the final [17] A. Yan, Z. Fan, L. Ding, J. Cui, Z. Huang, Q. Wang, H. Zheng, P. Girard, X. Wen,
manuscript version. Cost-effective and highly reliable circuit components design for safety-critical
This manuscript has not been submitted to, nor is under review at, applications, IEEE Trans. Aerospace Electronic Syst. 58 (1) (Aug. 2021) 517–529.
[18] D. Lin, Y. Xu, X. Li, X. Xie, J. Jiang, J. Ren, H. Zhu, Z. Zhang, S. Zou, A novel self-
another journal or other publishing venue. recoverable and triple nodes upset resilience DICE latch, IEICE Electron. Express 15
The contents of this manuscript will not be copyrighted, submitted, (19) (2018), 20180753.
or published elsewhere, while acceptance by the Journal is under [19] A. Yan, Z. Xu, X. Feng, J. Cui, Z. Chen, T. Ni, Z. Huang, P. Girard, X. Wen, Novel
quadruple-node-upset-tolerant latch designs with optimized overhead for reliable
consideration. computing in harsh radiation environments, IEEE Trans. Emerg. Top. Comput. 10
There are no directly related manuscripts or abstracts, published or (1) (Sep. 2020) 404–413.
unpublished, by any authors of this paper. [20] T. Calin, M. Nicolaidis, R. Velazco, Upset hardened memory design for submicron
CMOS technology, IEEE Trans. Nucl. Sci. 43 (6) (Dec. 1996) 2874–2878.
[21] M.J. Shah, D.J. Rennie, M. Sachdev, A soft error tolerant 10T SRAM bit-cell with
References differential read capability, IEEE Trans. Nucl. Sci. 56 (6) (Dec. 2009) 3768–3773.
[22] L.D.T. Dang, J.S. Kim, I.J. Chang, We-quatro: radiation-hardened SRAM cell with
[1] J. Guo, L. Zhu, Y. Sun, H. Cao, H. Huang, T. Wang, C. Qi, R. Zhang, X. Cao, L. Xiao, parametric process variation tolerance, IEEE Trans. Nucl. Sci. 64 (9) (Sep. 2017)
Z. Mao, Design of area-efficient and highly reliable RHBD 10T memory cell for 2489–2496.
aerospace applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst.: Briefs 26 [23] J. Guo, L. Zhu, W. Liu, H. Huang, S. Liu, T. Wang, L. Xiao, Z. Mao, Novel radiation-
(5) (May 2018) 991–994. hardened-by-design (RHBD) 12T memory cell for aerospace applications in
[2] W. Chen, X. Guo, C. Wang, F. Zhang, C. Qi, X. Wang, X. Jin, Y. Wei, S. Yang, nanoscale CMOS technology, IEEE Trans. Very Large Scale Integration (VLSI) Syst.
Z. Song, Single-event upsets in SRAMs with scaling technology nodes induced by 25 (5) (May 2017) 1593–1600.
terrestrial, nuclear reactor, and monoenergetic neutrons, IEEE Trans. Nucl. Sci. 66 [24] J. Jiang, Y. Xu, W. Zhu, J. Xiao, S. Zou, Quadruple cross-coupled latch based 10T
(6) (Jun. 2019) 856–865. and 12T SRAM bit cell designs for highly reliable terrestrial applications, IEEE
[3] M.S.M. Siddiqui, R. Sharma, L.V. Le, T. Yoo, I.J. Chang, T.T.H. Kim, SRAM Trans. Circuits Syst. I 66 (3) (Mar. 2019) 967–977.
radiation hardening through self-refresh operation and error correction, IEEE [25] S. Lin, Y.B. Kim, F. Lombardi, Analysis and design of nanoscale CMOS storage
Trans. Device Mater. Reliab. 15 (3) (Sep. 2015) 429–436. elements for single-event hardening with multiple-node upset, IEEE Trans. Device
[4] N. Gaspard, S. Jagannathan, Z. Diggins, M. McCurdy, T.D. Loveless, B.L. Bhuva, L. Mater. Reliab. 12 (1) (Mar. 2012) 68–77.
W. Massengill, W.T. Holman, T.S. Oates, Y.P. Fang, S.J. Wen, Estimation of [26] G. Prasad, B.C. Mandi, M. Ali, Power optimized SRAM cell with high radiation
hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in hardened for aerospace applications, Microelectron. J. 103 (Sep. 2020), 104843.
bulk CMOS, in: Proc. IEEE Inter. Reliability Physics Symposium (IRPS), CA, USA, [27] C. Peng, J. Huang, C. Liu, Q. Zhao, S. Xiao, X. Wu, Z. Lin, J. Chen, X. Zeng,
Apr. 2013 pp. SE-6. Radiation-hardened 14T SRAM bitcell with speed and power optimized for space
[5] A. Yan, Y. Ling, J. Cui, Z. Chen, Z. Huang, J. Song, P. Girard, X. Wen, Quadruple application, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27 (2) (Feb. 2019)
cross-coupled dual-interlocked-storage-cells-based multiple-node-upset-tolerant 407–415.
latch designs, IEEE Trans. Circuits Syst. Regul. Pap. 67 (3) (Mar. 2020) 879–890. [28] A. Yan, Z. Wu, J. Guo, J. Song, X. Wen, Novel double-node-upset-tolerant memory
[6] O.A. Amusan, L.W. Massengill, M.P. Baze, B.L. Bhuva, A.F. Witulski, J.D. Black, cell designs through radiation-hardening-by-design and layout, IEEE Trans. Reliab.
A. Balasubramanian, M.C. Casey, D.A. Black, J.R. Ahlbin, R.A. Reed, M. 68 (1) (Mar. 2019) 354–363.
W. McCurdy, Mitigation techniques for single-event-induced charge sharing in a [29] P.E. Dodd, L.W. Massengill, Basic mechanisms and modeling of single-event upset
90-nm bulk CMOS process, IEEE Trans. Device Mater. Reliab. 9 (2) (Jun. 2009) in digital microelectronics, IEEE Trans. Nucl. Sci. 50 (3) (Jun. 2003) 583–602.
311–317. [30] P.E. Dodd, Physics based simulation of single-event effects, IEEE Trans. Device
[7] F. Abouzeid, G. Gasiot, D. Soussan, C.L.M.D. Boissac, V. Malherbe, V. Bertin, Mater. Reliab. 5 (3) (Sep. 2005) 343–357.
G. Lallement, J.L. Autran, P. Roche, On-chip total ionizing dose digital monitor in [31] T. Heijmen, D. Giot, P. Roche, Factors that impact the critical charge of memory
fully depleted SOI technologies, IEEE Trans. Nucl. Sci. 67 (7) (Jul. 2020) elements, in: Proc. IEEE Int. On Line Testing Symp. (IOLTS'06), Lake Como, Italy,
1326–1331. Jul. 2006, pp. 57–62.
[8] K.P. Rodbell, D.F. Heidel, J.A. Pellish, P.W. Marshall, H.H.K. Tang, C.E. Murray, K. [32] C. Qi, L. Xiao, T. Wang, J. Li, L. Li, A highly reliable memory cell design combined
A. LaBel, M.S. Gordon, K.G. Stawiasz, J.R. Schwank, M.D. Berg, H.S. Kim, M. with layout-level approach to tolerant single event upsets, IEEE Trans. Device
R. Friendlich, A.M. Phan, C.M. Seidleck, 32 and 45 nm radiation-hardened-by- Mater. Reliab. 16 (3) (Sep. 2016) 388–395.
design (RHBD) SOI latches, IEEE Trans. Nucl. Sci. 58 (6) (Dec. 2011) 2702–2710. [33] C.N. Raghuram, B. Gupta, G. Kaushal, Single-event multiple effect tolerant
[9] N. Surana, J. Mekie, Energy efficient single-ended 6T SRAM for multimedia RHBD14T SRAM cell design for space applications, IEEE Trans. Device Mater.
applications, IEEE Trans. Circuits Syst. II 66 (6) (Jun. 2018) 1023–1027. Reliab. 21 (1) (Mar. 2021) 48–56.
[10] J.M. Dutertre, V. Beroulle, P. Candelier, S.D. Castro, L.B. Faber, M.L. Flottes, [34] J. Guo, L. Xiao, Z. Mao, Q. Zhao, Enhanced memory reliability against multiple cell
P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G.D. Natale, A. Papadimitriou, upsets using decimal matrix code, IEEE transVery Large Scale Integr. Syst. 22 (1)
B. Rouzeyre, Sensitivity to laser fault injection: CMOS FD-SOI vs. CMOS bulk, IEEE (Jan. 2014) 127–135.
Trans. Device Mater. Reliab. 19 (1) (Mar. 2019) 6–15. [35] I. Alouani, W.M. Elsharkasy, A.M. Eltawil, F.J. Kurdahi, S. Niar, AS8-static random
[11] D. Kobayashi, N. Hayashi, K. Hirose, Y. Kakehashi, O. Kawasaki, T. Makino, access memory (SRAM): asymmetric SRAM architecture for soft error hardening
T. Ohshima, D. Matsuura, Y. Mori, M. Kusano, T. Narita, S. Ishii, K. Masukawa, enhancement, IET Circ. Devices Syst. 11 (1) (Jan. 2017) 89–94.
Process variation aware analysis of SRAM SEU cross sections using data retention [36] M.J. Shah, M. Sharifkhani, M. Sachdev, An analytical model for soft error critical
voltage, IEEE Trans. Nucl. Sci. 66 (1) (Nov. 2018) 155–162. charge of nano-metric SRAMs, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17
[12] I. Chatterjee, B. Narasimham, N.N. Mahatme, B.L. Bhuva, R.A. Reed, R. (9) (Sep. 2009) 1187–1195.
D. Schrimpf, J.K. Wang, N. Vedula, B. Bartz, C. Monzel, Impact of technology [37] Q. Zhao, C. Peng, J. Chen, Z. Lin, X. Wu, Novel write enhanced and highly reliable
scaling on SRAM soft error rates, IEEE Trans. Nucl. Sci. 61 (6) (Dec. 2014) RHPD-12T SRAM cells for space applications, IEEE Trans. Very Large Scale Integr.
3512–3518. (VLSI) Syst. 28 (3) (Jan. 2020) 848–852.
[13] C.I. Kumar, B. Anand, A highly reliable and energy efficient radiation hardened [38] Y.Q. Aguiar, F. Wrobel, J.L. Autran, P. Leroux, F. Saigne, A.D. Touboul, V. Pouget,
12T SRAM cell design, IEEE Trans. Device Mater. Reliab. 20 (1) (Mar. 2020) 58–66. Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard
[14] A. Garg, T.T.H. Kim, SRAM array structures for energy efficiency enhancement, cell layouts under heavy ions, Microelectron. Reliab. 88 (Sep. 2018) 920–924.
IEEE Trans. Circuits Syst. Express Briefs 61 (6) (Jun. 2013), 1881–355. [39] C.N. Raghuram, B. Gupta, G. Kaushal, Double node upset tolerant RHBD15T SRAM
[15] T. Kato, T. Yamazaki, N. Saito, H. Matsuyama, Neutron-induced multiple-cell cell design for space applications, IEEE Trans. Device Mater. Reliab. 20 (1) (Mar.
upsets in 20-nm bulk SRAM: angular sensitivity and impact of multiwell potential 2020) 181–190.
perturbation, IEEE Trans. Nucl. Sci. 66 (7) (Jul. 2019) 1381–1389. [40] A. Yan, Y. Chen, Y. Hu, J. Zhou, T. Ni, J. Cui, P. Girard, X. Wen, Novel speed-and-
power-optimized SRAM cell designs with enhanced self-recoverability from single-

8
G. Prasad et al. Microelectronics Reliability 133 (2022) 114526

and double-node upsets, IEEE Trans. Circuits Syst. I 67 (12) (Aug. 2020) [42] H. Jiao, Y. Qiu, V. Kursun, Low power and robust memory circuits with
4684–4695. asymmetrical ground gating, Microelectron. J. 48 (Feb. 2016) 109–119.
[41] N. Zheng, P. Mazumder, Modeling and mitigation of static noise margin variation
in subthreshold SRAM cells, IEEE Trans. Circuits Syst. I 64 (10) (May 2018)
2726–2736, pp. SE-6.