1560 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO.

4, APRIL 2022

Soft-Error-Aware Read-Stability-Enhanced
Low-Power 12T SRAM With Multi-Node Upset
Recoverability for Aerospace Applications
Soumitra Pal , Member, IEEE, Wing-Hung Ki, Member, IEEE, and Chi-Ying Tsui, Senior Member, IEEE

Abstract— With the advancement of technology, the size of amount of cache memory is required [2]. Hence, SRAM cells,
transistors and the distance between them are reducing rapidly. which are used as cache memory, play a vital role in the power,
Therefore, the critical charge of sensitive nodes is reducing, area, and delay optimization of the processor.
making SRAM cells, used for aerospace applications, more
vulnerable to soft-error. If a radiation particle strikes a sensitive Deep space contains highly energetic particles, which
node of the standard 6T SRAM cell, the stored data in the impact the functionality of memory circuits [3]. On striking the
cell are flipped, causing a single-event upset (SEU). Therefore, substrate of an integrated circuit, such as semiconductor mem-
in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low- ory, an energetic particle generates electron-hole pairs. The
Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. electric field caused due to the reverse bias between the diffu-
To analyze the relative performance of SARP12T, it is compared
with other recently published soft-error-aware SRAM cells, sion region and substrate/n-well appears to the strike-generated
QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. minority carriers as a forward field. Hence, minority carriers
All the sensitive nodes of SARP12T can regain their data drift towards the drain diffusion regions, and on accumulation,
even if the node values are flipped due to a radiation strike. a positive or negative voltage spike is generated based on the
Furthermore, SARP12T can recover from the effect of single- type of minority carrier. If the level of the spike is beyond
event multi-node upsets (SEMNUs) induced at its storage node-
pair. Along with these advantages, the proposed cell exhibits the switching threshold of the logic circuit and its duration
the highest read stability, as the ‘0’-storing storage node, which is long enough, the stored content may flip, resulting in a
is directly accessed by the bitline during read operation, can phenomenon called single-event upset (SEU) or soft-error
recover from any upset. Furthermore, SARP12T consumes the [4], [5]. Furthermore, with minimum spacing between devices
least hold power. SARP12T also exhibits higher write ability and of an integrated circuit decreasing drastically due to aggressive
shorter write delay than most of the comparison cells. All these
improvements in the proposed cell are obtained by exhibiting technology scaling, a strike by a single ion may affect multiple
only a slightly longer read delay and consuming slightly higher nodes, which may result in a single-event multi-node upset
read and write energy. (SEMNU) [6].
Index Terms— Single-event upset (SEU), single-event multi- To address the effects of SEUs on memory, triple modular
node upsets (SEMNUs), critical charge, radiation hardness, read redundancy (TMR) has been used. This method uses three
stability, hold power, write ability. copies of memory cells, with majority voting to select and
output the correct value [7], [8]. If one copy is flipped,
I. I NTRODUCTION the other two will dominate the voting process, resulting
in the same output. However, this technique incurs huge
T HE aerospace industry has made human lives simpler
and improved security by providing a plethora of utili-
ties, such as satellite communications, military surveillance,
area and power penalties, making it unsuitable for most
designs [8], [9].
guidance, tracking systems, etc. In aerospace applications, Another way to mitigate the effects of SEUs is to employ
microprocessors are widely used for control and guidance, error correction codes (ECCs). However, ECCs incur huge
engine control, inertial navigation, etc. [1], and these proces- power, area and delay overhead due to the requirement of
sors are being embedded with multiple cores to upgrade their redundancy and extra devices for encoding and decoding
performance. A larger number of cores implies that a higher circuits [10], [11]. Therefore, soft-error-aware SRAMs are
preferred over ECCs because they are a less power-area- and
Manuscript received March 10, 2021; revised June 17, 2021 and July 26, delay-consuming solution [12]. Furthermore, it is preferred
2021; accepted August 18, 2021. Date of publication March 17, 2022; date
of current version March 29, 2022. This work was supported in part by
that the SRAM cell should have multi-node upset recover-
the Hong Kong Research Grants Council Areas of Excellence under Grant ability along with its SEU recovery ability [12].
AoE/P-404/18. This article was recommended by Associate Editor C. Wang. Due to the positive feedback of cross-coupled inverters in
(Corresponding author: Soumitra Pal.)
The authors are with the Department of Electronic and Computer Engi-
the 6T SRAM cell, an SEU occurring at one storage node
neering, The Hong Kong University of Science and Technology, Hong Kong alters the content of the other storage node automatically.
(e-mail: [email protected]). Hence, the 6T cell does not possess the characteristics that
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2022.3147675.
a soft-error-aware SRAM should [13]. Several soft-error-
Digital Object Identifier 10.1109/TCSI.2022.3147675 aware SRAM cells have been proposed in the literature.
1549-8328 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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PAL et al.: SARP12T SRAM WITH MULTI-NODE UPSET RECOVERABILITY 1561

QUATRO10T, proposed in [13], is capable of recovering

from a ‘1’→‘0’ SEU. However, it is unable to recover from
an SEU induced at the ‘0’-storing storage node. Moreover,
it shows a higher write failure probability. To improve its write
operation, the authors in [14] presented its modified version,
QUATRO12T. However, QUATRO12T also shows only par-
tial immunity to SEUs. Two further soft-error-aware SRAM
cells, QUCCE10T and QUCCE12T, were proposed in [11].
However, QUCCE10T exhibits poor write performance. More-
over, it cannot recover from a ‘0’→‘1’ SEU induced at its
‘0’-storing storage node, while QUCCE12T cannot recover
from a ‘0’→‘1’ SEU induced at both its ‘0’-storing storage
and internal nodes. Furthermore, QUCCE12T, along with
the previously mentioned QUATRO12T, consumes high hold
power. In short, all the above-mentioned cells are only partially
immune to SEUs and are unable to recover at all from
SEMNUs.
To achieve recovery from SEMNUs, the authors in [15] pro-
posed RHD12T, which can recover from SEMNUs occurring Fig. 1. Schematic of the proposed SARP12T SRAM cell.
at its internal node-pair. However, it cannot recover from SEUs
induced at its ‘0’-storing storage node. The enhanced version II. T HE P ROPOSED SARP12T C ELL AND I TS O PERATION
of RHD12T, called RSP14T [6], can tolerate a higher charge at The schematic of SARP12T and its equivalent layout are
the ‘0’-storing storage node. However, it still cannot recover shown in Fig. 1 and Fig. 2, respectively. SARP12T has two
the data if a ‘0’→‘1’ SEU of sufficient strength affects the wordlines, WL and WWL, two storage nodes, Q and QB,
node. Both types of SEUs, i.e., ‘1’→‘0’ and ‘0’→‘1’, induced and two internal nodes, S1 and S0. WL controls the access
at all the sensitive nodes and SEMNUs induced at one node- transistors N7 and N8, which connect the storage nodes Q
pair can be recovered by RHM12T [12] and RHPD12T [16]. and QB with their corresponding bitlines BL and BLB. The
However, in RHM12T, scaling down of the supply voltage internal nodes S1 and S0 are connected to their corresponding
(VDD ) is limited due to the excessive stacking present in the bitlines BL and BLB through their corresponding access
core inverters, while RHPD12T consumes a larger area and transistors N9 and N10, which are controlled by WWL. Let us
higher power due to the use of large-size transistors. contemplate SARP12T and all the comparison cells storing ‘1’,
Furthermore, it is to be noted that in all the above-mentioned i.e., Q = ‘1’ and QB = ‘0’. Thus, S1 and S0 are storing ‘1’ and
cells the ‘0’-storing storage and/or internal node(s) are directly ‘0’, respectively. With this consideration, the basic operations
accessed by the bitline during read operation and the node(s) and SEU recovery analysis of SARP12T are explained below.
cannot recover from upset. Therefore, all the above-mentioned
cells show poor read stability. A. Basic Operations
To address the above-mentioned issues, we propose the All the basic operations of the proposed SARP12T are
Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T mentioned in this sub-section.
(SARP12T) SRAM cell (Fig. 1) in this paper. SARP12T has 1) Hold Operation: During hold mode, both pairs of access
the following salient features: transistors are kept OFF by pulling down both WL and WWL
to GND. In order to shorten the read delay, bitlines are kept
1) SARP12T is immune to SEUs of both polarities induced
precharged to VDD during hold mode. Therefore, while the cell
at any sensitive node.
is in the hold state, transistors P1, N2, N3 and N6 remain ON,
2) The proposed cell can recover from SEMNUs that occur
while the rest of the transistors remain OFF for the considered
at its storage node-pair.
case. Thus, SARP12T maintains its initial stored data (Fig. 3).
3) SARP12T consumes the lowest hold power among all
2) Write Operation: During write operation, both the word-
the considered cells.
lines (WL and WWL) are activated. Therefore, both pairs of
4) SARP12T shows enhanced read stability as the
access transistors (N7/N8 and N9/N10) are turned ON. For
‘0’-storing storage node, which is directly accessed by
altering the stored data (i.e., writing ‘0’ at Q), BL is connected
the bitline during read operation, can recover from any
to GND, whereas BLB is clamped at VDD . As BL is connected
upset.
to GND, nodes Q and S1 are pulled down by BL through
5) The proposed cell shows higher write ability and shorter
N7 and N9, respectively. Subsequently, node Q turns ON P2
write delay than most of the comparison cells.
and turns OFF N6, whereas node S1 turns OFF N2 and N3.
This paper is further presented as follows− Section II In the meantime, nodes QB and S0 are pulled up by BLB
explains the basic operations and SEU recovery ability of the through N8 and N10, respectively. Consequently, node QB
proposed SARP12T cell. The simulation setup and compara- turns OFF P1 and turns ON N5. Similarly, node S0 turns ON
tive analysis are discussed in Section III. Section IV concludes N1 and N4. The cross-coupling between P1 and P2 amplifies
the paper. the potential difference between Q and QB. Similarly, the

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1562 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 4, APRIL 2022

Fig. 2. Thin cell layout of SARP12T.

cross-coupling between N3 and N4 enhances the potential

difference between S1 and S0. Therefore, the write operation
is performed successfully (Fig. 3).
3) Read Operation: During read operation, WL is con-
nected to VDD , whereas WWL is kept deactivated. There-
fore, access transistors N7 and N8 are turned ON, while
the other access transistors (N9 and N10) remain OFF. For
read operation, bitlines are precharged to VDD . Therefore,
BLB discharges through N8, N2 and N3. On the other hand,
as N1 and N4 are OFF, BL stays at VDD (Fig. 3). Once
the voltage difference between BL and BLB reaches 50 mV,
a sense amplifier (not shown) can sense the stored data, which Fig. 3. Sequence diagram of basic operations and soft-error recovery at
completes the read operation. different nodes of the proposed cell.

B. SEU Recovery Analysis turned ON and OFF, respectively. Since N6 is turned OFF
This sub-section gives a brief discussion of the proposed cell and N4 remains OFF (by virtue of its hold mode), node S1
when its sensitive nodes are affected by an SEU. A sensitive goes to a high impedance state and retains its logic value.
node is the surroundings of the reverse biased drain diffusion Therefore, N2 and N3 remain ON. Though P2 is turned ON,
region of an OFF transistor. If a radiation particle strikes the as NMOS transistors N2 (2.5×) and N3 (2.5×) are made larger
drain terminal of a PMOS, it produces either a ‘0’→‘1’ or than the PMOS transistor P2 (1×), QB stays at its original
‘1’→‘1’ transient pulse, based on the data that the node was logic level. Since QB retains its state, P1 remains ON and N5
storing initially. On the other hand, if an energetic particle remains OFF. Furthermore, as N3 is ON, S0 stays at ‘0’ and
strikes an NMOS, it generates either a ‘0’→‘0’ or ‘1’→‘0’ keeps N1 OFF. Therefore, Q recovers its original data (Fig. 3).
transient pulse. It is to be noted that, as the ‘0’-storing internal 3) SEU @ QB: When an SEU of enough strength influences
node (S0) of SARP12T is surrounded by drain terminals of ‘0’-storing storage node QB, the logic value changes to ‘1’
only NMOS transistors, only a ‘0’→‘0’ spike is generated, (Fig. 3). Subsequently, P1 is temporarily turned OFF and N5
which does not affect the logic state of the node. Hence, for is temporarily turned ON. Though N5 is turned ON, node S0
the ‘1’-storing case of SARP12T (i.e, Q = ‘1’, QB = ‘0’, retains its logic state because N3 (remains ON by virtue of its
S1 = ‘1’ and S0 = ‘0’), node S0 is not sensitive, whereas the hold mode) is made larger (2.5×) than N5. Therefore, N1 and
other nodes, i.e., Q, QB and S1, are sensitive. N4 remain OFF. Since both the pull-up (P1) and pull-down
1) SEU @ S1: When the ‘1’-storing internal node S1 is (N1) transistors corresponding to Q are OFF, node Q goes to
affected by an SEU, the node value changes from ‘1’ to a high impedance state and retains its initial logic state. As N4
‘0’ (Fig. 3). Consequently, transistors N2 and N3 are turned remains OFF and N6 (driven by Q) remains ON, S1 stays at
OFF. However, the pull-up transistor P2, corresponding to QB, its original logic value and keeps N2 and N3 ON. Hence, node
is kept OFF by the unaffected node Q. Since, both the pull-up QB is discharged to GND (Fig. 3).
and pull-down paths corresponding to QB are disconnected, 4) SEMNU @ Q-QB: When both the storage nodes Q and
node QB goes to a high impedance state. Generally, a high QB are simultaneously affected due to an SEMNU, node Q
impedance state does not change the logic state of the node. transits from ‘1’→‘0’ and node QB changes from ‘0’→‘1’.
Hence, QB maintains its initial logic value and keeps N5 OFF. Therefore, Q turns ON P2 and turns OFF N6. Similarly,
Therefore, S0 also goes to a high impedance state (as N5 and QB turns OFF P1 and turns ON N5. Though N5 is turned ON,
N3 are OFF) and retains its initial logic value. Since Q, QB and node S0 retains its logic level (as explained in Section II-B.3).
S0 retain their states, S1 recovers its original state (Fig. 3). Since the logic state of S0 is unaffected, transistors N1 and
2) SEU @ Q: When ‘1’-storing storage node Q is influ- N4 remain OFF. As both N6 and N4 are OFF, node S1
enced by an SEU, the logic state of the node transits to ‘0’ goes to a high impedance state and stays at its original logic
(Fig. 3). Therefore, transistors P2 and N6 are temporarily state. Therefore, N2 and N3 remain ON, and hence, QB is

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PAL et al.: SARP12T SRAM WITH MULTI-NODE UPSET RECOVERABILITY 1563

discharged to GND. Since N1 is OFF (as S0 retains its state)

and P1 is turned ON (as driven by QB), node Q is brought
back to ‘1’. Therefore, both Q and QB recover their original
states.
Therefore, the proposed SARP12T cell can recover from
the effect of an SEU induced at node S1 or Q or QB, and
can also recover from an SEMNU induced at the Q-QB
node-pair. However, if enough charge is collected at the
node-pair S1-Q/S1-QB, node S1 may transit from ‘1’→‘0’,
which turns OFF N2 and N3, whereas node Q/QB may
alter from ‘1’→‘0’/‘0’→‘1’, which turns OFF N6/P1 and
turns ON P2/N5. Hence, the stored data of the cell may
become altered. However, charge sharing between two NMOS
transistors (NMOS and PMOS transistors) can be avoided if
they are greater than 2 μm (0.6 μm) apart. Therefore, charge
sharing at the S1-Q and S1-QB node-pairs is avoided by
keeping enough spacing between them (Fig. 2).

III. S IMULATION S ETUP AND R ESULTS

Various design metrics of the proposed SARP12T cell Fig. 4. TRA of comparison cells at different VDDs .
have been estimated using 65-nm CMOS technology. For
comparison purposes, the estimated design metrics of
SARP12T are compared with those of other contemporary at lower voltages the higher bitline capacitance becomes dom-
cells, QUCCE12T [11], QUATRO12T [14], RHD12T [15], inant and the extra read path in these cells cannot compensate
RHPD12T [16] and RSP14T [6]. The sizing specified by for the effect of the increased bitline capacitance and the cells
their respective papers is used for QUCCE12T, QUATRO12T, fail to compete with the higher CR of RHD12T and RSP14T.
RHPD12T and RSP14T for simulation. An equivalent sizing On the other hand, because of a lower CR (1.5, 1.33) in both its
for RHD12T is considered as no sizing is mentioned in the read paths, QUATRO12T shows a longer TRA than RHD12T
paper. at all VDDs . Along with a higher bitline capacitance, SARP12T
has only a single read path (see Section II-A.3), and hence it
A. Read Delay Comparison shows a longer TRA (Fig. 4).
Read delay or access time (TRA ) is evaluated as the time
required to develop a 50 mV voltage difference between the B. Read Stability Comparison
bitlines since the WL crosses 50% in its rising edge. The TRA During read operation, the voltage that is developed at the
of an SRAM cell mainly depends on the read current and ‘0’-storing node(s) can potentially flip the stored content of
bitline capacitance. During read operation, a voltage bump is the SRAM cell. The higher the voltage rises at the ‘0’-storing
developed at the ‘0’-storing node(s) due to the voltage divider node(s), the higher the probability that the cell will suffer read
formed between the access device(s) and the driver transis- upset. The read static noise margin (RSNM) is the traditional
tor(s). This increases the threshold voltage (Vth ) and reduces metric for assessing the read stability of an SRAM cell [17].
the driving strength of the corresponding access device(s) The RSNM values of all the comparison cells at different VDDs
because of the increased body effect. The cells with a single are shown in Fig. 5.
access transistor attached to each bitline possess similar bitline Since RSP14T and RHD12T have a higher CR, a lower
capacitance. Therefore, for these cells, the TRA mainly relies voltage is developed at their respective ‘0’-storing storage
on the current through the read path, which eventually relies on nodes. Hence, they exhibit a higher RSNM as per their CR
the body effect offered to the access transistor. Hence, the cell values (Fig. 5). Since both the internal and storage nodes of
ratio (CR) is crucial for read delay comparison. Since RSP14T QUATRO12T, QUCCE12T and RHPD12T are susceptible to
(CR = 3) possesses a higher CR value than RHD12T (CR = read upsets as all their nodes are accessed by the bitlines
2.5), it shows a shorter TRA (Fig. 4). during read mode, they show a reduced RSNM compared to all
Having two additional access transistors connected to their other cells. Among these, RHPD12T exhibits a higher RSNM
bitlines, RHPD12T, QUCCE12T, QUATRO12T and SARP12T (Fig. 5) due to its higher CR.
possess higher bitline capacitance, which tends to extend It can be observed from Fig. 5 that, though the proposed
the TRA , whereas the extra read path in these cells, except SARP12T exhibits a slightly lower RSNM at very low voltage,
SARP12T (SARP12T has only a single read discharge path), it exhibits a higher RSNM at higher voltages. This is because
tends to shorten it. Therefore, RHPD12T and QUCCE12T the ‘0’-storing storage node QB of SARP12T, which is directly
show a shorter TRA than RSP14T. Among them, RHPD12T accessed by the bitline during read operation, can recover from
exhibits the shortest TRA due to its higher CR (2, 2) in both any upset (as explained in Section II-B.3) at higher voltages.
the read paths than that of QUCCE12T (1.8, 1.8). However, Therefore, during read operation, even if the voltage at QB

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1564 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 4, APRIL 2022

Fig. 5. RSNM of all the comparison cells at different VDDs . Fig. 6. TWA of all the considered cells at different VDDs .

rises beyond the switching threshold of the logic, the proposed

cell can recover its original stored data, and hence, the cell
shows enhanced read stability.

C. Write Delay and Write Ability Comparison

Write delay or access time (TWA ) is gauged as the difference
in time from the WL reaching 50% of its full swing till the
storage nodes Q and QB cross each other. RHD12T, having
longer feedback in flipping the stored data, exhibits a longer
TWA (Fig. 6). RSP14T, the enhanced version of RHD12T,
shows a shorter TWA than RHD12T since the ‘1’-storing
internal node discharges faster in RSP14T. This is because the
pull-up path, corresponding to its initially ‘1’-storing internal
node, gets weaker as the voltage at QB rises, while the same
internal node in RHD12T requires a longer time to discharge
due to the fight that exists between the pull-up and pull-down
transistors corresponding to the node.
As two extra access transistors are connected to the
internal nodes of QUCCE12T, QUATRO12T, RHPD12T and
SARP12T, both their internal and storage nodes change simul- Fig. 7. WWTV of all the comparison cells at different VDDs .
taneously and hence, they show a shorter TWA . Among them,
RHPD12T and SARP12T exhibit an even shorter TWA than
QUCCE12T and QUATRO12T. This is due to the poor driving It is important to note that during the write operation of
ability of the internal nodes in the former two cells. For SARP12T, both the wordlines WL and WWL are considered to
instance, in SARP12T, as the ‘1’-storing internal node S1 be activated at the same time. However, if a difference between
is pulled up by an NMOS, it stores a weak ‘1’. Therefore, the arrival time of WL and WWL occurs, the corresponding
it becomes easier for the corresponding access transistor to access transistors will not be turned on at the exact same time,
discharge the weak ‘1’ at node S1. Furthermore, since the and hence, the write delay will be prolonged. For instance,
‘0’-storing internal node S0 has been pulled down by this weak if WL arrives earlier than WWL, then N9/N10 will be turned
‘1’, initial charging of S0 is easier. Therefore, the reduced volt- on later than N7/N8. This will result in a delayed write
age swing of S1 and S0 helps in write operation. Even though, operation.
the internal nodes of both RHPD12T and SARP12T exhibit The ease with which an SRAM can change its data during
poor driving ability, RHPD12T shows a relatively shorter TWA write operation is the measure of its write ability. Conven-
due to its lower γ ratio or pull-up ratio corresponding to both tionally, write ability has been evaluated using the write static
the internal and storage nodes. noise margin (WSNM). However, as per recent studies, the

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PAL et al.: SARP12T SRAM WITH MULTI-NODE UPSET RECOVERABILITY 1565

Fig. 8. Energy consumption during read mode (EREAD ) at different VDDs . Fig. 9. Energy consumption during write mode (EWRITE ) at different VDDs .

in comparison to only two access transistors in RHD12T,

wordline write trip voltage (WWTV) is a more reliable method
RSP14T, and SARP12T. Hence, these cells consume higher
to judge the write ability of an SRAM cell. For analyzing
dynamic power, which eventually leads to higher EREAD
the WWTV, BL and BLB are fed with the required data that
consumption. Among these cells, RHPD12T consumes the
is to be written, followed by ramping up the voltage of the
highest EREAD because of the much larger transistors used
wordline(s). The WWTV is gauged as the difference of VDD
in its design.
and the WL voltage when Q and QB cross each other. It is to
2) Write Energy Consumption: The energy consumption
be observed that a cell with a longer TWA requires more time
during write mode (EWRITE ) of all the cells at different VDDs
to alter its stored data, and hence, a higher voltage rise at WL
is shown in Fig. 9. Though RHD12T and RSP14T show a
takes place. Therefore, a cell, which exhibits a longer TWA ,
longer TWA , they consume lower EWRITE because of their
also shows a lower WWTV. Hence, the order of the cells for
much lower dynamic power consumption. On the other hand,
WWTV (Fig. 7) is the exact opposite to that of TWA (Fig. 6).
SARP12T consumes lower EWRITE than the cells having two
D. Energy Consumption Analysis access transistors adjacent to each bitline because of its shorter
TWA . Though RHPD12T shows the shortest TWA , it consumes
In an SRAM cell, dynamic power is divided into two
higher EWRITE because of its much higher dynamic power
components: read power and write power. During read oper-
consumption.
ation, the voltage swing of the bitlines is limited to a smaller
value, whereas write operation requires full voltage swing
on the bitlines [18]. As a result, the power consumption E. Hold Power Comparison
during write operation is considerably higher than during read Hold power (HPWR ) dissipation is a major contributor to the
operation. While dynamic power consumption decreases with total power consumption in an SRAM cell. HPWR is consumed
supply voltage scaling, the delay of an SRAM cell increases. mainly due to bitline leakage and leakage in inverters. The
Therefore, it is important to consider the energy consumption HPWR comparison of all the considered cells is shown in
per read/write cycle for all the comparison cells. Fig. 10. It can be observed from the figure that RHPD12T,
1) Read Energy Consumption: The energy consumption QUCCE12T and QUATRO12T dissipate higher HPWR com-
during read operation (EREAD ) of different cells at varying pared to all other cells, which is due to the absence of stacking
VDD is shown in Fig. 8. As RHD12T and RSP14T have a and the presence of excess access transistors. Since there is
single access transistor adjacent to each bitline, they possess only one access transistor attached to each bitline and stacking
lower bitline capacitance and hence consume lower dynamic exists in the pull-up path of the core inverters of RSP14T
power. Furthermore, their TRA is also on the shorter side. and RHD12T, they consume lower HPWR . Between these two
Therefore, these cells consume lower EREAD than other cells. cells, RSP14T consumes the higher HPWR due to its larger
On the other hand, RHPD12T, QUATRO12T, QUCCE12T, pull-down transistors. However, SARP12T consumes the least
and SARP12T have two access transistors adjacent to each HPWR (Fig. 10). This is because it has NMOS stacking in the
bitline, and hence, they possess higher bitline capacitance. pull-down path of the core inverters. Furthermore, SARP12T
Furthermore, the power consumption due to the activation of has only two NMOS transistors that are connected to GND,
the wordline in RHPD12T, QUATRO12T, and QUCCE12T is whereas all other comparison cells have four transistors con-
also higher as their wordline controls four access transistors, nected to GND. Therefore, less current is sunk by SARP12T.

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1566 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 4, APRIL 2022

Fig. 11. Equivalent circuit for generating a negative transient pulse.

Fig. 10. HPWR of all the considered cells at various VDDs .

TABLE I
C RITICAL C HARGE (QC ) C OMPARISONS

F. Soft-Error Recovery Simulations and Comparison

A double exponential current source is applied to emulate
an SEU and verify the soft-error robustness of the proposed
cell. The direction of the current source is decided such that it
produces a negative transient pulse at the drain of an NMOS
(Fig. 11) and a positive transient pulse at the drain of a PMOS
Fig. 12. Equivalent circuit for generating a positive transient pulse.
(Fig. 12). The injected current source is expressed by the
equation given as follows:
−t −t
Iinj(t) = I O (e τα − e τβ ), (1) It is evident from the table that SARP12T can withstand higher
Q doses of radiation at all sensitive nodes compared to all other
IO = , (2) considered cells. The behavior of soft-error recovery when
τα − τβ
different amounts of charge are collected at each sensitive node
where I0 = peak current of the current pulse, τα = collection of the proposed cell is shown in Fig. 13. It can be seen from
time constant of a junction, τβ = initial ion-track-establishing Fig. 13(a–c) that even when a 75 fC charge is collected at all
time constant, and Q = injected charge at a sensitive node. the sensitive nodes of SARP12T, individually, the nodes can
In this paper, τα = 200 ps and τβ = 50 ps are considered. recover their initial data even after being flipped by an SEU.
This chosen method for analyzing the soft-error tolerance has Furthermore, as previously mentioned, in advanced technol-
been proven to yield the same correct results as the 3-D device ogy the charge collected at one sensitive node of an SRAM
modeling approach. cell can affect the other sensitive nodes, by virtue of charge
The critical charge, QC , is the minimum charge collected at sharing, due to reduced transistor spacing. Therefore, we have
a sensitive node which is enough to alter the data previously estimated the shared charge, which can potentially flip a cell
stored in a storage node. The critical charge of all the sensitive when multiple nodes are affected, for all the considered cells
nodes is estimated, and the lowest is considered to be the in accordance with [19]. Fig. 14 presents the estimated critical
cell’s effective QC , which signifies its soft-error tolerance. charge sharing values of all the considered cells. The larger
Table I reports the effective QC of all the considered cells. the area under the curve in Fig. 14, the greater the ability

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PAL et al.: SARP12T SRAM WITH MULTI-NODE UPSET RECOVERABILITY 1567

Fig. 13. Behavior of soft-error recovery when different amounts of charge are collected at (a) node S1, (b) node Q, and (c) node QB, individually, and
(d) the storage node-pair Q-QB, simultaneously, of the proposed cell.

TABLE II
P ROBABILITY OF R ECOVERY FAILURE

even if the shared charge is more than 75 fC. The behavior

of soft-error recovery when different amounts of charge are
collected at the storage node-pair of the proposed cell is
shown in Fig. 13(d). It can be observed from Fig. 13(d) that
even when 75 fC charge is collected at both Q and QB
simultaneously, SARP12T can regain its initial state.
Fig. 14. Critical charge comparison for multi-node upset scenarios.
Knowing the threat of process variations in advanced tech-
nology, an SRAM cell needs to withstand the harsh sur-
of the SRAM to tolerate multi-node upset. It is noticeable roundings in space and function reliably. Therefore, it is
in Fig. 14 that SARP12T can recover from multi-node upset, important to verify the ability of an SRAM cell to recover

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1568 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 4, APRIL 2022

Fig. 15. Recovery of SARP12T when its (a) node S1, (b) node Q, (c) node QB and (d) storage node-pair Q-QB are affected by SEUs at V DD = 1 V. Insets:
results of 2000 MC simulations.

stored data reliably when its sensitive nodes are subjected to Table II presents the PRF of all the comparison cells. It is
SEUs or SEMNUs. To verify this, we have carried out Monte noticeable from the table that SARP12T can recover from
Carlo (MC) simulations with a sample size of 2000 while SEMNUs even in the presence of PVT variations, without a
injecting a 75 fC charge at all the single sensitive nodes, single failure (can also be seen from Fig. 15(d)), whereas the
individually, and at the storage node-pair, simultaneously, other comparison cells fail to recover from SEMNUs reliably.
in the presence of process, voltage and temperature (PVT)
variations. It is observed from the simulations that SARP12T G. Layout Area Comparison
can recover from SEUs induced at all its sensitive nodes and Layouts of all the considered cells are drawn to compare
SEMNUs induced at the Q-QB node-pair even in the presence the area of SARP12T with that of other cells. The thin cell
of PVT variations (Fig. 15). layout of SARP12T is shown in Fig. 2. The relative area of
Moreover, the reliability of a cell to recover from multi-node all the considered cells, with respect to SARP12T, is reported
upset is analyzed by estimating the probability of recovery- in Table III. It can be observed from the table that SARP12T
failure (PRF ), as given by consumes slightly larger area than the 12T cells, QUCCE12T
and QUATRO12T. This is due to the use of larger pull-down
# simulations failed to recover transistors in the proposed cell. Even though RHD12T also
PRF (%) = × 100. (3)
total number of simulations has 12 transistors in its design, it occupies a larger area

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PAL et al.: SARP12T SRAM WITH MULTI-NODE UPSET RECOVERABILITY 1569

TABLE III A cell with a higher EQM shows a better overall per-
R ELATIVE A REA C OMPARISON formance. The relative EQM (with respect to SARP12T)
values, are shown in Fig. 16. The figure clearly illustrates
that the proposed SARP12T shows the highest EQM, thereby
validating its superior performance.

IV. C ONCLUSION
In this paper, a soft-error-aware read-stability-enhanced low-
power SRAM cell is proposed for aerospace applications.
SARP12T can regain its original data at all the sensitive
nodes, even if the node values are flipped by a radiation
strike. Furthermore, SARP12T can recover from the effect
of multi-node upset due to a single ion strike at the storage
node-pair. In addition to these advantages, the proposed cell
also exhibits the highest RSNM and consumes the lowest hold
power, while also showing better write performance compared
to most of the comparison cells. Moreover, SARP12T proves
its superiority over other contemporary cells by exhibiting
the highest EQM. Therefore, the proposed SARP12T can be
considered a better choice for aerospace applications.

R EFERENCES
[1] G. S. Mersten, “Microprocessors in aerospace applications,” in Proc.
Compcon Fall, Washington, DC, USA, Sep. 1979, pp. 264–269,
doi: 10.1109/CMPCON.1979.729122.
[2] G. Prasad, B. C. Mandi, and M. Ali, “Power optimized SRAM cell with
high radiation hardened for aerospace applications,” Microelectron. J.,
vol. 103, Sep. 2020, Art. no. 104843, doi: 10.1016/j.mejo.2020.104843.
[3] F. Pavón-Carrasco and A. De Santis, “The South Atlantic anomaly: The
Fig. 16. Relative EQM with respect to SARP12T at VDD = 1 V. key for a possible geomagnetic reversal,” Frontiers Earth Sci., vol. 4,
p. 40, Apr. 2016.
[4] J. Guo, L. Xiao, T. Wang, S. Liu, X. Wang, and Z. Mao, “Soft
than SARP12T because it has more PMOS (6) in its cell error hardened memory design for nanoscale complementary metal
design compared to the proposed SARP12T (2). RSP14T also oxide semiconductor technology,” IEEE Trans. Rel., vol. 64, no. 2,
pp. 596–602, 2015, doi: 10.1109/TR.2015.2410275.
consumes even larger area than SARP12T because it has more [5] J. Guo et al., “Design of area-efficient and highly reliable RHBD
transistors in its design. However, RHPD12T consumes the 10T memory cell for aerospace applications,” IEEE Trans. Very Large
largest area (Table III) among the cells because it is designed Scale Integr. (VLSI) Syst., vol. 26, no. 5, pp. 991–994, May 2018, doi:
10.1109/TVLSI.2017.2788439.
with much larger transistors. [6] C. Peng, “Radiation-hardened 14T SRAM bitcell with speed and
power optimized for space application,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 27, no. 2, pp. 407–415, Nov. 2019, doi:
H. New Performance Metric for SRAM Cells 10.1109/TVLSI.2018.2879341.
The critical charge (QC ) determines an SRAM cell’s util- [7] D. G. Mavis and P. H. Eaton, “Soft error rate mitigation techniques for
modern microcircuits,” in Proc. IEEE Int. Rel. Phys. Symp. 40th Annu.,
ity in aerospace, and all other design metrics discussed in Apr. 2002, pp. 216–225, doi: 10.1109/RELPHY.2002.996639.
the preceding sub-sections are also important to consider [8] S.-F. Liu, P. Reviriego, and J. A. Maestro, “Efficient majority logic
for designing an SRAM cell. However, it is to be noted fault detection with difference-set codes for memory applications,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148–156,
that these SRAM design metrics are conflicting in nature. Jan. 2012, doi: 10.1109/TVLSI.2010.2091432.
For example, QC , RSNM, WWTV, TRA and TWA can be [9] M. Nicolaidis, “Design for soft error mitigation,” IEEE Trans.
improved by increasing VDD , but at the expense of higher Device Mater. Rel., vol. 5, no. 3, pp. 405–418, Sep. 2005, doi:
10.1109/TDMR.2005.855790.
power consumption (both hold power and dynamic power). [10] J. Gracia-Morán, L. J. Saiz-Adalid, D. Gil-Tomás, and P. J. Gil-Vicente,
QC can also be improved by increasing the node capacitance “Improving error correction codes for multiple-cell upsets in space
using upsized transistors. However, this will result in a larger applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26,
no. 10, pp. 2132–2142, Oct. 2018, doi: 10.1109/TVLSI.2018.2837220.
area overhead and higher power consumption. Therefore, it is [11] J. Jiang, Y. Xu, W. Zhu, J. Xiao, and S. Zou, “Quadruple cross-coupled
not accurate to judge the overall performance of an SRAM latch-based 10T and 12T SRAM bit-cell designs for highly reliable ter-
cell by comparing individual parameters. This necessitates restrial applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66,
no. 3, pp. 967–977, Mar. 2019, doi: 10.1109/TCSI.2018.2872507.
a design metric with which the overall performance of an [12] J. Guo, L. Xiao, and Z. Mao, “Novel low-power and highly reliable
SRAM cell can be gauged. For this purpose, we present an radiation hardened memory cell for 65 nm CMOS technology,” IEEE
electrical quality metric (EQM) that can estimate the overall Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 7, pp. 1994–2001,
Jul. 2014, doi: 10.1109/TCSI.2014.2304658.
performance of an SRAM, which is in line with [20]: [13] S. M. Jahinuzzaman, D. J. Rennie, and M. Sachdev, “A soft
Q C × RSNM × WWTV error tolerant 10T SRAM bit-cell with differential read capability,”
E QM = . (4) IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3768–3773, Dec. 2009,
E READ × E WRITE × HPWR × Area doi: 10.1109/TNS.2009.2032090.

Authorized licensed use limited to: Tsinghua University. Downloaded on May 30,2023 at 22:30:15 UTC from IEEE Xplore. Restrictions apply.
1570 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 4, APRIL 2022

[14] L. D. T. Dang, J. S. Kim, and I. J. Chang, “We-quatro: Radiation- Wing-Hung Ki (Member, IEEE) received the B.Sc.
hardened SRAM cell with parametric process variation tolerance,” IEEE degree from the University of California at San
Trans. Nucl. Sci., vol. 64, no. 9, pp. 2489–2496, Sep. 2017, doi: Diego, San Diego, CA, USA, in 1984, the M.Sc.
10.1109/TNS.2017.2728180. degree from the California Institute of Technology,
[15] C. Qi, L. Xiao, T. Wang, J. Li, and L. Li, “A highly reliable memory Pasadena, CA, USA, in 1985, and the Ph.D. degree
cell design combined with layout-level approach to tolerant single-event from the University of California at Los Angeles,
upsets,” IEEE Trans. Device Mater. Rel., vol. 16, no. 3, pp. 388–395, Los Angeles, CA, USA, in 1995.
Sep. 2016, doi: 10.1109/TDMR.2016.2593590. In 1992, he joined Micro Linear, San Jose, where
[16] Q. Zhao, C. Peng, J. Chen, Z. Lin, and X. Wu, “Novel write-enhanced he was involved in the design of power converter
and highly reliable RHPD-12T SRAM cells for space applications,” controllers. In 1995, he joined The Hong Kong
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 28, no. 3, University of Science and Technology, Hong Kong,
pp. 848–852, Mar. 2020, doi: 10.1109/TVLSI.2019.2955865. where he is currently a Professor with the Department of Electronic and
[17] E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis Computer Engineering. His current research interests include power manage-
of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. 22, no. 5, ment circuits and systems, switched-inductor and switched capacitor power
pp. 748–754, Oct. 1987, doi: 10.1109/JSSC.1987.1052809. converters, low dropout regulators, wireless power transfer for biomedical
[18] V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, implants, and analog IC design methodologies.
and W. Dehaene, “A 4.4 pJ/access 80 MHz, 128 kbit variability Dr. Ki has served on the International Technical Program Committee of
resilient SRAM with multi-sized sense amplifier redundancy,” IEEE the International Solid-State Circuits Conference from 2010 to 2014. He has
J. Solid-State Circuits, vol. 46, no. 10, pp. 2416–2430, Oct. 2011, doi: served as an Associate Editor for the IEEE T RANSACTIONS ON C IRCUITS
10.1109/JSSC.2011.2159056. AND S YSTEMS —II: E XPRESS B RIEFS . He is also an Associate Editor of the
[19] S. Pal, S. Mohapatra, W.-H. Ki, and A. Islam, “Soft-error-immune IEEE T RANSACTIONS ON P OWER E LECTRONICS and the IEEE J OURNAL
read-stability-improved SRAM for multi-node upset tolerance in space OF S OLID -S TATE C IRCUITS .
applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 8,
pp. 3317–3327, Aug. 2021, doi: 10.1109/TCSI.2021.3085516.
[20] S. Lin, Y.-B. Kim, and F. Lombardi, “Design and performance evaluation
of radiation hardened latches for nanoscale CMOS,” IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 19, no. 7, pp. 1315–1319, Jul. 2011,
doi: 10.1109/TVLSI.2010.2047954.

Soumitra Pal (Member, IEEE) received the M.E.

degree in electronics and communication engineer-
ing from the Birla Institute of Technology, Ranchi,
India, in 2015, and the Ph.D. degree in electronic
and computer engineering from The Hong Kong Chi-Ying Tsui (Senior Member, IEEE) received
University of Science and Technology (HKUST), the B.S. degree in electrical engineering from The
Hong Kong, in 2021. University of Hong Kong, Hong Kong, in 1982, and
He is currently a Post-Doctoral Fellow with the the Ph.D. degree in computer engineering from the
Department of Electronic and Computer Engineer- University of Southern California, Los Angeles, CA,
ing, HKUST. He is the author or coauthor of more USA, in 1994.
than 37 research articles, out of which 27 have been In 1994, he joined the Department of Electronic
published in reputed journals (22 in SCI/SCIE/ESCI, including 12 in IEEE and Computer Engineering, The Hong Kong Univer-
T RANSACTIONS /J OURNALS and five in SCOPUS indexed journals), three as sity of Science and Technology, Hong Kong, where
book chapters, and seven in IEEE international conference publications. His he is currently a Full Professor. He has authored
research interests include designing semiconductor memory, power manage- more than 170 referred publications. He holds ten
ment circuits and systems, and wireless power transfer circuits and systems. U.S. patents on power management, VLSI, and multimedia systems. His
Dr. Pal was a recipient of the Graduate Aptitude Test in Engineering (GATE) research interests include designing VLSI architectures for low-power multi-
Scholarship from the All India Council for Technical Education (AICTE), media and wireless applications, developing power management circuits and
Government of India, from 2013 to 2015, and the HKUST Postgraduate techniques for embedded portable devices and ultralow power systems.
Studentship from 2016 to 2021. He received the IET Circuits, Devices & Dr. Tsui received the Best Paper Awards from the IEEE T RANSACTIONS
Systems Premium Award for two consecutive years, 2020 and 2021, and ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS in 1995, the IEEE
the Best Paper Award at the Third International Conference on Information ISCAS in 1999, the IEEE/ACM ISLPED in 2007, the IEEE DELTA in 2008,
System Design and Intelligent Applications in 2016. He has served as a and CODES in 2012. He also received the Design Awards at the IEEE
reviewer for multiple international journals/conferences. ASPDAC University Design Contest in 2004 and 2006.

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