The Ultimate HC Extension Modification Guide SE
(second edition)
1. Introduction:
The HC-90, HC-91 and HC-2000 are arguably the most advanced Romanian “Home Computers” ever built,
considering only two important characteristics: first, the fully synchronous video sequencer, which has RAM access
interleaved with the main CPU (on “Main” board); second, a modern double density floppy disk interface with digital PLL
data window and ROM software (on “Extension” board).
The Extension board also contains another two interfaces for serial and network connections, further called here
communication interfaces. The HC-2000 is mainly identical, but has all circuits on the same single board. This document
presents some very simple modifications which can be made with minimal technical abilities, in the required order: A, B,
C, D, E. Not all these changes are required, one can stop after any modd, but A is prerequisite for B modd, A&B for C,
A&B&C for D and A&B&C&D for E. The changes are easier to make on the HC-90 and HC-91 Extension board, because
there are a lot of unused gates and flip-flops on these, and they are harder to make on the HC-2000, which has fewer
unused resources. Another independent small modd F can be applied to transform the HC-90 and HC-91 extensions to
HC-2000 variant if 2 x 720Ko drives are to be acccessed.
Unfortunately, due to some economic considerations, the decoding of the extension ports is very incomplete,
especially the ports of the communication interfaces. These ports should have only two main I/O addresses: #F7 and #EF.
Instead, they are selected with a negative condition, when (A6A5A4)≠(000). Then, if A3=0 port #F7 is selected and if A4=0
port #EF is selected. The result of such a bad decoding scheme is the complete pollution of the CPU I/O space with
parasithic redundant ports for communication interfaces: almost all normally free odd addresses are occupied with
“avatars” of #F7 and #EF ports. The disk selection ports (#05/#07), the floppy controller ports (#85/#87) and the CPM
memory banking ports (#C5/#C7) are all normally selected without pollution !
2. Modification A: Escape the port pollution nightmare & overlapp mistake !
The ports of communication interfaces can be decoded with minimal redundancy by adding another LS138 decoder
partially soldered on top of the existing one from D9 position (see schematic). Pin7 (output7) of the new decoder must be
wired to Pin10 and Pin12 of D8C and D8D gates, cutting AB0 connection. Then two unused inverters on the Extension
board from positions D4E and D4D must be wired with outputs to Pin4 and Pin5 of the decoder and with inputs to the
nearest A0, respectively A1 address lines. The HC-2000 needs additional LS04 inverter on top of the D4 one.
This simple modification eliminates all the port pollution and the communication ports will be restricted to only 3
addresses: (#F7/#E7) for #F7 and (#EF/#E7) for #EF. Another result is the elimination of the value #EE that must be
loaded when banking video RAM under CPM mode: that was a requirement because the communication ports overlapped
with the (#C5/#C7) ports. Anything can be now placed to the ports, not only the initialization #EE value. That was really
a design mistake of I.C.E. Felix engineers !
3. Modification B: Add nice & easy auto-programmable EEPROM !
The Extension board has a 32Ko EPROM from which only 16Ko is availlable (another waste !). This can be substituted
with a 32Ko EEPROM fully readable and programmable by the system’s CPU, like a slow writing RAM. Much more useful
for little software changes !
Two new integrated circuits are required: a LS174 register partially soldered on top of the C6 one, and a LS32 with
quad OR gates placed over the C8 one. All blue connections from the schematic means vertically soldered pins to the
circuit undersided. Another third existing and unused inverter D4F must be connected in circuit, like in the schematic. Only
¾ OR gates will be used in this B modd. A wire must be connected from the modd A decoder Pin12 (output3) to one of
the OR gates.
Then, at the memory socket, the “Output Enable” Pin22 must be disconnected from ground and connected to RD
signal from CPU; the “Write Enable” Pin27 must be disconnected from VCC and connected to FRWE output of one OR gate;
the “A14” Pin1 must be connected to the Q0 Pin2 of the new LS174 to enable software controlled EEPROM pagging.
This modification adds a quad selected hardware port at main address #7F, with redundant selections at
#67/#6F/#77. All adresses are safe and carefully chosen not to overlapp with any known Spectrum compatible peripherals.
The new port allows selection of the EEPROM’s first or second 16Ko pages, the required write protection (if not protected,
the EEPROM cannot be read after the first write !) and the “auto-disconnect” feature for freeing the port in the I.C.E. Felix
style from the HC Mainboard.
4. Modification C: Add predictable software pagging mechanism !
The original Extension has a hardware pagging mechanism which maps the Extension ROM instead of the Mainboard
ROM when the CPU fetches any instruction from the memory address interval #0008..#000F or #1708..#170F and maps
back the Mainboard ROM when the CPU fetches an instruction from the address interval #0700..#0707 (it is an interval
because the address lines A2A1A0 are not decoded !). Of course this mechanism is nice, but there are many new operating
systems that want a predictable software pagging mechanism instead. Why not having both ?!
To add software pagging of ROMs, only one new LS157 multiplexer is needed after the B modd. The best location to
place it, is on top over the D6 flip-flops, because there will be mostly connected, maximizing the direcly underneat soldered
pins. Pin5 from D6A flip-flop must be cut from the PHANTOM connection and routed through the new multiplexer. The
selection is done with the Q2 Pin7 of the LS174 register from B modd: when this is “0”, the multiplexer re-connects the
PHANTOM output back to the D6A flip-flop, enabling the hardware pagging; when the bit is “1”, the PHANTOM pagging
becomes software controlled through output Q1 Pin5 of the register.
Another useful change is to completely eliminate one of the two diodes from the “ROMDisable” signal, which is
already absent on HC-2000 and can mantain the ROM present at address #0000 after an OUT to port #C7 from BASIC.
This modification enables all sort of tricks with EEPROM pagging under program control; only think that one of the
two 16Ko pages of the EEPROM can be loaded with anything else !
5. Modification D: Add SRAM banked with “no matter what” OUT !
If all the previous changes were made, is worth to add another 32Ko SRAM soldered on top of the existing EEPROM,
to load all kind of dual-banked operating systems (like the one from IF1-BIS for hard disk), Cobra’s good Opus or any
other computer’s ROM. The SRAM pins must be soldered vertically to the EEPROM pins, with only two exceptions, that
must be brought horizontally and connected elsewhere: the “Chip Enable” Pin20 must be connected to 2 x 1N4148 diodes
placed vertically on the decoder C9 together with a resistor to VCC; the address A14 Pin1 should be connected to an
unused existing flip-flop D3B, with clock controlled by the modd A decoder Pin13 (output2), through the fourth unused
modd B OR gate. The two diodes and the resistor form a logical OR function (active low), to maintain the same SRAM
selection for all the 16Ko address interval, instead of both the EEPROM and 1Ko Phantom RAM.
To enable switching between EEPROM and SRAM, the Pin3 of the C9 decoder must be cut from the ground and
connected to the Q3 Pin10 output of the LS174 register.
This modification adds another 4 ports to the system: (#57/#47) and (#5F/#4F). An OUT (#57) selects the lower
16Ko and an OUT (#5F) selects the higher half of the SRAM. Doesn’t matter at all what is put to the ports, so no register
must be altered for bank change (IF1-BIS compatible switching) !
6. Modification E: Add full EEPROM access option for other ROMs !
The electrically reprogrammable EEPROM memory added with the modification B is not fully accessible, due to the
selection of the Extension scratchpad Phantom RAM over the primary address space #2800-#2FFF and the redundant one
at #3800-#3FFF (the 1Ko RAM appears redundant four times there). This restriction has two negative consequences. First,
if the EEPROM software write protection mechanism is enabled (in an external programmer), the memory can no longer
be re-programmed in the system, because the disable sequence needs access to address #2AAA in the lower 16K page
which maps to the 4 x 1K Phantom RAM instead. Of course, software protection cannnot be accidentally activated in the
system either if it was initially inactive, because the same address must be used in that case too. Thus, if the software
protection was initially inactive when the EEPROM was installed in the system, the modification B works fine and the
memory can be re-programmed directly in the system.
The second negative consequence of the Phantom RAM mapping is partial acccess to ROM space, so it cannot be
really used to install other full operating systems such as OPUS or other Spectrum compatible ROMs: they can only be
dinamically loaded from the discs into the 32Ko SRAM added with the modification D. Of course, the first 16Ko section of
the Extension EEPROM houses the IF1 compatible ROM which must be kept intact, but the second 16Ko page is free and
cannot be used in its entirety for any additional full ROMs.
If all hardware changes A, B, C, D have already been made, is it really easy to add full acccess to EEPROM space as
an option to alleviate the restrictions mentioned above, using only two minor components: a resistor and a diode. The
idea behind this change is to use the 32Ko SRAM paging ports #57 and #5F from D modd to enable or disable the 1Ko
Phantom RAM mapping over the EEPROM, since these ports have no effect on the 32Ko SRAM when it has not been
selected in the address space #0000-#3FFF.
The direct connection from Pin11 of AND gate D7D to Pin1 of memory decoder C9 must be cut in a suitable position
and an 1K resistor inserted to restore the connection, but allowing it to be forced to another logic value from elsewhere.
Next, an 1N4148 diode should be soldered with the anode to Pin1 of the C9 decoder and the cathode wired to Pin8
(inverted output) of the flip-flop D3B, which was used in modification D. When this flip-flop switches its inverted output
to “0” (after any output to port #5F), it will force the decoder to select only EEPROM in the entire address space, disabling
Phantom RAM access. The default value “1” (after reset or any output to port #57) will not pass through the diode, allowing
the decoder to be controlled by the AND gate through the resistor, with Phantom RAM mapped over EEPROM, as normal.
When 32Ko SRAM from the modd D is selected instead the EEPROM, these ports return to their normal operation: selecting
one of the two 16Ko SRAM pages.
The picture on the next page shows the top side of the Extension board without the E modd, also highlighting the
NMI button (mounted here on the Extension, but part of the HC Mainboard modification guide). The best positions to
solder the resistor and diode are marked with blue arrows. The images presented in introduction have all the modifications
in this guide, including F.
7. Modification F: Transform HC-9x into HC-2000 with 2 x 720Ko drives !
Normally, the HC-90 or HC-91 Extension board cannot access secondary drives with more than 360Ko capacity, but
the HC-2000 can. The proper jumper is simply missing on the HC-9x, but the equivalent logical gate is still present, just
not connected anywhere. To use a 720Ko secondary drive, first the Pin12 and Pin13 of the existing C5D NAND gate with
power open collector must be connected together, then both to Pin10 of the same chip, bypassing the output Pin11 which
must be connected elsewhere.
Then, if the user wants to chose the capacity of the secondary drive (360Ko/720Ko), a jumper socket should be
mounted by drilling the board on the path from Pin11 of C5 to Pin4 of C6 register, which is connected to the CPU D1 line.
But if the user just wants fixed 2 x 720Ko drives configuration, a wire is just enough, without other complications.
NMI
button
8. Schematics:
Legend: black = initial schematics;
blue = components found on board;
red = new components or connections.
Author: Aleodor-Daniel Ioan (PhD computer engineer & MoS physicist)
