Universal Asynchronous
Receiver Transmitter
UART
INTRODUCTION
• Protocol: A set of rules and regulations is called a protocol.
• Different type of protocols are available.
1. Bus protocol: APB,AHB,AXI,ASB,ACE
2. Peripheral protocol.
• High speed: PCIe, SATA, SAS, Ethernet, USB, MIPI.
• Low speed :UART,SPI,I2C
Cont.
• One of the biggest challenge in SOC design is the on
chip communication between the different components.
• The different bus protocols used for interconnection .
• Most of the times, the IP cores are designed with many
different interfaces and communication protocols and this can
be a problem while integrating into an SOC.
• To avoid this problem, standard on-chip bus structures and
protocols were developed.
Cont.
• Exchange of information from one system to another system
with a medium is called communication.
• A set of rules and regulations that allow two electronic
devices to connect to exchange the data with one and
another.
• Universal asynchronous receiver-transmitter (UART) is one of
the simplest and oldest forms of device-to-device digital
communication.
• You can find UART devices as a part of integrated circuits (ICs)
or as individual components.
UART
• UART stands for a universal asynchronous transmitter and
receiver.
• UART Protocols is a serial communication with two wired
protocols.
• The data cable signal lines are labelled as Rx and Tx.
• Serial communication is commonly used for transmitting and
receiving the signal.
• It is transferred and receives the data serially bit by bit
without class pulses.
• The UART takes bytes of data and sends the individual bits in a
sequential manner.
Cont.
• UART is a half-duplex protocol.
• Half-duplex means transferring and receiving the data but not
at the same time.
• It uses a single data line for transmitting and receiving the
data. It has one start bit, 8-bit data and one-stop bit mean the
8-bit data transfer one’s signal is high to low.
• UART Protocol Data Flow
UART Communication
Cont.
• Two UARTs communicate directly with each other.
• The transmitting UART converts parallel data from a
controlling device like a CPU into serial form.
• Transmitting it in serial to the receiving UART
• Receiver UART then converts the serial data back into parallel
data for the receiving device.
• Only two wires are needed to transmit data between two
UARTs.
• Data flows from TX pin of the transmitting UART to the Rx pin
of the receiving UART.
Cont.
• UART transmit data asynchronously, which
means there is no need to transmit clock
signal with the transmitted data.
• Instead of clock, the transmitter transmit data with some
special bits to synchronize the sending and receiving units.
• These bits define the beginning and end of the data packet so
the receiving UART knows when to start and stop reading the
bits.
• These special bits are:
• Start bit, Priority bit, Stop bit
Cont.
• START BIT: When a word is given to UART for asynchronous
transmission, a bit called “START BIT” is added to the
beginning of each word that is to be transmitted.
• The start bit is used to alert the receiver that a word of data is
about to sent, and to force the clock in the receiver into
synchronization with the clock in the transmitter.
Cont.
• DATA BIT:-
• After the start bit, the individual bits of data are sent, with the
least significant. Bit (LSB) being sent first.
• Each bit in the transmission is transmitted for exactly the
same amount of time as all of the other bits.
• And the receiver looks at the wire at approximately halfway
through the period assigned to each bit to determine if the
bit is 1 or 0.
• For example, if it takes 2 second to send each bit, the receiver
will track the
• signal after 1 second has passed.
Cont.
• PARITY BIT
• To remove the problem of loss of some bits during the
transmission of a signal, error correction mechanism must be
added to the transmitted data.
• Parity bit error checking mechanism is one of the simplest
methods to detect
• any error in received data.
• In asynchronous serial communication, a parity bit is added at
the end of data bits to check the number of 1’s.
Cont.
• STOP BIT
• At the end of each data packet, stop bit i.e. 1 is added to
indicate the end of
• one data packet.
• At the receiver end, this stop bit is used to stop the reception
of data.
Working
• The transmitter receives the 8-bit data from input and stores
in some register.
• The transmitter then adds some special bits like start bit, stop
bit and parity bit(if selected) to make the complete data
frame.
• The data frame then sent out serially by the transmitter at
the predefined clock rate (baud rate).
• The receiver is by default at high logic state which indicates
idle state of receiver and keeps looking for the high to low
transition i.e. start bit.
Cont.
• As soon as the start bit is detected, the receiver observe the
start bit for 50% of the receiving baud rate, if it is the receiver
start sampling other data bits at the middle of each bit
otherwise receiver set flag for framing error.
• After detecting the 8 bit data, the receiver then looks for the
parity bit which is generated by the transmitter for the single
bit error detection.
Cont.
• If the parity bit is detected properly, the receiver looks for the
stop bit to stop the reception of data.
• After the successful detection of stop bit the receiver line goes
high logic state to indicate idle state and start looking for the
next start bit.
Verilog implementation
• This project is divided into 3 main modules for the easy and
clear understanding and also for the ease in further
development of project.
• Baud_rate_generator
• UART_transmitter
• UART_receiver
• These 3 module are further divided into sub modules.
• All the modules are connected by instantiating each module
in the main module
Block diagram
Baud_rate_generator
• Baud rate generator determines transmission speed in
asynchronous communication.
• It is the number of symbols per second transferred.
• Each bit is 1/(baud rate) wide.
• Baud rate=clock freq./(16 X divisor).
Some standard baud rate:
• 2400
• 9600
• 19200
• 38400
• 115200
UART_transmitter
• This module is further divided into 4 sub modules:-
• TX Controller_fsm: Generates all the necessary signal required
to transmit data at right time
• Parity_generator: Generate parity for the 8 bit input data
• PISO(Parallel In Serial Out):Takes the 8 bit input binary data
and convert it into 1 bit serial data
• Txmux: It is 4x1 Mux to transmit 4 different type of data viz.
start bit, data bit, parity bit and the stop bit
UART_transmitter
Transmitter State Machine
UART_receiver
• This module is further divided into following sub modules:-
• RX_fsm: Generates all the control signals for the UART
receiver.
• Detect start: Ideally the receiver receives
continuous 1, as soon as the 0 is
detected which is done by this module, the reception of data
starts.
• SIPO: Converts serial data into 8 bit parallel data.
Cont.
• Parity checker:Checks the correctness of data by Xoring the
10th received bit with xor value of 8 bit received data
• Stop Bit checker: After the detection of valid parity bit, the
stop bit is detected, if the stop bit is not detected then
reception of data is terminated by setting Stop bit error signal
high.
UART_receiver
Receiver State Machine
