DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS

Design problem normally starts with a word description of input output relation and ends with a circuit
diagram having sequential and combinatorial logic elements. The word description is first converted to a state
transition diagram or Algorithmic State Machine (ASM) chart followed by preparation of state synthesis table.
For flip-flop
flop based implementation, excitation tables are used to generate design equations through Karnaugh
Map. The final circuit diagram is developed from these design equations. In this lecture,
lecture we show how these
techniques can be used in sequential circuit design.
There are two different approaches of state machine design called Moore model and Mealy model. In
Moore model circuit outputs, also called primary outputs are generated solely from secondary outputs or
memory values. In Mealy model circuit inputs, also known as primary inputs combine with memory elements to
generate circuit output. Both the methods
ethods will be discussed in detail.
In general, sequential logic circuit design refers to synchronous clock-triggered
triggered circuit because of its
design and implementation advantages. But there is increasiincreasing attention to asynchronous sequential logic
circuit, as its response is not limited by the clock frequency. But there are too many operational constraints that
make design of asynchronous circuit very complex. Except for time time-critical
critical applications synchronous circuit
always remains a preferred choice for seqsequential logic design.
MODEL SELECTION

Figure 1: (a) Moore model, (b) Mealy model of sequential logic system
There are two distinct models by which a synchronous sequential logic circuit can be designed. In Moore model
(Fig. l(a))) the output depends only on present state and not on input. In Mealy model (Fig. 1(b)), the output is
derived from present state as well as input. The option to include input in output generation logic gives certain
advantage to Mealy model. Usually it re requires less number of states and thereby less hardware to solve any
problem. Also, the output is generated one clock cycle earlier. However, there is one important disadvantage
associated with such circuit. The input transients, glitches etc. (if any) are directly conveyed to the output. Also
if we want output transitions to be synchronized while input can change any time Mealy model is not preferred.
In Moore model, the output remains stable over entire clock period and changes only when there occurs a state
change at clock trigger based on input available at that time.
We shall also discuss the conversion from one model to other can be done through state diagram
representation. Depending on application requirements we choose one of these two models or
o a mixed model
where a part of the circuit follows Mealy model and the other Moore model.
We address all design related issues of synchronous sequential logic by solving a binary sequence
detector problem in a step-by-step
step manner. We use both Moore model and Mealy model for this problem and
note the pros and cons of each approach. Note that, any other design problem can be attempted in the same way.
The solution presented in subsequent sections is particular to this problem but the approach is general in nature.
n
The Problem:
Design a sequence detector that receives binary data stream at its input, X and signals when a
combination '011'
11' arrives at the input by making its output, Y high which otherwise remains low. Consider, data
is coming from left, i.e. the first bit to be identified is 1, second 1 and third 0 from the input sequence.
STATE TRANSITION DIAGRAM
The first step in a sequential logic synthesis problem is to convert this word description to State
transition diagram. Let
et us see how we arrive at state transition diagram following Moore and Mealy model.
State Definitions: Moore Model
Since, the output is generated only from the state variables let us see how many of them are necessary.
Let the detector circuit be at state a when initialized. State a can also be considered as one where none of the bit
in input sequence is properly detected or the starting point of detection. Then if 1st bit is detected properly the
circuit should be at a different
erent state say, b. Similarly, we need two more states say, c and d to represent
detection of 2nd and 3rd bit in proper order. When the detector circuit is at state d, output Y is asserted and kept
high as long as circuit remains in stated signaling sequen
sequence
ce detection. For other states detector output, Y=0.
State Transition Diagram: Moore Model
In Moore model each state and output is defined within a circle in state transition diagram in the format
s/Y where s represents a symbol or memory values identified with a state and Y represents the output of the
circuit. An arrow sign marks state transition following an input value 0 or 1 that is written along the path. Note
that X represents the binary data input from which sequence '011' is to be detected.
Figure 2(a) shows the state transition diagram following Moore model.
We arrive at it by following logic. The circuit is initialized with state a. If input
data X = 1, the first bit of the sequence to be detected is considered detected and
the circuit goes to state b. If X = 0 then it remains at state a and checks next bit
that arrives. If at state b, thehe circuit receives X = 1, then first two bit of the
pattern is considered detected and it moves to state c. But at state b, if it
receives X = 0 (i.e., input sequence is '01') then detection has to start afresh as
we need all three bits of' 011' to match. Thus, the detector goes back to initial Figure 2: (a) State
state a. At state c, if the circuit receives X
X= 0 then input bit stream is '011' and the transition diagram of
circuit goes to state d and signals detection of pattern at state d. However, at c if sequence detector: Moore
X = l, the detector is in a situation where
ere it has received '111' in order. It stays at c model
so that if next arriving bit, X = 0 it should signal sequence detection. At state d if the circuit continues sequence
detection job, receiving X = 1 it goes to state b. That ensures detection of '011' second time in input '011011 '.
For X = 0 the circuit goes to initial state a signifying not a single bit has been detected properly subsequent to
previous detection.
State Definitions: Mealy Model
Since, the output can be derived using state as well as input we need three different states for 3-bit 3
sequence detector circuit following Mealy model. The three states say, a, b, c represents none, 1st 1 bit and 2nd
bit detection, respectively.. When the circuit is at state c if the input is as per the pattern the output is generated
in state c itself with proper logic combination of input. Note the difference with Moore model where output is
generated one clock cycle later in state d and also requires one additional state.
State Transition Diagram: Mealy Model
The
he output is written by the side of input along arrow path in the format X/Y: where X and Y represent
input and output, respectively. Fig. 2(b) shows state transition diagram of the problem following Mealy model.
 The circuit is initialized with state a. If it receives input X = 0, it stays at a else
goes to state b that signifies first bit is detected properly. In both the cases output, Y =
0 signifying no detection. At state b, if X = 0, the circuit returns to initial state a, i.e.
no bit in given order is detected and if X = 1, goes to state c, signifying two bits in
order are detected. In both the cases Y = 0. Now when at c, if input received is 0 then
all the three bits of the pattern are received properly and sequence detection can be
signaled through Y = l. Also the circuit goes to initial state a and prepares for a new
set of detection. At state c, if X = 1 then the sequence received is '111 '. An arrival of
0 in next clock can make the detection' tion' 110
110' possible. So, at state c if X = 1 it is
Figure 2: (b) State
considered as two bits, '11' have been detected properly and the circuit remains at state
transition diagram of
c. The output at that time is Y = 0 since sequence is not ffully detected.
sequence detector:
Conversion of Models Mealy model
Conversion between Mealy and
Moore models can take place as shown in
Fig. 3 where, T1, T2, T3 represent paths
leading to state a. The path T4 leads from
state a when input is 1. If input is 0, state a
leads to state b and there are no other paths
reaching b.. The rule of conversion is as
follows. If all the transitions in a Mealy
model to a particular state are associated
with only one type of output then in
corresponding Moore model that outpu output
becomes state output (Fig. 3(a)).). If there is
more than one output in Mealy model we
need as many intermediate state variables,
as shown in Fig. 3(b). In Fig. 3(c) it is
shown how to treat transitions that loop
within a particular state. The reverse of this
is applied in convertingg Moore model to
Mealy model.
As an example, let us look at
equivalence between two models of the
sequence detector problem shown in Fig.
Figure 3: Conversion between Mealy and Moore model
2(a) and Fig. 2(b).. In Mealy model we have
paths leading to state a,, have two different types of outputs. So state a of Mealy model get divided in two as a
and d in Moore model. Since there is a loop in state a itself for one input, conversion rule shown in Fig. 3(c) is
applicable. For other states there is no such conflict and a direct conversion is possible following Fig. 3(a).
3(
Now that we know one model can be obtained from other, i.e. logical equivalence exists between the
two, and thus let the application constraints
ints decide which one is to be chosen for a particular problem.
STATE SYNTHESIS TABLE
The next step in design process is to develop state synthesis table, also called circuit excitation table or
simply state table from state transition diagram. Note that ffor m number of memory elements we can have up to
2m number of different states in a circuit. Once we decide how many memory elements are to be used, we go for
state assignment.
Often, we need to exercise state reduction technique before state assignment to remove redundancy in
state description. Redundancy may come while converting word description of a complex problem to state
transition diagram.
State Assignment
Now, we allocate each state a binary combination of memory values. For the given problem, both Moore
and Mealy models require minimum 2 flip-flops (A and B) to define their states (4 for Moore and 3 for Mealy).
Let the state assignment be as follows: a: B=0, A=0 b: B=0, A=l c: B=l, A=0 d: B=1, A=l
Note that Mealy model does not use state d. Assignment can be done in any order, e.g. we can make a: B = 0, A
= l and b: B = 0, A = 0 and proceed with the design. However, one set of state assignment may give simpler
final logic circuit over other. Though there is no definite state assignment rule that gives minimum hardware for
an implementation, logical adjacency between transition states often helps.
State Synthesis Table
The next design step is to decide what kind of memory elements are to be used for our design. Flip-flops
are commonly used for this purpose. Take a note of the fact that there are different types of them available.
Each flip-flop has a unique characteristic equation and excitation table. In synthesis problem we have to find out
how flip-flop inputs are to be connected and how final output is generated from flip-flop output. For this, we
use state synthesis table that gives the input requirement of all flip-flops for a given state transition diagram.
Before we prepare this table we should decide which flip-flop we are going to use. We nom1ally prefer JK flip-
flop as it has maximum number of don't care states in its excitation table and that leads to simpler design
equations. We design the given sequence detector circuit using JK flip-flops.
Moore Model
State synthesis table obtained from state transition diagram of Moore model (Fig. 2(a)) and excitation
table of JK flip-flop is shown in Table 1. It has eight rows as for each of the four possible states there can be
two different types of inputs. The table is prepared as follows. When the circuit is at state 00, i.e., a, and
receives X = 0 it remains at state 00 and output in this state Y = 0. Since both B and A flip-flop makes 0→0
transition both the flip-flops should have input 0x from excitation table. This way first four columns of the table
(present state, input, next state, output) are filled from state transition diagram and last two columns (B and A
flip-flop inputs) from flip-flop excitation table.
Present State Present Input Next State Output B Flip-Flop A Flip-Flop
Bn An Xn Bn+1 An+1 Yn JB KB JA KA
0 0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 0 x 1 x
0 1 0 0 0 0 0 x x 1
0 1 1 1 0 0 1 x x 1
1 0 0 1 1 0 x 0 1 x
1 0 1 1 0 0 x 0 0 x
1 1 0 0 0 1 x 1 x 1
1 1 1 0 1 1 x 1 x 0
Table 1: State Synthesis Table for Moore Model
Mealy Model
Since, Mealy Model requires three states for this problem we have six rows in state synthesis table as in
each state there can be two different types of input X = 0 or X = 1. Table 2 represents state synthesis table for
Mealy model. The method remains the same as before but we use state transition diagram of Fig. 2(b).
Present State Present Input Next State Output B Flip-Flop
Flip A Flip-Flop
Bn An Xn Bn+1 An+1 Yn JB KB JA KA
0 0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 0 x 1 x
0 1 0 0 0 0 0 x x 1
0 1 1 1 0 0 1 x x 1
1 0 0 0 0 1 x 1 0 x
1 0 1 1 0 0 x 0 0 x
Table 2:: State Synthesis Table for Mealy Model
DESIGN EQUATIONS AND CIRCUIT DIAGRAM
Next,, we discuss how to get final circuit diagram from state synthesis table through design equation. In
design equation we express flip-flop
flop inputs as a function of present state, i.e. memory values (here, B and A)
and present input (here, X). This ensures proper transfer of the circuit to next state. The design equations also
give output (here, Y) equation in term
termss of state variables or memory elements in Moore model and state
variables together with input in Mealy model. We no normally use Karnaugh
augh map technique to get a simplified
form of these relations.
Moore Model
Figure 4(a) presents Karnaugh map developed from state synthesis Table 1 and also shows
corresponding design equations. Figure 44(b) shows the sequence detector circuit diagram developed from these
equations. This is done in the following manner. Equation JB = XA requires J input of flip-flop
fl A to be fed from
a two input AND gate, inputs to which are X and A. The other inputs and output are obtained in similar way.
Note that, output is generated by AND operation on two flip
flip-flop
flop outputs and does not use X.
 Figure 4: (a) Design equations for Moore model, (b) Circuit diagram following Moore model
Mealy Model
Using state synthesis table corresponding to Mealy model (Table 2) we can fill six positions in each
Karnaugh map (Fig. 5(a)). Locations Bn An X = 110 and Bn An X = 111 are filled with don't care (x) conditions as
such a combination never occur in the detector circuit if properly initialized. The design equations are obtained
from these Karnaugh maps from which circuit diagr
diagram is drawn as shown in Fig. 5(b).. Note that
t in this circuit,
output directly uses input information.

Figure 5: (a) Design equations for Me

Mealy model, (b) Circuit diagram following Mealy
Me model
ALGORITHMIC STATE MACHINE
Algorithmic State Machine (ASM) is a flow chart like representation (ASM Chart) of the algorithm a state
machine performs. State Transition diagrams though more compact in representation has certain disadvantages.
For relatively more complex problem where number of inputs and states are higher the state diagram space
becomes so crowded that it is difficult to read. The other advantage of ASM chart is that, it handles
implementation issues with greater ease offering better timing infom1ation. In ASM chart, square boxes
represent a state. If a state generates an unconditional outp
output
ut (Moore model) it can be specified within the
square box. A diamond shaped box represents decision to be taken and normally the variable or the condition
that is tested is placed inside it with a question mark. There are two exit paths of this decision box since the
decision is binary in nature. For Mealy model, oval shaped boxes are used to desc1ibe the output that depends
on present state as well as the present input. Circles are used to denote start, stop of the algorithm and also the
connector point of an ASM chart when it becomes too large and needs to be drawn at more than one place.
Entry and exit of each ASM block is shown by arrow headed connecting link.
Fig. 6 shows the ASM chart of the sequence detector problem following Moore model where X denotes
the input data bit and Y the detector output. Note the similarity between Moore model state transition diagram of
Fig. 2(a) and ASM chart shown here. Once we arrive at the ASM Chart the rest of the design procedure starting
from state assignment up to final circuit diagram is same as what is discussed earlier.
ASM Chart for the Mealy model sequence detector is left as exercise.

Figure 6: ASM chart of sequence detector problem: Moore model

EXAMPLE: A Garage-door Opener
An ASM chart is to be constructed for an automatic garage
garage-door
door opener. Let x be the input signal
resulting from a sensor actuated by a physical switch; the output is z. The value of x toggles when the switch is
activated. The output signal z controls the mechanism that opens and d closes the garage door; z also toggles. A
low-frequency clock synchronizes the system.
Assuming the garage door is closed, when the switch is activated the input becomes 1 and the machine
changes state at the next clock edge.
The next time the switch is activated, the input signal goes to 0. In response to this input the output goes
to 0 at the next clock edge. We seek an ASM chart to describe this system.
The machine has two states: open and closed. An ASM block starting from the closed state is shown in
Figure 7(a).. It does not indicate how this state is reached.
After the “open” input signal is received, the output 1 is emitted. That means the garage door should
open, so the next state is the “open” state.
The next time the switch is actuated, the input toggles (x = 0), and so does the output (z = 0). The
“closed” state is reached when x = 0 while in the open state.
Figure 7(b) shows the completed chart.

Figure 7: ASM chart for a garage-door opener

Vending Machine Problem
The task is to design a synchronous logic control unit of a vending machine. The machine can take only
two types of coins of denomination 1 and 2 in any order. It delivers only one product that is priced Rs. 3. On
receiving Rs. 3 the product is delivered by asserting an output D = 1 which otherwise remains 0. If it gets Rs. 4
then product is delivered by asserting X and also a coin return mechanism is activated by output Y = 1 to return
a Re. 1 coin. There are two sensors to sense the denomination of the coins that give binary output as shown in
the following table. The clock speed is much higher than human response time, i.e. no two coins can be
deposited in same clock cycle.
I J Coin
0 x No coin inserted
1 0 One rupee
1 1 Two rupees
ASM Chart
The ASM chart is prepared following Mealy model and is shown in Fig. 8. The initial state when no
coin is deposited is designated as state a. Note that, sensor output I= 0 indicates no coin is deposited. At every
clock trigger I is tested and if found 0 the circuit retraces its path to state a and obviously none of X and Y is
asserted, i.e. no product is delivered or coin returned. If I= 1, the controller tests J. If J= 0 it goes to state b that
represents Re. 1 is received and if J = l, goes to state c indicating Rs. 2 is received. The controller remains at
state b if no further coin is deposited found by checking I. Now, if I= 1 and J = 0, the machine has received two
Re. 1 coins in succession and should move to state c. But I= 1 and J = I means a Rs. 2 coin is received
following Re. 1 totaling Rs. 3 the cost of the product. Hence, the product is delivered by asserting X = 1 and the
circuit goes to initial state. At state c if on testing I= I that is a coin is deposited, the controller tests J to
ascertain if it is Re. 1 or Rs. 2. If J = 0, Re. 1 is deposited and a total of Rs. 3 is received. The product is
delivered by X =1 and the circuit goes to initial state a. Now if J = 1 then Rs. 2 is received totaling Rs. 4. Then
Re. 1 is returned by asserting Y = 1, also the product is delivered through X = l and the controller moves to
initial state a.
State Assignment and State Synthesis Table
The subsequent design steps are same as state transition diagram based method discussed before. We
prepare state table from this ASM Chart. In this example we show how to use D flip-flop as the memory
element though JK flip-flop can also be used. As expected, filling up of columns that corresponds to D input in
a given state is easier than JK flip-flop, also the number of Karnaugh map to be drawn for each flip-flop is half
that of JK flip-flop as D flip-flop has only one data input. But all these come at a cost of increased hardware
complexity. This example will highlight this aspect of design issue for synchronous sequential circuit. The state
assignment is done as follows. Since there are three different states we need two flip-flops (say, B and A) to
represent them. Let BA= 00 represent state a, BA= 01 state b, BA= 10 state c. State BA= 11 is not used in this
problem. Table 3 shows the state table corresponding to ASM chart shown in Fig. 8 and also the D inputs
corresponding to every state.
Design Equations from Karnaugh map and Circuit Diagram
Karnaugh maps for each flip-flop input and both the outputs are shown in Fig. 9(a) along with design
equations. Note that for BA = 11 we have don’t care states in each map that helps in minimizing design
equation. The final digital controller circuit for the vending machine problem is shown in Fig. 9(b).
The diagram can easily be drawn from ASM chart (Fig. 8) and is shown in Fig. 10.
Figure 8: ASM chart for vending machine problem: Mealy model
Present State Input Next State Output D Flip-Flops
Bn An I J Bn+1 An+1 X Y DB DA
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
1 0 0 1 0 0 0 1
1 1 1 0 0 0 1 0
0 0 0 1 0 0 0 1
0 1 0 1 0 0 0 1
0 1
1 0 1 0 0 0 1 0
1 1 0 0 1 0 0 0
0 0 1 0 0 0 1 0
0 1 1 0 0 0 1 0
1 0
1 0 0 0 1 0 0 0
1 1 0 0 1 1 0 0
Table 3: State Synthesis Table for Vending Machine Problem: Mealy Model
Figure 9: (a) Design equation, (b) Circuit diagram for vending machine problem: Mealy model

Figure 9: State transition diagram of vending machine problem

problem: Mealy model