UNIT 5

Finite State Machine

` Finite state machine can be defined as a type of machine whose past histories can affect its
future behavior in a finite number of ways. To clarify, consider for example of binary full adder.
Its output depends on the present input and the carry generated from the previous input. It may
have a large number of previous input histories but they can be divided into two types: (i) Input

The most general model of a sequential circuit has inputs, outputs and internal states. A
sequential circuit is referred to as a finite state machine (FSM). A finite state machine is abstract
model that describes the synchronous sequential machine. The fig. shows the block diagram of a
finite state model. X1, X2,….., Xl, are inputs. Z1, Z2,….,Zm are outputs. Y1,Y2,….Yk are state
variables, and Y1,Y2,….Yk represent the next state.

Capabilities and limitations of finite-state machine

Let a finite state machine have n states. Let a long sequence of input be given to the machine.
The machine will progress starting from its beginning state to the next states according to the
state transitions. However, after some time the input string may be longer than n, the number of
states. As there are only n states in the machine, it must come to a state it was previously been in
and from this phase if the input remains the same the machine will function in a periodically
repeating fashion. From here a conclusion that ‗for a n state machine the output will become
periodic after a number of clock pulses less than equal to n can be drawn. States are memory
elements. As for a finite state machine the number of states is finite, so finite number of memory
elements are required to design a finite state machine.

Limitations:

1. Periodic sequence and limitations of finite states: with n-state machines, we can generate
periodic sequences of n states are smaller than n states. For example, in a 6-state machine,
we can have a maximum periodic sequence as 0,1,2,3,4,5,0,1….

2. No infinite sequence: consider an infinite sequence such that the output is 1 when and
only when the number of inputs received so far is equal to P(P+1)/2 for P=1,2,3….,i.e.,
the desired input-output sequence has the following form:

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 Input: x x x x x x x x x x x x x x x x x x x x x x
Output: 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1

Such an infinite sequence cannot be produced by a finite state machine.

3. Limited memory: the finite state machine has a limited memory and due to limited
memory it cannot produce certain outputs. Consider a binary multiplier circuit for
multiplying two arbitrarily large binary numbers. The memory is not sufficient to store
arbitrarily large partial products resulted during multiplication.
Finite state machines are two types. They differ in the way the output is generate they are:
1. Mealy type model: in this model, the output is a function of the present state and the
present input.
2. Moore type model: in this model, the output is a function of the present state only.

Mathematical representation of synchronous sequential machine:

The relation between the present state S(t), present input X(t), and next state s(t+1) can be
given as
S(t+1)= f{S(t),X(t)}
The value of output Z(t) can be given as
Z(t)= g{S(t),X(t)} for mealy model
Z(t)= G{S(t)} for Moore model
Because, in a mealy machine, the output depends on the present state and input, where as in a
Moore machine, the output depends only on the present state.

Comparison between the Moore machine and mealy machine:

Moore machine mealy machine

1. its output is a function of present 1. its output is a function of present state
state only Z(t)= g{S(t)} as well as present input Z(t)=g{S(t),X(t)}
2. input changes do not affect the 2. input changes may affect the output of
output the circuit
3. it requires more number of states 3. it requires less number of states for
for implementing same function implementing same function

Mealy model:

When the output of the sequential circuit depends on the both the present state of the flip-flops
and on the inputs, the sequential circuit is referred to as mealy circuit or mealy machine.
The fig. shows the logic diagram of the mealy model. Notice that the output depends up on the
present state as well as the present inputs. We can easily realize that changes in the input during
the clock pulse cannot affect the state of the flip-flop. They can affect the output of the circuit. If
the input variations are not synchronized with a clock, he derived output will also not be
synchronized with the clock and we get false output. The false outputs can be eliminated by
allowing input to change only at the active transition of the clock.

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 Fig: logic diagram of a mealy model

The behavior of a clocked sequential circuit can be described algebraically by means of state
equations. A state equation specifies the next state as a function of the present state and inputs.
The mealy model shown in fig. consists of two D flip-flops, an input x and an output z. since the
D input of a flip-flop determines the value of the next state, the state equations for the model can
be written as
Y1 (t+1)=y1(t)x(t)+y2(t)x(t)
Y2(t+1)= 𝑦1(t)x(t)

And the output equation is

Z(t)={ y1(t)+y2(t)} X‘(t)
Where y(t+1) is the next state of the flip-flop one clock edge later, x(t) is the present input, and
z(t) is the present output. If y1(t+1) are represented by y1(t) and y2(t) , in more compact form,
the equations are
Y1(t+1)=y1=y1x+y2x
Y2(t+1)=y2=y1‘x
Z=(y1+y2)x‘

The stable table of the mealy model based on the above state equations and output equation is
shown in fig. the state diagram based on the state table is shown in fig.

In general form, the mealy circuit can be represented with its block schematic as shown in below
fig.

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Moore model: when the output of the sequential circuit depends up only on the present state of
the flip-flop, the sequential circuit is referred as to as the Moore circuit or the Moore machine.
Notice that the output depend only on the present state. It does not depend upon the input at
all. The input is used only to determine the inputs of flip-flops. It is not used to determine the
output. The circuit shown has two T flip-flops, one input x, and one output z. it can be described
algebraically by two input equations an output equation.
T1=y2x
T2=x
Z=y1y2

The characteristic equation of a T-flip-flop is

Q(t+1)=TQ‘+T‘Q
The values for the next state can be derived from the state equations by substituting T1 and T2 in
the characteristic equation yielding
Y1(t+1)=Y1=(y2x) =(𝑦2𝑥)y1+(y2x)𝑦1𝑥
= y1 𝑦2+ y1𝑥 + 𝑦1y2x
= y2 (t+1)= y2= x 𝑦2+𝑥 y2

The state table of the Moore model based on the above state equations and output equation is
shown in fig.

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In general form , the Moore circuit can be represented with its block schematic as shown in
below fig.

Figure: moore circuit model:

Figure: moore circuit model with an output decoder

Finite state machine-definitions:

Consider the state diagram of a finite state machine shown in fig. it is five-state machine with
one input variable and one output variable.

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Successor: looking at the state diagram when present state is A and input is 1, the next state is D.
this condition is specified as D is the successor of A. similarly we can say that A is the 1
successor of B, and C,D is the 11 successor of B and C, C is the 00 successor of A and D, D is
the 000 successor of A,E, is the 10 successor of A or 0000 successor of A and so on.

Terminal state: looking at the state diagram , we observe that no such input sequence exists
which can take the sequential machine out of state E and thus state E is said to be a terminal
state.

Strongly-connected machine: in sequential machines many times certain subsets of states may
not be reachable from other subsets of states. Even if the machine does not contain any terminal
state. If for every pair of states si, sj, of a sequential machine there exists an input sequence which
takes the machine M from si to sj, then the sequential machine is said to be strongly connected.

State equivalence and machine minimization:

In realizing the logic diagram from a stat table or state diagram many times we come across
redundant states. Redundant states are states whose functions can be accomplished by other
states. The elimination of redundant states reduces the total number of states of the machines
which in turn results in reduction of the number of flip-flops and logic gates, reducing the cost of
the final circuit.
Two states are said to be equivalent. When two states are equivalent, one of them can be
removed without altering the input output relationship.

State equivalence theorem: it states that two states s1, and s2 are equivalent if for every possible
input sequence applied. The machine goes to the same next state and generates the same output.
That is
If S1(t+1)= s2(t+1) and z1=z2, then s1=s2

distinguishable states and distinguishing sequences:

Two states sa, and sb of a sequential machine are distinguishable, if and only if there exists at
least one finite input sequence which when applied to the sequential machine causes different
outputs sequences depending on weather sa or sb is the initial state.
Consider states A and B in the state table, when input X=0, their outputs are 0 and 1
respectively and therefore, states A and B are called 1-distinguishabke. Now consider states A
and E . the output sequence is as follows.

X=0 A C,0 and E D, 0 ; outputs are the same

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 C E,0 and D b,1 ; outputs are different

Here the outputs are different after 2-state transition and hence states A and E are 2-
distungishable. Again consider states A and C . the output sequence is as follows:

X=0 A C,0 and C E, 0; outputs are the same

C E,0 and E D,0 ; outputs are the

same E D,0 and D B,1 ; outputs are

different

Here the outputs are different after 3- transition and hence states A and B are 3-distuingshable.
the concept of K- distuingshable leads directly to the definition of K-equivalence. States that are
not K-distinguishable are said to be K-equivalent.

Truth table for Distunigshable states:

PS NS,Z
X=0 X=1
A C,0 F,0
B D,1 F,0
C E,0 B,0
D B,1 E,0
E D,0 B,0
F D,1 B,0
State Minimization:
Completely Specified Machines

• Two states, si and sj of machine M are distinguishable if and only if there exists a finite
input sequence which when applied to M causes different output sequences depending on
whether M started in si or sj.
• Such a sequence is called a distinguishing sequence for (si, sj).
• If there exists a distinguishing sequence of length k for (si, sj), they are said to be k-
distinguishable.
EXAMPLE:

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• states A and B are 1-distinguishable, since a 1 input applied to A yields an output 1,
versus an output 0 from B.
• states A and E are 3-distinguishable, since input sequence 111 applied to A yields output
100, versus an output 101 from E.
• States si and sj (si ~ sj ) are said to be equivalent iff no distinguishing sequence exists for
(si, sj ).
• If si ~ sj and sj ~ sk, then si ~ sk. So state equivalence is an equivalence relation (i.e. it is a
reflexive, symmetric and transitive relation).
• An equivalence relation partitions the elements of a set into equivalence classes.
• Property: If si ~sj, their corresponding X-successors, for all inputs X, are also equivalent.
• Procedure: Group states of M so that two states are in the same group iff they are
equivalent (forms a partition of the states).

Completely Specified Machines

Pi : partition using distinguishing sequences of length i.

Partition: Distinguishing Sequence:
P0 = (A B C D E F)
P1 = (A C E)(B D F) x =1
P2 = (A C E)(B D)(F) x =1; x =1
P3 = (A C)(E)(B D)(F) x =1; x =1; x =1
P4 = (A C)(E)(B D)(F)
Algorithm terminates when Pk = PK+1
Outline of state minimization procedure:
• All states equivalent to each other form an equivalence class. These may be combined
into one state in the reduced (quotient) machine.
• Start an initial partition of a single block. Iteratively refine this partition by separating
the 1-distinguishable states, 2-distinguishable states and so on.
• To obtain Pk+1, for each block Bi of Pk, create one block of states that not 1-
distinguishable within Bi , and create different blocks states that are 1-distinguishable
within Bi .
Theorem: The equivalence partition is unique.
Theorem: If two states, si and sj, of machine M are distinguishable, then they are (n-1 )-
distinguishable, where n is the number of states in M.
Definition: Two machines, M1 and M2, are equivalent (M1 ~ M2 ) if, for every state in M1
there is a corresponding equivalent state in M2 and vice versa.

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Theorem. For every machine M there is a minimum machine Mred ~ M. Mred is unique up to
isomorphism.

State Minimization of CSMs: Complexity

Algorithm DFA ~ DFAmin
Input: A finite automaton M = (Q, , , q 0, F ) with no unreachable states.
Output: A minimum finite automaton M‘ = (Q’, , ‘, q ‘0, F’ ).
Method:
1. t :=2; Q0:= { undefined }; Q1:=F; Q2:= Q\F.
2. while there is 0 < i  t, a   with (Qi,a)  Qj, for all j  t
do (a) Choose such an i, a , and j  t with  (Qi,a)  Qj  .
(b) Qt +1 := {q  Qi |  (q,a)  Qj };
Qi := Qi \ Qt +1;
t := t +1.
end.
3. (* Denote [q ] the equivalence class of state q , and {Qi } the set of all equivalence
classes. *)
Q’ := {Q1, Q2, ..., Qt }.
q ‘0 := [q0].
F’ := { [q]  Q’ | q  F }.
 ’ ( [q], a) := [(q,a)] for all q  Q, a  .

Standard implementation: O (kn 2), where n =|Q| and k = ||

Modification of the body of the while loop:
1. Choose such an i, a  , and choose j1,j2  t with j1  j2,  (Qi,a)  Qj1  , and 
(Qi,a)  Qj2  .
2. If |{q  Qi | (q,a)  Qj1}|  |{q  Qi | (q,a)  Qj2}|

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 then Qt +1 := {q  Qi | (q,a)  Qj1 }
else Qt +1 := {q  Qi | (q,a)  Qj2 } fI;
Qi := Qi \ Qt+1;
t := t +1.
(i.e. put smallest set in t +1 )
Note: |Qt +1|  1/2|Qi|. Therefore, for all q  Q, the name of the class which contains a given
state q changes at most log(n ) times.
Goal: Develop an implementation such that all computations can be assigned to transitions
containing a state for which the name of the corresponding class is changed.
Suitable data structures achieve an O (kn log n) implementation.

State Minimization:
Incompletely Specified Machines
Statement of the problem: given an incompletely specified machine M, find a machine M’
such that:
– on any input sequence, M’ produces the same outputs as M, whenever M is
specified.
– there does not exist a machine M’’ with fewer states than M’ which has the same
property

Machine M:

Attempt to reduce this case to usual state minimization of completely specified machines.

• Brute Force Method: Force the don‘t cares to all their possible values and choose the
smallest of the completely specified machines so obtained.
• In this example, it means to state minimize two completely specified machines obtained
from M, by setting the don‘t care to either 0 and 1.

Suppose that the - is set to be a 0.

• States s1 and s2 are equivalent if s3 and s2 are equivalent, but s3 and s2 assert different
outputs under input 0, so s1 and s2 are not equivalent.
• States s1 and s3 are not equivalent either.

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 • So this completely specified machine cannot be reduced further (3 states is the
minimum).
Suppose that the - is set to be a 1.

• States s1 is incompatible with both s2 and s3.

• States s3 and s2 are equivalent.
• So number of states is reduced from 3 to 2.

Machine M’’red :

Can this always be done?

Machine M:

Machine M2 and M3 are formed by filling in the unspecified entry in M with 0 and 1,
respectively.

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Both machines M2 and M3 cannot be reduced.
Conclusion?: M cannot be minimized further!
But is it a correct conclusion?
Note: that we want to ‗merge‘ two states when, for any input sequence, they generate the same
output sequence, but only where both outputs are specified.
Definition: A set of states is compatible if they agree on the outputs where they are all specified.
Machine M’’ :

In this case we have two compatible sets: A = (s1, s2) and B = (s3, s2). A reduced machine Mred
can be built as follows.
Machine Mred

A set of compatibles that cover all states is: (s3s6), (s4s6), (s1s6), (s4s5), (s2s5).
But (s3s6) requires (s4s6),
(s4s6) requires(s4s5), (s4s5) requires (s1s5),
(s1s6) requires (s1s2), (s1s2) requires (s3s6),
(s2s5) requires (s1s2).
So, this selection of compatibles requires too many other compatibles...

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 • Another set of compatibles that covers all states is (s1s2s5), (s3s6), (s4s5).
• But (s1s2s5) requires (s3s6) (s3s6) requires (s4s6)
• (s4s6) requires (s4s5) (s4s5) requires (s1s5).
• So must select also (s4s6) and (s1s5).
• Selection of minimum set is a binate covering problem

When a next state is unspecified, the future behavior of the machine is unpredictable. This
suggests the definition of admissible input sequence.
Definition. An input sequence is admissible, for a starting state of a machine if no unspecified
next state is encountered, except possibly at the final step.
Definition. State si of machine M1 is said to cover, or contain, state sj of M2 provided
1. every input sequence admissible to sj is also admissible to si , and
2. its application to both M1 and M2 (initially is si and sj, respectively) results in
identical output sequences whenever the outputs of M2 are specified.

Definition. Machine M1 is said to cover machine M2 if for every state sj in M2, there is a
corresponding state si in M1 such that si covers sj.

Merger Chart Methods:

Merger graphs:

The merger graph is a state reducing tool used to reduce states in the incompletely specified
machine. The merger graph is defined as follows.
1. Each state in the state table is represented by a vertex in the merger graph. So it contains
the same number of vertices as the state table contains states.
2. Each compatible state pair is indicated by an unbroken line draw between the two state
vertices
3. Every potentially compatible state pair with non-conflicting outputs but with different
next states is connected by a broken line. The implied states are written in theline break
between the two potentially compatible states.
4. If two states are incompatible no connecting line is drawn.

Consider a state table of an incompletely specified machine shown in fig. the corresponding
merger graph shown in fig.

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 State table:

PS NS,Z
I1 I2 I3 I4
A … E,1 B,1 ….
B … D,1 … F,1
C F,1 … … …
D … … C,1 …
E C,0 … A,0 F,1
F D,0 A,1 B,0 …

a) Merger graph b) Simplified merger graph

States A and B have non-conflicting outputs, but the successor under input I2are compatible only
if implied states D and E are compatible. So, draw a broken line from A to B with DE written in
between states A and C are compatible because the next states and output entries of states A and
C are not conflicting. Therefore, a line is drawn between nodes A and C. states A and D have
non-conflicting outputs but the successor under input I3 are B and C. hence join A and D by a
broken line with BC entered In between.

Two states are said to be incompatible if no line is drawn between them. If implied states are
incompatible, they are crossed and the corresponding line is ignored. Like, implied states D and
E are incompatible, so states A and B are also incompatible. Next, it is necessary to check
whether the incompatibility of A and B does not invalidate any other broken line. Observe that
states E and F also become incompatible because the implied pair AB is incompatible. The
broken lines which remain in the graph after all the implied pairs have been verified to be
compatible are regarded as complete lines.
After checking all possibilities of incompatibility, the merger graph gives the following seven
compatible pairs.

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These compatible pairs are further checked for further compatibility. For example, pairs
(B,C)(B,D)(C,D) are compatible. So (B, C, D) is also compatible. Also pairs (A,c)(A,D)(C,D)
are compatible. So (A,C,D) is also compatible. . In this way the entire set of compatibles of
sequential machine can be generated from its compatible pairs.
To find the minimal set of compatibles for state reduction, it is useful to find what are called the
maximal compatibles. A set of compatibles state pairs is said to be maximal, if it is not
completely covered by any other set of compatible state pairs. The maximum compatible can be
found by looking at the merger graph for polygons which are not contained within any higher
order complete polygons. For example only triangles (A, C,D) and (B,C,D) are of higher order.
The set of maximal compatibles for this sequential machine given as

Example:

Merger Table:

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 Figure: state table

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