A Project Report on

Design & Analysis of Dynamic Comparators with

Offset Calibration

For the partial fulfilment of the degree of

M. Tech. in VLSI Design
By
Sumit Kumar Jaiswal
Roll number: 325417015
Registration number: 325417015 of 2017-18

Under the supervision of

Dr. Kasturi Ghosh

SCHOOL OF VLSI TECHNOLOGY

INDIAN INSTITUTE OF ENGINEERING SCIENCE AND
TECHNOLOGY, SHIBPUR
May, 2019
 SCHOOL OF VLSI TECHNOLOGY
INDIAN INSTITUTE OF ENGINEERING SCIENCE AND
TECHNOLOGY, SHIBPUR, HOWRAH-711103

CERTIFICATE
This is to certify that the project entitled “Design & Analysis of Dynamic Comparators with
Offset Calibration” which is being submitted by Sumit Kumar Jaiswal bearing examination
roll number: 325417015 in partial fulfilment of the criterion for the Master of Technology
coursework, has been carried out by him under our supervision and guidance.

Dr. Kasturi Ghosh Prof. Jaya Sil

Supervisor & Asst. Professor, Head of Department,
School of VLSI Technology, School of VLSI Technology,
IIEST Shibpur IIEST Shibpur

Prof. Susanta Chakraborty External Examiners………………

Dean (Academic Affairs),
IIEST Shibpur
 ACKNOWLEDGEMENT

I would like to take this opportunity to express my heartiest gratitude and deepest
regards to my project guide Dr. Kasturi Ghosh for her valuable guidance, constant support and
inspiration throughout the course of the project. It has been a worthwhile experience being
mentored by her.

I am highly obliged to my Head of Department, Prof. Jaya Sil for creating such a
wonderful environment to work and successfully progress with the project and also allowing
me to use the university equipment as and when required. I am very thankful to Prof. Hafizur
Rahaman for providing me the opportunity to work in SMDP project and providing constant
support for my project work whenever deemed necessary.

I am very grateful to Mr. Subhajit Das for showering his invaluable knowledge on me.
I will take this opportunity to thank research scholars especially Supriyo Srimani for providing
me with significant suggestions for my project work whenever deemed necessary.

Lastly and most importantly, I would like to thank my parents for their immense
contribution in my life and also for their constant encouragement for the completion of this
work.

Regards,
DATE:

PLACE: IIEST Shibpur (SUMIT KUMAR JAISWAL)

 CONTENTS
CHAPTERS PAGE NO.

LIST OF FIGURES ……………………………………………………………………… iv

ABSTRACT ………………………………………………………………………………. vi

1. Introduction
1.1 Motivation …………………………………………………………...… 1
1.2 Thesis organization ………………………………………………...….. 3
2. Literature Review
2.1 Design Considerations for Voltage Comparator ………………………. 4
2.2 Parameters of Comparator
2.2.1 Gain …………………………………………………….. 5
2.2.2 Input Offset Voltage ……………………………………. 6
2.2.3 Delay ……………………………………………………. 6
2.2.4 Resolution ………………………………………………. 6
2.2.5 Clock Frequency ………………………………………... 7
2.2.6 Power Dissipation ………………………………………. 7
2.2.7 Kickback Noise …………………………………………. 7
2.3 Types of Comparators
2.3.1 Open-Loop Comparators ………………………………... 8
2.3.2 Pre-amplifier Based Latched Comparators …………....... 8
2.3.3 Fully Dynamic Latched Comparators
[Link] Resistor Divider Comparator …………... 10
(or Lewis-Gray Comparator)
[Link] Differential Pair Comparator/ ………...... 12
Latch-type Voltage Sense Amplifier
[Link] Double Tail Dynamic Latch Comparator .13
2.4 Comparator offset calibration …………………………………………. 15
2.5 Background calibration techniques
2.5.1 Offset averaging technique …………………………….. 15
2.5.2 Auto-zeroing technique …………………………………16
2.5.3 Correlated-double sampling technique ………………….17

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 2.5.4 Chopper stabilization technique ………………………...17
2.6 Foreground calibration technique
2.6.1 Threshold tuning technique …………………………… 17
2.6.2 Redundancy technique ………………………………… 17
2.6.3 Digitally controlled trimming technique ………………. 18
3. Fully Dynamic Latched Comparators
3.1 Double Tail Dynamic Latch Comparator
3.1.1 Circuit operation ………………………………………. 19
3.1.2 Design approach ………………………………………. 22
3.1.3 Offset analysis ………………………………………… 22
3.1.4 Post-Layout simulation ……………………………….. 24
4. Offset Voltage Analysis for Dynamic Comparators
4.1 Types of offset voltage ……………………………………………….. 26
4.2 Kickback Noise ………………………………………………………. 29
4.3 Metastability ………………………………………………………….. 31
5. Offset Calibration
5.1 Need of Calibration …………………………………………………... 32
5.2 Calibration technique ………………………………………………… 33
5.3 Calibration logic
5.3.1 Circuit operation ……………………………………… 36
5.3.2 Calibration control logic ……………………………… 38
5.4 Results ………………………………………………………………... 41
5.5 Layouts ………………………………………………………………. 42
5.6 Post-layout simulation results ………………………………………... 44
5.7 A comparative study of results ……………………………………….. 45
6. Dynamic Latch Comparator (PMOS-input type)
6.1 Circuit operation ……………………………………………………… 46
6.2 Design approach ……………………………………………………… 48
6.3 Offset analysis
6.3.1 Offset without calibration ……………………………... 48
6.3.2 Offset after calibration ………………………………… 49
6.4 Layout ………………………………………………………………… 50
6.5 Offset calibration ……………………………………………………... 50
6.6 A comparative study of results ……………………………………...... 51
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 7. Conclusion & Future work
7.1 Conclusion ………………………………………………………….. 53
7.2 Future work...……………………………………………………….. 54

REFERENCES ............................................................................................................... 55

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 LIST OF FIGURES
Figure 2.1: (a) Comparator Circuit symbol (b) Ideal voltage transfer curve of comparator
Figure 2.2: Voltage transfer curve of practical
Figure 2.3: Two-stage open-loop comparator [1]

Figure 2.4: Pre-amplifier based latched comparator [2]

Figure 2.5: Lewis-Gray comparator [3]

Figure 2.6: A typical differential pair comparator [4]

Figure 2.7: Double tail dynamic latch comparator [5]

Figure 3.1: Circuit diagram of double tail dynamic latch comparator

Figure 3.2: Output response of double tail dynamic latch comparator

Figure 3.3: Zoomed view of output response of double tail dynamic latch comparator

Figure 3.4: Monte-Carlo simulation of offset of double tail dynamic latch comparator

Figure 3.5: Layout of double tail dynamic latch comparator

Figure 3.6: Post-Layout offset measurement of double tail dynamic comparator

Figure 3.7: Post-Layout output response of double tail dynamic latch comparator

Figure 4.1: Simplified schematic of the differential input gain stage

Figure 4.2: Kickback noise affecting input nodes

Figure 4.3: Parasitic capacitors of a typical MOS

Figure 4.4: Voltage transfer curve (VTC) of two back-to-back inverters

Figure 5.1: Input differential pair of dynamic comparator with parasitic

Figure 5.2: Input differential pair of dynamic comparator with calibration unit

Figure 5.3: A typical arrangement of charge-pump

Figure 5.4: Circuit diagram of calibration logic

Figure 5.5: Circuit diagram of calibration phase

Figure 5.6(a): Circuit diagram of generation of two non-overlapping clocks

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Figure 5.6(b): Circuit diagram of delay unit

Figure 5.7: Timing diagram of clocks & signals required in calibration phase

Figure 5.8: Circuit diagram of calibration control logic

Figure 5.9: Monte-Carlo simulation of self-calibrated Double Tail Dynamic Latch

comparator

Figure 5.10: Layout of calibration logic without calibration capacitors

Figure 5.11: Layout of calibration control logic

Figure 5.12: Final layout of dynamic comparator with complete calibration block

Figure 5.13: Post-layout simulation of calibrated DTDC

Figure 6.1: Circuit diagram of PMOS-input type dynamic latch comparator

Figure 6.2: Output response of PMOS-input type dynamic latch comparator

Figure 6.3: Monte-Carlo analysis of offset of PMOS-input type comparator

Figure 6.4: Monte-Carlo analysis of offset of PMOS-input type comparator after calibration

Figure 6.5: Layout of PMOS-input type dynamic latch comparator

Figure 6.6: Offset calibration of PMOS-input type dynamic latch comparator

Figure 6.7:Post-layout simulation of offset calibration of PMOS-input type dynamic latch

comparator

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 ABSTRACT

In this paper an overview of comparators are shown based on some parameters like
speed, power, offset etc. Types of dynamic latch comparators are also discussed with their
advantages and disadvantages. A comparative study of both NMOS and PMOS input type
dynamic latch comparators is done with their advantages and disadvantages. As comparators
required for ADC application must have high resolution i.e. the comparators must be able to
sense the input differences in the range of micro-volts. But due to offset in millivolts, this
cannot be achieved. So, it is necessary to compensate the offset so that the comparator can take
correct decision. Therefore, a foreground offset compensation or self-calibration technique is
proposed which can able to eliminate both static as well as dynamic offset voltages. As dynamic
offset is mainly caused by parasitic capacitances mismatch in the internal Di nodes, so these
nodes are targeted to reduce or compensate the offset.

The complete circuit operation of whole calibration block is discussed along with
layouts. Monte-Carlo of calibration technique is also done along with post-layout simulations.
A comparative study of pre-layout and post-layout simulations are also done for different
parameters of both NMOS and PMOS input type dynamic latch comparators. From the results
it is found that PMOS-input type dynamic latch comparators are power efficient and have low
offset but comparatively slower than NMOS-input dynamic latch comparators (DTDC). One
more advantage of PMOS-input type dynamic latch comparator is that it doesn’t require a
common-mode voltage for its operation.

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1 Introduction
1.1 Motivation:

Due to fast-speed, low-power consumption, high-input impedance and full-swing

output, CMOS dynamic latched comparators are very attractive for many applications such as
high-speed Analog-to-Digital Converters (ADCs), Memory Sense Amplifiers and Data
Receivers. They use positive feedback mechanism with one pair of back-to-back cross coupled
inverters (latch) in order to convert a small input-voltage difference to a full-scale digital level
in a short time.

Comparator is the key building block in the design process for ADCs. The comparators
measure the smallest voltage differences in ADCs inputs, resolving the performance and the
precision of any ADCs. An application that requires digital information recovery from analog
signals, such as I/O receivers and radio frequency identification (RFID) memory circuits,
widely uses high performance comparators to amplify a little input voltage to a big voltage
level. Moreover, digital logic circuits can detect these signals within a short period of time.
Therefore, a faster decision making circuit requires high gain and high bandwidth.

However, an input-referred offset voltage, resulting from the device mismatches such
as threshold voltage Vth, current factor β (=μCoxW/L), parasitic node capacitances and output
load capacitance mismatches, limits the accuracy of such comparators. Because of this reason,
the offset voltage is one of the most important design parameters of the latched comparators.

Offset voltage can be reduced by increasing device dimensions. If large devices are
used, a less mismatch can be achieved at the cost of increased delay (due to slow regeneration
time) and increased power dissipation. Consequently, large device dimension leads to
proportional increase in parasitic capacitances. Due to this residual offset as well as kickback
noise will be more. Hence there is a trade-off among device dimensions, delay and offset.

In the literature, various kinds of CMOS comparators can be found. The types of
comparators can be classified largely into three:

 Open-loop Comparators (op-amps without compensation)

 Pre-amplifier Based Latched Comparators
 Fully Dynamic Latched Comparators

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 Comparators could be designed to work continuously (static) or to make decision after
being initiated with a clock signal (dynamic). Dynamic comparators have replaced static
comparators in many applications to minimize power consumption without trading off speed.
In this literature, various kinds of fully dynamic latched comparators will be fully analyzed in
terms of their advantages and disadvantages along with operating principles and experimental
results of the speed, power consumption, and offset voltage at a limited area. Then, a suitable
architecture of Dynamic Latched Comparator is chosen to apply the digital offset calibration
technique.

Latch-type comparators are able to accomplish decisions more rapidly with no static
power dissipation and strong positive feedback. Moreover, latch type comparators can generate
high gain in regeneration mode due to the positive feedback features. However, to design
circuits for low voltage operations capable of decreasing the dynamic range of the inputs and
the corresponding differential processes, the power dissipation in rail-to-rail operations are
often increased.

Consequently, the most vital limitations of the dynamic latch comparator are the
kickback noise generated by coupling of voltage variations in the internal nodes of comparator.
In addition, employing a transmission gate can also induce high transmission currents spikes
at the differential input voltage signals, which affects the performance of dynamic latch
comparator due to random noise, input offset voltages and component mismatch.

As resolution of ADC increases, the minimum offset requirement increases to achieve

high accuracy. For a good ADC design, offset of comparators should be less than at least one
LSB value. Hence to achieve this low target a Calibration Mechanism is necessary to reduce
the offset, as this requirement cannot be achieved by using large device dimensions only.
Therefore a digital offset calibration technique is proposed which can reduce the static as well
as dynamic offset. The idea of calibration is to balance the charging/discharging currents of
internal node parasitic capacitances.

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1.2 Thesis organization
This work provides detailed analysis of dynamic latch comparators (Both PMOS &
NMOS input type) in terms of speed, regeneration time, power dissipation, offset, effect of
parasitic etc. After that a digital offset calibration technique is proposed which efficiently
reduces the static as well as dynamic offset in the range of microvolts without using large
device dimension of comparators. The different chapters of the thesis are organized as follows.

Chapter 2 reviews the important features (design considerations) of voltage comparators,

introduces and classifies popular structures of voltage comparators. It also elaborates different
offset calibration techniques.

Chapter 3 reviews double tail dynamic latch comparator with advantages and disadvantages.

Chapter 4 elaborates causes of offset and its mathematical analysis for dynamic latch
comparators.

Chapter 5 reviews the proposed offset calibration technique applied in double tail dynamic
latch comparator along with the comparison of pre-layout and post-layout simulations with and
without proposed calibration technique.

Chapter 6 reviews PMOS-input type dynamic latch comparator with advantages and
disadvantages. Proposed calibration technique is also applied to reduce the offset.

Chapter 7 concludes the literature with comparative results and discuss some future works.

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2. Literature Review
In this chapter, important features and design considerations of a voltage comparator
will be reviewed. In addition, different kind of comparator architectures will be reviewed after
classifying them into three: Open-loop Comparator, Pre-amplifier Based Latched comparator,
and Fully Dynamic Latched Comparator. Especially, fully dynamic latched comparators will
be analysed in detail.
After that different existing offset calibration techniques will be discussed with their
merits and demerits.

2.1 Design Considerations for Voltage Comparator:

The basic function of a comparator is to compare an analog signal with another analog
signal or reference value and provides output (binary value) based on comparison. Since it is
easier to distribute voltages to a large number of comparators than to distribute currents, most
converters employ voltage comparison. A voltage comparator can be simply regarded as a 1-
bit ADC.

The circuit symbol and ideal and practical voltage transfer functions of a comparator
are shown in Figure 1. As shown in Figure, the ideal comparator outputs VOH (logic high “1”
= VDD) if Vin+ − Vin− > 0 else it outputs VOL (logic low “0” = 0V) since it has infinite gain,
zero offset voltage and zero RMS noise.
However, for a practical comparator shown in Figure , it outputs VOH only if Vin+ −
Vin− > VIH + VOS (+ |Vnoise|) and it outputs VOL only if Vin+ − Vin− < VIL (− |Vnoise|) because
it has a finite gain, non-zero offset voltage and RMS noise (for latched comparators, VIL and
VIH are limited by its sampling (or Clk) frequency due to meta-stability.

Figure 2.1: (a) Comparator Circuit symbol (b) Ideal voltage transfer curve of comparator

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 Figure 2.2: Voltage transfer curve of practical
comparator

Therefore, design considerations for voltage comparators are can be summarized as

high-speed (maximum clock rate fs), accuracy (high-resolution, which is related to gain, offset
voltage RMS and kickback noise, overdrive recovery, and linearity of input capacitance), wide
input common–mode range, low-power consumption, small-area and so on.

2.2 Parameters of Comparators:

2.2.1 Gain:-
The Ideal voltage transfer characteristic of comparator states the way in which the
output makes a transition between VOL and VOH. The output changes states for an input change
of ΔV, where ΔV approaches zero.

𝑉𝑂𝐻 −𝑉𝑂𝐿
𝐺𝑎𝑖𝑛 = 𝐴𝑉 = lim where ∆𝑉 is the input voltage change
∆𝑉⟶0 ∆𝑉

The voltage gain of comparator can be written as the dc transfer curve of a comparator
with finite gain that is an approximation to a comparator circuit. The difference between this
curve and the previous one is the gain, which can be expressed as:
𝑉𝑂𝐻 − 𝑉𝑂𝐿
𝐴𝑉 =
𝑉𝐼𝐻 − 𝑉𝐼𝐿

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 Where VIH and VIL represent the input voltage difference (Vp - Vn) needed to just
saturate the output at its upper and lower limit, respectively. Gain is a very important
characteristic describing comparator operation. It defines the minimum amount of input change
(resolution) necessary to make the output swing between the two binary states. These two
output states are usually defined by the input requirements of the digital circuitry driven by the
comparator output. The voltages VOH and VOL must be adequate to meet the VIH and VIL
requirements of the digital stage.

2.2.2 Input Offset Voltage:-

Input offset voltages can be classified as two types.
1. Static offset &
2. Random offset.

Static offset voltage occurs from the mismatch in µCox and Threshold Voltage (Vth)
and Dynamic offset voltage due to the mismatch in the parasitic capacitances.
The output changes as the input difference crosses zero. If the output did not change
until the input difference reached a value VOS then this difference would be defined as the offset
voltage. This would not be a problem if the offset could be predicted, but it varies randomly
from circuit to circuit for a given design. The sign of the VOS is unknown in polarity and
dynamic in nature.

2.2.3 Delay:-
It is a very important parameter since it is often the speed limitation in the conversion
rate of an ADC converter. Propagation delay or conversion time can be defined as at how much
speed the comparator responds to applied input. In the simple words, delay is the delay between
output and input. It is the time between active edge of clock and comparator output.

2.2.4 Resolution:-
The resolution of a comparator can be defined as the minimum input voltage difference
which can be sensed and a particular output is provided by the comparator. In other words it is

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simply the offset voltage. The resolution depends on the particular application. Generally the
resolution of comparator should be as low as much as possible.

2.2.5 Clock Frequency:-

The clock frequency ‘f’, also called as sampling frequency, is defined as the reciprocal
of the time interval T, i.e.

1
𝑓=
𝑇

The clock frequency has to be equal or greater than twice of the frequency bandwidth
of analog signals. Clock frequency is important in power dissipation of a circuit.

2.2.6 Power Dissipation:-

The power dissipated by comparator is simply the product of the sum of the currents
flowing in the current source with power supply voltage. We were primarily considering high
speed and low voltage. Dynamic comparator power dissipation same as that of digital gates.

2.2.7 Kickback Noise:-

The large voltage variations in the internal nodes of comparator are coupled to the input
(due to gate-drain parasitic capacitance), disturbing the input voltage—this is usually called
kickback noise. With increase in device size, parasitic gets increased proportionally. Hence
kickback noise is more.

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2.3 Types of Comparators
2.3.1 Open-Loop Comparators:
Open-loop, continuous time comparators, shown in figure 2.3, is an operational
amplifier without frequency compensation to obtain the largest possible bandwidth, hence
improving its time response [1]. Since the precise gain and linearity are of no interest in
comparator design, no-compensation does not pose a problem. However, due to its limited
gain-bandwidth product, open-loop comparators are too slow for many applications. One the
other hand, a cascade of open-loop amplifiers usually has a significantly larger gain-bandwidth
product than a single-stage amplifier with the same gain. However, since it costs more area and
power consumption, cascading does not give practical advantages for many applications.

Figure 2.3: Two-stage open-loop comparator [1]

comparator

2.3.2 Pre-amplifier Based Latched Comparators:

A typical pre-amplifier based latched comparator [2] is shown in figure 2.4. The main
advantages of the pre-amplifier based latched comparators are their fast speed and low input
referred latch offset voltage.

Typically pre-amplifier, which consists of one or two stages of an open-loop

comparator, have high gain and it can reduce the input referred latch offset voltage by its gain.

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For example, if a pre-amplifier has gain of 10 V/V and a latch stage has an offset voltage of
50mV, then the input-referred latch offset voltage will be 5 mV. In addition, by using pre-
amplification stage, kickback noise can be considerably reduced (by isolation between the
drains of the differential pair transistors and the regeneration nodes) and meta-stability problem
also can be relaxed.

Figure 2.4: Pre-amplifier based latched comparator [2]

comparator

Latched comparators commonly employ one or two clock signals (Clk and Clkb) to
determine the modes of operation: Track Mode (Reset) & Latch Mode (Evaluation): output is
toggled by using a positive feedback. For the operation of the circuit shown in Figure during
reset phase (Clkb=0V), both complementary output Vout+ and Vout− are reset to GND by reset
(switch) transistor M10 and M11. During evaluation phase (Clkb=VDD), as the reset
transistors are off, the comparison will be performed by a positive feedback from transistor M7
and M9.

This type of comparators offer low kickback noise, relatively large static power
consumption and slow regeneration time. Due to its limited current operation, it is less
attractive. It can be concluded that pre-amplifier based latched comparators, which is a
combination of a pre-amplifier and a latch, offer fast speed and low offset.

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2.3.3 Fully Dynamic Latched Comparators

[Link] Resistor Divider Comparator (or Lewis-Gray Comparator):

Since the input transistor M1 and M2 operate in the triode region and act like voltage
controlled resistors, this comparator is called “Resistive Divider Comparator” [3]. The
advantage of this comparator is its low power consumption (No DC power consumption) and
adjustable threshold voltage (decision level) which is defined as;

W2
Vin(threshold) = ( ) Vref Where; Vin = Vin+ − Vin−
W1

Figure 2.5: Lewis-Gray comparator [3]

During reset phase (Clk=GND),

comparator PMOS reset transistor M9 and M10 charge Out nodes

up to VDD (this makes NMOS transistor M3 and M4 on and the node voltage at VD3,4 discharge
to GND) and input transistor M1 and M2 discharge Di nodes to ground while NMOS transistor
M5 and M6 are off. During evaluation phase (Clk=VDD), as both switch transistor M5 and M6
are on, each node voltage at Di+ and Di− instantly rises up to the certain values, which are
defined as;

rds1on
VDi+ = . Vout− (≈ VDD)
rds1on + rds3,4on + rds5,6on

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 rds2on
VDi− = . Vout+ (≈ VDD)
rds2on + rds3,4on + rds5,6on

Then, each Out nodes voltage starts to discharge from VDD to ground inversely
proportional to the applied input voltage such a way; Vin+↑ → VDi↓ → VGS3↑ → ID3↑ → Vout-↓
→ VGS4↓ → Vout+↑ (→VGS3↑…). With positive feedback operation from the back-to-back
cross-coupled inverter pairs (M7/M3 and M8/M4), one Out node will discharge to GND and
the other Out node will charge up to VDD again and this comparator will finish its comparison.
Since the input transistor M1 and M2 are operated in the linear region during evaluation phase,
the transconductance for those transistors are can be approximately written as;
𝑊1,2
𝑔𝑚1,2 = 𝜇𝑛 𝐶𝑜𝑥 ( ) 𝑉𝑑𝑠1,2
𝐿

Also, because transistor M3 and M4 are operated in the saturation region during
evaluation phase, the transconductance for those transistors are can be written as;

𝑊3,4
𝑔𝑚3,4 = 𝜇𝑛 𝐶𝑜𝑥 ( ) (𝑉𝑔𝑠3,4 − 𝑉𝑡ℎ𝑛 )
𝐿

The transconductance of transistor M3 and M4 is much larger than that of the input
transistor pair; hence the differential voltage gain built between Di nodes from the input
transistor pair is not big enough to overcome an offset voltage caused from such a small
mismatch between transistor M3 and M4 pair. As a result, those transistors are the most critical
mismatch pair in this comparator and needed to be sized big enough to minimize the offset
voltage at the cost of the increased power consumption. Besides, the mismatch between
transistor M5 and M6 pair (which is switches and operated in the linear region) also causes the
considerable input-referred offset voltage. Furthermore, as the common mode voltage Vcm of
the input transistor pair increases, the relative difference between the voltage controlled
resistors (rds1,2) becomes smaller at the same amount of the input voltage difference ΔVin and
this in turn increases the offset voltage.
It can be concluded that despite its advantages such as zero-static power consumption
and adjustable threshold voltage, since Lewis-Gray comparator shows a high offset voltage and
its high offset voltage dependency on a different common mode voltage Vcm, it is only suitable
for low resolution comparison.

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[Link] Differential Pair Comparator/Latch-type Voltage Sense Amplifier:

The comparator shown in figure 2.6 is a typical differential pair based latch comparator
[4]. Two extra switching transistor M10 and M11 are added to improve its characteristics; since
those additional PMOS switch transistors increase the time the input transistor pair M2 and M3
being operated in the saturation region during evaluation phase (Clk=VDD), hence the
amplification from the differential input pair increases.
The operation of the comparator can be simply described as follows. During reset phase
(Clk=GND), Out nodes of the cross-coupled inverters (M6-M9) are reset to VDD through the
reset transistors M4 and M5. During evaluation phase (Clk=VDD), the tail transistor M1 is
turned on at the rising Clk edge. The input transistor pair (M2 and M3) starts to discharge each
Di node voltage with a different time rate proportional to the each applied input voltage from
VDD to 0V.

Figure 2.6: A typical differential pair comparator [4]

comparator
Once either of Di node voltages drops around VDD−Vtn, then the NMOS transistors of
the cross-coupled inverters M6 and M7 turn on and this initiates the positive feedback. Once
either of Out node voltage reaches around VDD−|Vtp|, the PMOS transistors of the inverters
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M2 and M4 also turn on; further enhancing the positive feedback and enabling the regeneration
of a small differential voltage ΔVin to a full swing differential output.
Comparing with Lewis-Gray comparator, this comparator shows faster operation and
less overall offset voltage. However, still its structure which consists of a stack of 4 transistors
requires large voltage headroom; it is problematic in low-voltage deep-submicron CMOS
technologies. Furthermore, in order to increase the drive currents of the latch, it is inevitable to
size up the transistor M1 since this comparator has only one tail transistor M1. If the size of
transistor M1 is increased, the drain currents of both input transistors M2 and M3 will increase
during evaluation phase (Clk=VDD).
This, in turn, means the reduction of the time duration for transistor M2 and M3 being
operated in saturation region because Di nodes discharge from VDD to ground in a very short
period. Consequently, lower amplification of the input voltage difference will be made and
such a small Vth variation from mismatch between transistor M6 and M7 can yield high input-
referred offset. In addition, since it shows the strong dependency on speed and offset voltage
with a different common-mode input voltage Vcm, it is less attractive in applications with wide
common-mode ranges such as ADCs.

[Link] Double Tail Dynamic Latch Comparator:

To mitigate the drawbacks (strong dependency on speed and offset with a different
common-mode input voltage Vcm and problem in low power supply voltage) of the differential
pair comparator, a comparator with separated input-gain stage and output-latch stage is shown
below [5]. Due to this separation, comparator have a lower and more stable offset voltage over
wide common-mode voltage ranges and operate at a lower supply voltage as well.

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 Figure 2.7: Double tail dynamic latch comparator [5]

It is because by controlling the sizes of the tail transistors (M1 and M12) of the input-
comparator

and output-stage such a way that a small tail current for the differential input pair to obtain a
long integration time and a better gm/ID2,3 ratio for a bigger gain (hence, less offset voltage)
and a large tail current for the output latch-stage for fast regeneration, one can get fast speed
and low offset voltage with less dependence on Vcm.

Generally two types of Dynamic latch comparator are there- one is NMOS input type
and other is PMOS input. Both types of architecture will be analysed in detail and calibration
technique will be applied.

2.4 Comparator offset calibration:

Variations could occur during the fabrication process of the metal oxide semiconductor
(MOS) transistors. As a result of these variations, the physical and electrical parameters of two
identical devices placed close to each other on an integrated circuits show random variations
that result in device mismatches. These random parameter mismatches lead to random DC
offsets in dynamic latched comparators. In addition to the static transistor mismatches, dynamic
comparators suffer from dynamic mismatches due to imbalance of parasitic capacitances

14 | P a g e
between the internal nodes during operation. Therefore, they often exhibit larger offsets when
compared to their static counterparts.

Both static and dynamic mismatches of transistors affect the offset performance, more
severely in deep-submicron CMOS processes, and they cannot be removed by layout design
techniques. It was reported that capacitive imbalance of only a few Femto Farad (fF) can lead
to several tens of millivolts of offset in a typical 0.18 µm CMOS dynamic latch. A detailed
mathematical derivation of mismatch and sensitivity for latched comparators can be found later
in the literature. As a result of random comparator offset, some ADC topologies that utilize
multiple comparators suffer direct degradation of their performance parameters including
differential nonlinearity (DNL), integral nonlinearity (INL), and signal-to-noise and distortion
ratio (SNDR). Therefore, offset correction is critical in data converter designs.

The offset calibration techniques can be categorized into two fundamental classes;
Background and Foreground [6].

2.5 Background calibration techniques

In background calibration, the calibration is done during the regular operation and
calibration values need to be determined periodically. It could be used for correcting both static
and dynamic offsets in comparators. They require extra clock cycles to determine correction
words for each comparison cycle which limit their use in low-speed applications. Widely used
background calibration techniques include offset averaging, auto-zeroing, correlated-double
sampling (CDS), and chopper stabilization techniques.

2.5.1 Offset averaging technique:-

Offset averaging technique is commonly used in flash ADCs where lateral resistors
between the outputs of adjacent preamplifiers and the comparators are used. This technique
causes speed degradation due to the extra parasitic loading of nodes by the averaging resistors.
Moreover, it is not suitable for correcting large offsets.

2.5.2 Auto-zeroing technique:-

In auto-zeroing technique, the comparator offset is sampled by switched capacitors at

input or output side of the comparator and subtracted from the signal, cancelling the offset
before the next clock cycle. One disadvantage of this technique is that it needs several switched
capacitors which limit the sampling rate and bandwidth. Moreover, it can be used only with

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clocked comparators. Offset sampling techniques introduce additional capacitance on the
signal path. They also cannot cancel the offset voltages of latched comparators completely.
Because the cancellation is limited by the charge-injection or clock-feed through mismatches
of the MOS switches used by the correction circuits.

2.5.3 Correlated-double sampling technique:-

Correlated double sampling technique is an auto-zeroing technique followed by an

analog sample-and-hold circuit. This technique helps eliminating the offset as well as the low
frequency 1/f noise. The disadvantage of this technique is that it needs sampling capacitors at
input which limit the sampling rate and the bandwidth. Furthermore, it needs a complex
clocking scheme to operate and the correction accuracy depends strongly on the signal
amplitude. Thus, this technique is not suitable for continuous time comparators or high speed
ADCs.

2.5.4 Chopper stabilization technique:-

In chopper stabilization technique, the polarity and random offset of a comparator is

detected by monitoring the digital output code density, and then binary feedback is used to
digitally compensate the offsets until it is minimized. One of the disadvantages of the chopping
calibration technique is that it needs a chopping circuit which is composed of several switches
in front of the comparator. These analog switches on the analog signal path cause signal
distortion and degrades the signal bandwidth.

2.6 Foreground calibration technique

In foreground calibration, required calibration values are determined once during the
system start up or just before sub-block operation and the obtained values are stored and used
for correcting the offsets during regular operation. Foreground calibration techniques can only
correct static offsets. Implementing foreground calibration is not as complicated as
implementing background calibration. Thus, it is more suitable for high-speed comparators and
ADCs. Common foreground calibration techniques include threshold tuning, redundancy and
re-assignment, and digitally controlled trimming approaches.

2.6.1 Threshold tuning technique:-

Threshold voltages of comparator transistors on critical signal paths could be tuned by

using non-volatile floating gate elements that store charge for trimming in order to correct the

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offset voltages. Another method of tuning threshold voltage is pushing charge into bulk (body)
of MOS by using a charge pump. Special process steps are required to build stacked gates or
bulks, one of which is floating is the main disadvantage of this method. Therefore, this
technique is process dependent.

2.6.2 Redundancy technique:-

Redundancy and re-assignment technique is mainly used in flash ADCs. More than two
comparators for each reference voltage are integrated in the flash topology, but only one of
these is active during normal operation while the rest are powered off. During start up,
calibration circuit reassigns one of the redundant comparators with the least offset drift from
the reference voltage. The main disadvantage of this calibration technique is that it needs
complex correction circuits (i.e., summing encoder) which cause speed degradation. Also using
large number of redundant comparators requires large silicon area.

2.6.3 Digitally controlled trimming technique:-

Digitally controlled trimming is a popular calibration technique developed for high-

speed ADCs and can be implemented using different approaches. The offset voltage is not
sampled in these techniques. Instead, calibration circuits compensate for the input referred
offset by imposing digitally controlled counter imbalance on one of the comparator’s signal
paths. Digitally controlled trimming methods are grouped into two approaches; digital
calibration and digitally-assisted analog calibration.

Digital calibration is implemented by using digitally controlled binary-weighted circuit

elements (capacitors, transistors, etc.) connected on different comparator nodes. Digitally-
assisted analog calibration is implemented by applying analog calibration signals to counter
imbalance element parameters (current, capacitance, transconductance, resistance, etc.) on the
comparator’s signal paths.

These calibration signals are generated by integrated DACs and at most a single circuit
element is added to the comparator instead of an array of elements. In these approaches,
integrated or external digital logic or signal processing circuits determine the digital correction
words by equalizing the comparator outputs either statistically or through linear search. The
obtained trimming words are then stored on integrated memories. Stored digital correction
words either control the value of circuit elements such as binary-weighted capacitive loads or
control DACs that generate analog trimming signals for the added circuit elements.

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3. Fully Dynamic Latched Comparators
Comparators could be designed to work continuously (static) or to make decision after
being initiated with a clock signal (dynamic). Dynamic comparators have replaced static
comparators in many applications to minimize power consumption without trading off speed
Latch-type comparators are able to accomplish decisions more rapidly with no static power
dissipation and strong positive feedback. Moreover, latch type comparators can generate high
gain in regeneration mode due to the positive feedback features.

Now-a-days fully differential ADC is the first choice of designers due to its noise
immunity property. Hence, double tail dynamic latch comparator is widely used due to its
differential input nature. It can be of two types depending upon application. One is PMOS input
type- In this input pairs of comparator are PMOS type which can able to detect very low input
differences. Another is NMOS input type- In this input pairs of comparators are NMOS type
which requires a common mode voltage to detect very low inputs. Hence based on application
requirements, type of dynamic latch comparator will be chosen.

In this chapter NMOS-input type of the fully dynamic latch comparator will be analyzed
in detail. It is commonly known as Double Tail Dynamic Latch Comparator (DTDC).

3.1 Double Tail Dynamic Latch Comparator:-

A Double Tail Dynamic Latch Comparator shown below have a lower and more stable
offset voltage over wide common-mode voltage (Vcm) ranges and operate at a lower supply
voltage as well. It is done by controlling the sizes of the tail transistors (M13 and M1) of the
input and output stage in such a way that a small tail current for the differential input pair leads
to obtain a long integration time and a better gm/ID8,17 ratio for a bigger gain. Hence less offset
voltage and a large tail current for the output latch-stage for fast regeneration, one can get fast
speed and low offset voltage with less dependency on Vcm.

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3.1.1 Circuit operation:-

The operation of double tail dynamic comparator can be understood in two phases-
one is reset (clk=GND, clkb=VDD) and another is evaluation phase (clk=VDD, clkb=GND).
Therefore, the comparator is positive-edge triggered.

In reset phase PMOS transistor pair M9 and M10 pre-charge Di node capacitances
(parasitic) up to VDD. At the same time, the NMOS transistor pair M6 & M7 are turned on
and both output nodes OUTP and OUTN are reset to GND irrespective of any input applied.
While both tail transistors (M13 and M1) of the input stage and output latch-stage are off.
Hence in reset phase both outputs are at same level.

Figure 3.1: Circuit diagram of double tail dynamic latch comparator

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 During evaluation phase once the input-stage tail transistor M13 is turned on, each Di
node voltages starts to discharge from VDD to GND with a different time rate proportional to
each input voltage. Then, the voltage difference built between Di nodes is passed to output
latch-stage through the transistor pair M6 and M7. Due to discharging of Di nodes, as the gate
voltage of NMOS pairs approaches common-mode voltage, PMOS pairs M20 & M21 starts to
pull up the output nodes. Depending on inputs, the cross-coupled inverters start to regenerate
the voltage difference formed between output nodes as soon as the common-mode voltage at
the Di nodes is not big enough to clamp out nodes to GND. With the help of positive feedback
one of the output nodes start toggling to VDD while another output remains at GND during
evaluation phase.

Hence one can understand that if Vip is more than Vin, then OUTP will toggle and vice
versa.

Figure 3.2: Output response of double tail dynamic latch comparator

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 As this comparator requires both Clk and Clkb signals for its operation, high accuracy
timing between Clk and Clkb is required because the second stage has to detect the voltage
difference between the differential outputs of the first gain stage at short span of time. If a
simple inverter replaces Clkb, Clk has to be able to drive an additional large inverter (heavier
clock load) in order to drive the largest transistor M12 in a small delay. If Clkb is lagging Clk,
it results in increased delay and if Clkb is leading Clk, it results in increased power dissipation
due to existing the short circuit current path M1 to M6/M7 though M20/M21 and it can even
increase the latch offset voltage if the device mismatch between M8 and M17 is significant.

Figure 3.3: Zoomed view of output response of double tail dynamic latch comparator

From the response it is clear that, during the positive edge of clock as vip is more than
vin Di+ node discharges fast. Due to this node Lp start to regenerate towards VDD. But it takes
time due to the presence of PMOS tail transistor M1. Hence to overcome this issue buffers are
required to get instant output. This is the reason behind two back to back inverters are inserted
into the outputs. From the response it is clear that using buffers, comparator response time
improves. The comparison time of comparator is less than 10ns.

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3.1.2 Design approach:

From the circuit operation it is clear that PMOS M9, M10 and NMOS M6, M7 are
acting just like a switch. The output latch stage is basically two cross-coupled inverters. So
these are basics cell of a designed inverter. The main designed elements are input differential
pair and two tail transistors. The channel length of input differential pair is taken more than
two times of minimum channel length to reduce short channel effects and channel length
modulation. One more advantage of increasing channel length is that mismatch between these
two transistors reduces as well. With increase of channel length of NMOS tail transistor gain
increases. PMOS tail transistor width is taken more to increase the latch current and to reduce
the regeneration time.

There is a trade-off between width of differential input pair and offset voltage. As width
increases, parasitic get increased proportionally. Hence fingering is done to reduce the parasitic
effect. From the simulations of different width of inputs pairs, the aspect ratio of input pair is
found to (500/500 nm)*3. At this the trade-off between width and offset is less.

3.1.3 Offset analysis:

As offset voltage is an important parameter in dynamic comparator, it has to be

measured accurately. The offset can be measured by using a slowly rising ramp signal, applied
to one of the input of dynamic comparator while common-mode voltage (900mv) is applied to
other input. If both inputs of an ideal comparator are kept at common-mode voltage, the output
of the comparator doesn’t toggle and remain constant to any of the supply voltage.

Hence, if a slowly rising ramp (895mv to 905mv) is applied to any one input while the
other input is fed to common-mode voltage, the comparator output toggles when the applied
ramp goes on increasing beyond 900mv. The value of applied ramp signal at which the output
toggles is the required offset voltage of dynamic comparator. One thing should be kept on mind
that the frequency of applied CLOCK to the comparator must be in GHz range. This is because
of the fact that due to fast changing CLOCK, comparator is bound to take decision very fast
and provide the output. This will lead to more accurate results.

Due to metastability issues, the applied ramp should be both increasing and decreasing.
The reason behind using both increasing and decreasing ramps is that as the offset voltage is
in microvolts (obtained from simulation), the offset is very nearer to the metastability point.
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Metastable point of a comparator is a point where comparator decision is uncertain in nature.
The offset obtained from both increasing and decreasing ramp is averaged to get the final offset.

Monte-Carlo simulation is also done to approximate the static as well as dynamic offset
of the comparator. The MC simulation is done considering only the mismatches of differential
input transistors (M8 & M17). The mean value & standard deviation of offset (500 points) is
found to be 3.9 mV & 2.6 mV respectively. The worst case offset is calculated by using µ+3σ
i.e. approx. 11 mV. The reason behind this higher value is the mismatch between parasitic
capacitances of Di nodes and input differential pairs which can be analysed in details in later
chapter.

The obtained offset value is very higher than the required value. As it is known that the
offset should be less than 1 LSB value. So the comparator cannot be used without any offset
cancellation technique. Hence an efficient offset calibration technique is required which can
compensate such large offset and reduces it up to the range of microvolts.

Figure 3.4: Monte-Carlo simulation of offset of double tail dynamic latch comparator

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3.1.4 Post-Layout simulation:

The layouts of double tail dynamic latch comparator has been done in UMC 180nm
technology. The offset of comparator is layout dependent due to the long routing of Di node
connections. So efficient layout strategy leads to the lowering of offset up to a limit. In post-
layout simulations the offset of comparator is found to near 8 mV.

Figure 3.5: Layout of double tail dynamic latch comparator

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Figure 3.6: Post-Layout offset measurement of double tail dynamic comparator

Figure 3.7: Post-Layout output response of double tail dynamic latch comparator

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4. Offset Voltage Analysis for Dynamic Comparators:

4.1 The offset voltage in dynamic latch comparators is mainly comprised of two types:

1) Static offset voltage due to variation in µCox and threshold voltage and
2) Dynamic offset voltage from internal node parasitic capacitors’ imbalance.

Apart from mismatch caused by µCox & and Threshold Voltage (Vth), the effects of
parasitic capacitances mismatch are observed only during transient process and therefore called
dynamic offset. A four-terminal MOS device includes several parasitic capacitors. For a
matched pair in the dynamic comparator, any dimension mismatch due to process variation and
asymmetric interconnection will cause capacitance mismatch.

Figure 4.1: Simplified schematic of the differential input gain stage

The simplified first stage of the dynamic comparator is show above. During evaluation
phase (clk=vdd), the input differential pair discharges each Di node voltage from vdd down to
0V with a different time rate proportional to each input voltage. By assuming that λ= 0 for
simplicity, since both transistor M2 and M3 operate in the saturation region between the time
t1 and t2 (t1: time at which transistor M1 is just turned on at the rising Clk edge and transistor
M2 and M3 start to operate in the saturation region, t2: time at which either of transistor M2 or

26 | P a g e
M3 moves out of the saturation region operation and goes into the linear region operation), the
drain-to-source current of M2 and M3 are constant over [t1, t2]. Therefore, the currents can be
expressed as-

dVDi− (t)
CDi− = icDi− (t) = −ID2 (1)
dt

dVDi+ (t)
CDi+ = icDi+ (t) = −ID3 (2)
dt

By integrating both sides of (1) and (2) over [t1, t] and applying the initial condition:
VDi (t1) =vdd, the following equations are obtained;

ID2
VDi− (t) = vdd − .t (3)
CDi− (t)

ID3
VDi+ (t) = vdd − .t (4)
CDi+ (t)

∆VDi (t) = VDi− (t) − VDi+ (t) (5)

Then, under the assumption that ΔVin (Vin+ − Vin-) is constant over the integration time [t1, t]
(t is between t1 and t2), the dynamic gain of the first stage can be defined as-

dVDi (t)
Av1 (t) = (6)
∆Vin

By applying the small signal approximation: 2(VGS2,3 – Vtn) >>ΔVin and assuming that

CDi- =CDi+ = CDi, Equation (6) can be expressed as-

gm2,3
Av1 (t) = − .t (7)
CDi

W2,3
where g m2,3 = μ n Cox . . (Vcm − VD1 (t) − Vtn2,3 ) & VD1 (t) = (ID2 + ID3 ). rds1 ≈
L

constant

Equation (7) reveals that as long as the input transistor pair M2 and M3 operates in the
saturation region and ΔVin does not change over [t1, t2], the dynamic gain AV1 (t) keeps

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increasing with the increasing time. To maximize the gain |AV1 (t)|, |gm2,3/ID2,3| should be
maximized because the integration time t is proportional to CDi/ID2,3 from (3 & 4). Simply, this
can be done with reducing the size of transistor M1. However, as equation (3 & 4) also
indicates, the reduced ID2,3 increases the discharging time of Di node voltages during evaluation
phase. Therefore, the higher gain can be achieved at the cost of the increased delay.

Furthermore, by increasing the channel length of the input transistor, one can get higher
gain with the same W2,3/L ratio by reducing short-channel effects.
To calculate the offset voltage (VOSpre1 ) of the input differential pair, both input
transistors and Di node capacitances are assumed to be mismatched. Then, the device
parameters and Di node capacitances can be express as;

Then, the value ΔVin (Vin+ − Vin−) which make ΔVDi = 0 is the offset voltage (VOSpre1 ),
which is equal to VGS2 − VGS3. From equation (5), ΔVDi = 0, it can be derived that ID2. CDi+ =
ID3. CDi−. Since we assumed that Di node capacitances were mismatched (CDi+ ≠ CDi−), ID2 cannot
be equal to ID3. By assuming that ID2 = ID and ID3 =ID +ΔID, ΔID/ID = ΔC/C is obtained.
Therefore, the offset voltage is derived by following way [3 & 4].

VOSpre1 = VOS2,3 = VGS2 − VGS3

∆I
2ID2 2ID3 2ID 1+ I D
D
VOSpre1 = √ + Vtn2 − √ − Vtn3 = √ . [1 − √ ∆β ] − ΔVtn
β2 β3 β 1+ β

Assuming ΔID/ID << 1 and Δβ/β << 1, the above equation is reduced to:

2ID 2∆ID ∆β
VOSpre1 = √ [1 − (1 + )(1 − ) ] − ΔVtn
β ID β

2ID ∆ID ∆β
=√ [− + ) ] − ΔVtn
β ID β

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 VGS2,3 −Vtn ∆C ∆β
= [− + ) ] − ΔVtn (8)
2 C β

Considering the charge injection mismatch (ΔQ) between PMOS transistor M4 and M5,
the additional term ΔQ/CDi has to be added to equation (8). Since mismatches are independent
statistical variables, the random offset voltage (VOSpre1 ) can be expressed as the variance of (8):

2
VGS2,3 −Vtn ∆CDi 2 ∆β 2 ∆Q 2
VOSpre1 2 = ( ) [{( ) +( ) }+( ) ] + ∆Vtn 2 (9)
2 CDi β CDi

Equation (9) shows that:

(1) The threshold voltage mismatch is directly referred to the input.

(2) Di node capacitances mismatch, which consists of the mismatch between the drain
diffusion capacitances of the input transistor pair (M2 and M3). The current factor β mismatch
increases with the increasing common mode voltage Vcm.
(3) The influence of the charge injection mismatch (ΔQ) on the offset voltage is related to Di
node capacitances.
Since all terms are related to the size of transistors, the offset voltage can be reduced at
the cost of the increasing size of the transistors, hence increasing area and power consumption.
But care should be taken that increasing transistors sizes will proportionally increase the
residual offset as well as kickback noise. Di nodes capacitance mismatch can be reduced by
efficient layout techniques.

4.2 Kickback Noise:

During the regeneration process the latched comparator uses the positive feedback
mechanism to scale the digital level. The voltage variations at the regeneration nodes are
coupled to the inputs and disturb the input voltages. This disturbance is called kickback noise.
The analog input signals are regenerated to digital output level, the large voltage
variations in the internal nodes of comparator are coupled to the input (due to gate-drain
parasitic capacitance), disturbing the input voltage. The non-idealities of dynamic comparators
are thermal noise, offset voltage and kickback noise. The presence of non-idealities can restrict
the resolution, accuracy, conversion speed and ENOB of ADCs.

29 | P a g e
 Noise in a dynamic comparator can be reduced by upsizing the input MOS transistor
pair, which in turn generates the kickback noise as with increase in MOS width, the gate to
drain parasitic capacitance will increase, results in increased kickback noise. The generated
kickback noise is proportional to the parasitic capacitance of the input transistors and can
operate in all the regions (triode, cut-off and saturation) during the comparison process,
seriously affecting the accuracy of the decision taken by the comparator. Due to kickback noise,
the input voltage get distorted and the comparator takes a wrong decision.

Figure 4.2: Kickback noise affecting input nodes

The parasitics play a critical role in analog designs. The ac behaviour of the MOSFET
is crucially effected of parasitics. The figure shows a simple model to illustrate the parasitics
of a MOSFET. Between every two of four nodes of MOSFET, there exists a capacitance. The
capacitance depends upon the gate voltage and it changes values according to the region of
operations. The capacitances are; overlap capacitance between gate and source/drain, depletion
capacitance between channel and substrate, oxide capacitance between gate and channel and
junction capacitance between source/drain and substrate. It can be concluded that the fastest
and most power efficient comparators generate more kickback noise.

Figure 4.3: Parasitic capacitors of a typical MOS

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4.3 Metastability
Normally in all latching comparators metastability is a problem which occurs when the
input is near the comparator decision point. Comparator metastability occurs when very small
signals appear at the input of a comparator, close to the comparator decision point. Normally
all kind of latching comparators exhibit this problem. In such cases, the comparator is not able
to make a decision, i.e. did not latch its output to the stable point, within the allotted time. This
metastability delay is random and could switch the output to the wrong logical levels which
can cause system malfunction or failure. The figure shows the voltage transfer characteristics
of two back to back connected inverters. Each inverter has two stable points; VDD and GND.
The mid-point where the two curves intercept each other is metastable point (MSP) as shown
in the figure. Ideally the MSP of an inverter is at half of the input range i.e. Vdd/2. Now, if the
input at the first inverter slightly deviates from Vdd/2, the output at the second inverter goes to
one of the stable states. In this band of range the output is unpredictable and can switch to
wrong logic level.

Figure 4.4: Voltage transfer curve (VTC) of two back-to-back inverters

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5 Offset Calibration

5.1 Need of Calibration:

Variations could occur during the fabrication process of the MOS transistors. As a result
of these variations, the physical and electrical parameters of two identical devices closely
placed to each other on an integrated circuit (IC) show random variations that result in device
mismatches. These random parameter mismatches lead to random DC offsets in dynamic
latched comparators.
For a matched pair in the dynamic comparator, any dimension mismatch due to process
variation and asymmetric interconnection will cause capacitance mismatch. It has been
demonstrated that a 1fF capacitance mismatch at the internal & output node may contribute in
several of millivolts of input-referred offset voltage. This will affect the decision of comparator
very badly. As comparators required for ADC application must have high resolution i.e. the
comparators must be able to sense the input differences in the range of micro-volts. But due to
offset in millivolts, this cannot be achieved.
So, it is necessary to compensate the offset at the cost of anything so that the comparator
can take correct decision. There are various types of offset callibration/compensation
techniques which are quiet efficienct to compensate static offset voltage but they are not able
to compensate dynamic offset voltage e.g. input offset cancellation using [Link] an
efficient technique is required which can compensate static as well as dynamic offset voltages.
Therefore a foreground offset compensation or self-calibration technique is used to
eliminate both static as well as dynamic offset voltages. The offset calibration technique does
not require quiescent DC current for offset cancellation owing to use of a charge pump circuit
instead of a pre-amplifier. Thus, the offset cancellation achieves not only low offset voltage
but also low power consumption. Moreover, the circuit topology can improve the comparator
noise.
There are various advantages of using calibration techniques like reduction of kickback
noise, lowering of input device dimensions, improvement of conversion time etc. Due to this
offset dramatically reduces up to the range of one LSB value. The offset calibration gives a
flexibility towards the sizing of input pairs. A low offset can be achieved without using larger
transistors.

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 The drawbacks of calibration technique is that it requires many clock pulses before the
comparison starts. Once the comparator gets calibrated it can compare the input differences in
the range of one LSB value. Every comparator have some residual offsets which cannot be
compensated or eliminated. This is again due to fact of parasitics as for example charge
injection, clock-feed-through etc.

5.2 Calibration technique:

As dynamic offset is mainly caused by parasitic capacitances mismatch in the internal

Di nodes, so these nodes are targeted to reduce or compensate the offset. If common-mode
voltage to both the inputs, the outputs of comparator should not toggle ideally. But due to the
mismatch in the internal Di nodes, one of the output starts toggling. During the precharge phase,
the Di+ & Di- parasitic node capacitors are charged to vdd. This voltage is discharged through
input pair transistors at a rate depending on the input values. Ideally the discharging rate of
both nodes are same. But due to mismatch the discharging rate is different and hence current
through both the nodes are different. More offset leads to the more difference in discharging
currents.

Figure 5.1: Input differential pair of dynamic comparator with parasitic

If this discharging rates can be controlled the mismatch effect can be reduced very
efficiently. Conceptually, this is the basic idea of the offset calibration of dynamic comparator.

33 | P a g e
For the controlling of discharging currents two extra differential MOS pair (M15 & M16) are
connected to Di nodes. By connecting this two mosfets, the discharging current has two parallel
paths to flow as shown in figure. The gates of two extra differential pairs are connected to large
capacitors which should be capable of storing common-mode voltage. To bias this extra
differential pairs, one tail transistor is connected as in comparator architecture. The dimensions
of these mosfets (M15, M16 & M18) should be same as the comparator have. This extra
arrangement of three mosfets connected to Di nodes, are used for offset calibration and can be
termed as ‘calibration unit’.
If gates of all shown mosfets are connected to common-mode voltage, ideally current
through Di nodes are ‘I’ (say), but due to mismatch current through one node become ‘I+∆I’.
To balance same currents from each node, calibration unit is connected. After that ‘I’ will
divide into two equal parts. For simplicity suppose there is a mismatch in Di- node capacitance.
So the currents through mosfets are:

Figure 5.2: Input differential pair of dynamic comparator with calibration unit

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M1---- I⁄2

M8---- I⁄2 + ∆𝐼⁄2

M15--- I⁄2

M16--- I⁄2 + ∆𝐼⁄2

It is known that if gate to source voltage of mosfets is increased then current through
the mosfets will increase (if other factors are constant). So by increasing or decreasing the gate
voltages of M15 & M16 differentially, the current through the Di nodes can be controlled. As
mismatch is considered in Di- node, then current through M16 & M8 is to be reduced and
increased respectively. This is done by reducing and increasing the gate voltages of M16 and
M8 respectively. Hence using this mechanism current through both Di nodes can be matched
and the offset of comparator can be reduced efficiently.

Care should be taken that the increasing and decreasing in gate voltages should be
differential in nature i.e. they should be increased or decreased in equal amount. There is a self-
controlling feedback mechanism which can ensure the differential change and control the
charging mechanism of capacitors connected to the gate of M16 and M8, which will be
discussed later-on in details.

5.3 Calibration logic:

The calibration logic basically controls the charging and discharging of capacitors
connected in calibration unit. This can be done using a charge pump circuit. A current source
and a clocked switch will charge the capacitors up or down as required.

Figure 5.3: A typical arrangement of charge-pump

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 In order to achieve offset value below one LSB value, the step size of charging or
discharging should be near of half of one LSB value. This is because when the capacitor
voltages are close enough to overcome the offset, bigger step-size leads to over calibration and
may introduce noise. The figure shown is a typical charge pump used for calibration. Due to
mismatch either OUTP or OUTN will be toggled at a time. Depending on this and CLK_CAL,
the capacitor is either charged up or down.

5.3.1 Circuit operation:

Figure 5.4: Circuit diagram of calibration logic

When CLK_CAL is low, transistor M11 and M3 are on and they charge Cu and Cp with
Vrefp and Vrefn respectively. When CLK_CAL is high, charge redistribution between Cp/Cm and
Ccal takes place. Hence using this mechanism Ccal is charged up or down in every clock cycle
with a fixed step size. The step size is set to around 60 µv by sizing Cp and Cm as 1fF and Ccal

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as 25pF. This huge difference in capacitors leads to achieve the small step size. The capacitor
sizes can be reduced by choosing Vrefp and Vrefn closer to common-mode voltage. As the gap
between Vrefp/Vrefn and common-mode voltage reduces, the size of Ccal reduces dramatically.

Basically goal is to charge the capacitors with a step size near to half of one LSB value.
The step size is determined by charge redistribution between Ccal and Cu or Cp. From the charge
C𝑢 /𝐶𝑝
redistribution the ratio of can be found out as:
𝐶𝑐𝑎𝑙

C𝑢 /𝐶𝑝 𝑉𝑢 − 𝑉𝑓
= (1)
𝐶𝑐𝑎𝑙 𝑉𝑓 − 𝑉𝑝

Where; 𝐶𝑐𝑎𝑙 is calibration capacitor connected to calibration unit,

Cu/Cp is charging or discharging charge pump capacitor,

Vu is initial voltage of charging pump,

Vp is initial voltage of discharging pump,

Vf is final voltage of calibration capacitor after charge redistribution.

From equation (1) it is clear that in order to achieve step size of 60 µv, the ratio of
C𝑢 /𝐶𝑝
is approx. 10-3. If Cu/Cp is chosen 1fF then 𝐶𝑐𝑎𝑙 should be around 1.5 pF. But due to the
𝐶𝑐𝑎𝑙

body effect of M3 and M11, 𝐶𝑐𝑎𝑙 have to be increased to 25pF. This is because of the fact that
UMC 180nm technology is not a ‘TWIN-TUB’ process. Hence body terminal of M3 and M11
cannot be connected to source terminal of the respective mosfets. Therefore, due to the
technology dependency calibration capacitor size increases a lot.

Figure 5.5 shows the detailed circuit diagram of calibration logic. At first inputs of
comparators are connected to common-voltage voltage. An external RST signal will charge the
calibration capacitors (Ccal ) of calibration unit to common-voltage voltage. After that, an
external EN signal will start the calibration phase. Now comparator is clocked to identify the
offset. Depending on the mismatch one of the output of comparator start toggling. This
comparison result is feed-backed to the calibration logic and hence Ccal either absorbs charge
from Cu or pushes charge into Cp. Hence, capacitors of the calibration unit charged up and
down differentially i.e. if one calibration capacitor is absorbing charge then other calibration
capacitor should release charge. This process is totally dependent on comparison result of
comparator. The charging and discharging mechanism continues until the other output starts

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toggling. As a result an EOC signal will be generated and offset calibration phase will be
terminated. There is a ‘calibration control logic’ which control all the operation of calibration
phase.

Figure 5.5: Circuit diagram of calibration phase

5.3.2 Calibration control logic:

Two non-overlapping clocks are required for comparator and calibration logic
respectively as shown in figure. The circuit diagram to generate two non-overlapping clocks is
also shown in figure. It is done as comparator has some internal delay i.e. comparator takes
some time to provide output. Up to that time calibration should not start. The circuit is basically
a cross-coupled NAND based latch with some delay connected in input and output. The internal
and external signals which controls the calibration are explained below-

a. RST- An external signal used to charge the capacitors of calibration unit initially.
b. EN- An external signal used to start the calibration phase. Once calibration is over it is
forced to go low by using digital circuitary.

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Figure 5.6(a): Circuit diagram of generation of two non-overlapping clocks

Figure 5.6(b): Circuit diagram of delay unit

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 Figure 5.7: Timing diagram of clocks & signals required in calibration phase

c. Eoc- It is an internal signal which generates when calibration is over.

d. En12- It is an internal signal used to stop the calibration and comparator clock
instantly, once calibration is over.

Figure 5.8: Circuit diagram of calibration control logic

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5.4 Results:
Monte-Carlo simulation has been done over 500 points to check the accuracy and
efficiency of double tail dynamic latch comparator after offset calibration. From the shown
figure, the results are quite satisfactory and nearer to the expected values. The mismatches of
respective input differential pair of comparator and calibration unit has been considered for
Monte-Carlo simulations. The results are based on one Monte-Carlo sampling and
corresponding calibration, after each calibration offset is measured. From the simulation, the
mean value & standard deviation of offset is found to be 75 µV & 38 µV respectively. From
the figure it is clear that there are no samples outside 2σ value. Hence, offset can be calculated
by using formula µ+2σ i.e. approx. 150 µV. Therefore it can be concluded that the proposed
offset calibration scheme is quite efficient to reduce static as well as dynamic offset. As the
results are quite satisfactory, layouts of double tail dynamic comparator and whole calibration
block has been done to verify the results in post-layout simulations.

Figure 5.9: Monte-Carlo simulation of self-calibrated Double Tail Dynamic Latch comparator

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5.5 Layouts:

Figure 5.10: Layout of calibration logic without calibration capacitors

Figure 5.11: Layout of calibration control logic

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Figure 5.12: Final layout of dynamic comparator with complete calibration block

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5.6 Post-layout simulation results:

Figure 5.13: Post-layout simulation of calibrated DTDC

After calibration offset of double tail dynamic latch comparator in post-layout

simulations reduces to 650 µV. The time taken for calibration is approx. 450 µs. As the
comparator required to calibrate once at the time of starting up, so this time can be tolerated.
From the figure 5.13 it is clear that the calibration capacitors of calibration logic are charged
up or down differentially. After the end of calibration EOC signal has been generated which
can be used by the successive block of ADCs.

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5.7 A comparative study of results:

A comparative study of double tail dynamic latch comparator in pre-layout and post-
simulations with and without insertion of calibration block has been done as follows:

Pre-layout Post-layout After calibration

(Post-layout)
Offset 8 µV 8mV 645µV

Decision time 1.58 ns 1.69 ns 1.46 ns

Avg. power 1.1 µW 1.3 µW 11µW

Energy per 1.7 fJ 2.1 fJ 16 fJ

conversion

Hence, it is clear that the offset of double tail dynamic latch comparator is efficiently
reduced with a cost of increased power dissipation. The comparison time of DTDC is also
reduced because of the fact that the Di node parasitic capacitances have two parallel paths for
discharging (due to insertion of calibration unit). Hence discharging rate is fast and as a result
the comparator will be able to take a fast decision.

The average power dissipation get increased due to the offset calibration. As the two
calibration capacitors remain on all the time after calibration, the power dissipation increases
by 10 times. Overall it can be concluded that the offset calibration technique is quiet efficient
and fast.

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6. Dynamic Latch Comparator (PMOS-input type)

The drawbacks of NMOS-input type dynamic latch comparators are the requirement of
a common-mode voltage for its operation and high power dissipation. Basically NMOS-input
comparators can compare a minimum voltage defined by the Threshold Voltage (Vth) of NMOS
transistor. To mitigate this drawbacks PMOS-input type dynamic latch comparators came into
picture. These types of architectures have some advantages which will be discussed. Figure 6.1
shows popularly used PMOS-input type dynamic latch comparator.

Figure 6.1: Circuit diagram of PMOS-input type dynamic latch comparator

6.1 Circuit operation:

The operation of the dynamic latch comparator can be understood in two phases- one
is reset (clk=VDD, clkb=GND) and another is evaluation phase (clk=GND, clkb=VDD).
Therefore, the comparator is said to be negative-edge triggered.

When the clock signal is high, transistor M7 & M8 are switched on and shorts the ti
nodes to GND. At this instant, transistors M19 & M18 also get turned on and pull the outp &
outn nodes to VDD. When the comparator clock signal is low, the tail MOS M11 turns on and

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transistors M9 & M24 starts amplifying the differential input signal .The amplified signal is
put to the gate of M29 & M30 respectively.
Basically depending on the input voltages charging rate of ti nodes are defined. As in
PMOS with increase in gate voltage, effective Vsg reduces. As a result current through the MOS
reduces. Thus the MOS which input is more will charge the respective ti node slowly. As the
voltage of ti node reaches the Threshold Voltage of NMOS transistor, the NMOS transistor
forces to pull down one output node to GND and other to VDD due a positive feedback loop
formed by the latch stage transistors M12, M14, M15 & M16. In this way comparator takes a
fast decision.

Figure 6.2: Output response of PMOS-input type dynamic latch comparator

This type of comparators are typically faster and power efficient due to the insertion
of two NMOS transistors in output latch stage.

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6.2 Design approach:

From the circuit operation it is clear that NMOS M7, M8 and PMOS M18, M19 are
acting just like a switch. The output latch stage is basically two cross-coupled inverters. So
these are basics cell of a designed inverter. The main designed elements are input differential
pair and two tail transistors. The channel length of input differential pair is taken more than
two times of minimum channel length to reduce short channel effects and channel length
modulation. One more advantage of increasing channel length is that mismatch between these
two transistors reduces as well. With increase of channel length of PMOS tail transistor gain
of input pair increases.

There is a trade-off between width of differential input pair and offset voltage. As width
increases, parasitic get increased proportionally. Hence fingering is done to reduce the parasitic
effect. To compare the results with double tail dynamic latch comparator, sizing of the said
comparator is chosen as same as of that.

6.3 Offset analysis

6.3.1 Offset without calibration:

Monte-Carlo simulation is done to approximate the static as well as dynamic offset of

the comparator. The MC simulation is done considering only the mismatches of differential
input transistors (M9 & M24).

Figure 6.3: Monte-Carlo analysis of offset of PMOS-input type comparator

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 The mean value & standard deviation of offset (500 points) is found to be 25 nV & 14
nV respectively. The worst case offset is calculated by using µ+3σ i.e. approx. 100 nV. Thus
the offset obtained is far below from one LSB value.

6.3.2 Offset after calibration:

Monte-Carlo simulation has been done over 500 points to check the accuracy and
efficiency of comparator after offset calibration. The mismatches of respective input
differential pair of comparator and calibration unit has been considered for Monte-Carlo
simulations. The results are based on one Monte-Carlo sampling and corresponding calibration,
after each calibration offset is measured. From the simulation, the mean value & standard
deviation of offset is found to be 182 µV & 28 µV respectively. Hence, offset after calibration
can be calculated by using formula µ+3σ is approx. 266 µV.

Figure 6.4: Monte-Carlo analysis of offset of PMOS-input type comparator after calibration

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6.4 Layout:

Figure 6.5: Layout of PMOS-input type dynamic latch comparator

In post-layout simulations offset of PMOS-input type dynamic latch comparator is

found to be 13 mV. Hence this offset need to be calibrated to achieve high accuracy comparison
result.

6.5 Offset calibration:

To calibrate the PMOS-input type dynamic latch comparator, two modifications are
required. One in calibration unit- as the input differential pair of comparator is PMOS type, so
calibration unit is also to be same type. Another change is to just place an inverter in front of
comparator as the comparator is negative edge triggered. All remaining blocks and functioning
of the calibration blocks remains the same as discussed in previous chapter. The arrangement
of offset calibration is shown in figure 6.6. From the response of post-layout simulation (figure
6.7) it is shown that the calibration time is only approx. 170 µs. The capacitors of calibration
unit are charged or discharged differentially to 4.98 mV respectively. With the insertion of
calibration block offset of the comparator in post-layout reduces from 13mV to 200 µV.

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 Figure 6.6: Offset calibration of PMOS-input type dynamic latch comparator

6.7 A comparative study of results:

A comparative study of PMOS-input type dynamic latch comparator in pre-layout and
post-simulations with and without insertion of calibration block has been done as follows:

Pre-layout Post-layout After calibration

(Post-layout)
Offset 65 nV 13 mV 200 µV

Decision time 1.2 ns 3.8 ns 1.63 ns

Avg. power 110 nW 424 nW 4.5 µW

Energy per 0.13 fJ 0.46 fJ 7.3 fJ

conversion

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Figure 6.7:Post-layout simulation of offset calibration of PMOS-input type dynamic latch comparator

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7.1 Conclusion

In this paper an overview of comparators are shown based on some parameters like
speed, power, offset etc. Types of dynamic latch comparators are also discussed with their
advantages and disadvantages. Based on the comparative analysis it can be concluded that the
NMOS and PMOS input type dynamic latch comparators have their own advantages and
disadvantages. The PMOS-input type dynamic latch comparators are power efficient and hence
less energy required for each conversion but have moderate speed. While the advantage of
NMOS-input type dynamic latch comparator are moderate offset and high speed.

The proposed calibration technique is quite efficient to reduce the static as well as
dynamic offset up to a satisfactory value. The calibration technique is applied to both type of
dynamic latch comparators and the obtained results are quiet comparable to the targeted value.
To compare both type of architectures sizing of respective input differential pairs are kept same.
From the results it is clear that the mean value of offset is less in NMOS-input type dynamic
latch comparator (DTDC) while deviation is less in PMOS-input type dynamic latch
comparator. This is because of the residual offset caused due to the parasitic effect.

Offset Conversion Time Avg. power

(post-layout) (post-layout) (post-layout)
Dynamic Latch 645 µV 1.46 ns 11 µW
Comparator (NMOS-
input type)
Dynamic Latch 200 µV 1.63 ns 4.5 µW
Comparator (PMOS-
input type)

Hence, it can be concluded that the PMOS-input type dynamic latch comparators are
power efficient and have low offset but comparatively slower than NMOS-input dynamic latch
comparators (DTDC). One more advantage of PMOS-input type dynamic latch comparator is
that it doesn’t require a common-mode voltage for its operation. From the comparative study
of post-layout simulations it can be said that using PMOS-input type comparators, one can get
satisfactory results.

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7.2 Future work

 Modelling of both type of dynamic latch comparators in MATLAB. With the help of
this modelling, sizing of comparators can be optimized.

 Model the offset equations in MATLAB in order to achieve better or optimized sizing
of MOSFETS to reduce the offset further below. By using this results of Monte-Carlo
simulation can be improved.

 The offset caused by parasitic mismatch in the output latch stage need to be analysed
in order to know how it affects the comparator offset.

 The reasons behind the degradation of results in post-layout simulations need to be

analysed.

 The proposed calibration technique can be applied to more modified architectures of

Dynamic Latched Comparators.

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REFERENCES
[1] S. Kale and R. S. Gamad, “Design of a CMOS Comparator for Low Power and High
Speed”, International Journal of Electronic Engineering Research, vol. 2, no. 1, pp. 29-34,
2010.

[2] Shabi Tabassum, Anush Bekal, Manish Goswami “A Low Power Preamplifier Latch Based
Comparator Using 180nm CMOS Technology” Analog Integrated Circuits and Signal
Processing, vol. 74, no. 2, pp. 467–471, 2013.

[3] Manuel Delgado-Restituto, Rafael Domínguez Castro, Fernando Medeiro, Josep Lluís de
la Rosa “Trade-Offs in the Design of CMOS Comparators” chapter-14, Trade-Offs in Analog
Circuit Design, pp.407-441.

[4] Behzad Razavi and Bruce A. Wooley “Design Techniques for High-speed, High-
Resolution Comparators” IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 12.
DECEMBER 1992.

[5] M. Miyahara, Y. Asada, P. Daehwa and A. Matsuzawa, “A Low-Noise Self- Calibrating

Dynamic Comparator for High-Speed ADCs,” in Proc. A-SSCC, pp. 269-272, Nov. 2008.

[6] Islam T. Abougindia, Ismail Cevik. Fadi N. Zghoul, Suat U. Ay “A precision comparator
design with a new foreground offset calibration technique” Analog Integrated Circuits Signal
Processing 83:243–255, oct. 2015.

[7] Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger “Analyses of Static and Dynamic
Random Offset Voltages in Dynamic Comparators” IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009.

[8] Amin Nikoozadeh and Boris Murmann “An Analysis of Latch Comparator Offset Due to
Load Capacitor Mismatch” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II:
EXPRESS BRIEFS, VOL. 53, NO. 12, DECEMBER 2006.

55 | P a g e
[9] Shaolong Liu, Taimur Rabusk, Jeyanandh Paramesh, Lawrence Pileggi and Jorge
Fernandes “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled
SAR ADCs” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR
PAPERS, VOL. 65, NO. 2, FEBUARY 2018.

[10] Luu, Danny “Design and Background Calibration of Time-Interleaved High-Speed SAR
ADCs” a Doctoral Thesis, 2018.

[11] Islam T. Abougindia Ismail Cevik Fadi N. Zghoul Suat U. Ay “A precision comparator
design with a new foreground offset calibration technique” a Journal, Analog Integrated
Circuits and Signal Processing archive Volume 83 Issue 2, May 2015.

[12] Jinda yang, Xu cheng, Zhang zhang “A novel low offset Dynamic Comparator for high
speed low voltage pipe line ADC ” International Journal of Microelectronics Engineering
(IJME), Vol.2, No.2, April 2016.

[13] Jun He and Sanyi Zhan “A Simple and Accurate Method to Predict Offset Voltage in
Dynamic Comparators” in Proc. IECES’00, pp. I-32-35, Dec. 2000.

[14] G.A. Al-Rawi, “A New Offset Measurement And Cancellation Technique For Dynamic
Latches.” Proceedings of the 2002 IEEE International Symposium on Circuits and Systems,
vol. V of V, pp. 149-152, May 2002.

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