Journal of Electrical and Electronic Engineering

2015; 3(4): 93-96

Published online August 11, 2015 (http://www.sciencepublishinggroup.com/j/jeee)
doi: 10.11648/j.jeee.20150304.15
ISSN: 2329-1613 (Print); ISSN: 2329-1605 (Online)

Dynamic Comparator with Using Negative Resistance and

CMOS Input Pair Strategies in FS =4MHz-10GHz
M. Dashtbayazi1, M. Sabaghi2, *, S. Marjani1
1
Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
2
Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran

Email address:
[email protected] (M. Sabaghi)

To cite this article:

M. Dashtbayazi, M. Sabaghi, S. Marjani. Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS
=4MHz-10GHz. Journal of Electrical and Electronic Engineering. Vol. 3, No. 4, 2015, pp. 93-96. doi: 10.11648/j.jeee.20150304.15

Abstract: A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is
proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling
frequency from CMOS technology and the proposed comparator consumes 110nw-146µW at 1.5V supply.
Keywords: Comparator, Negative Resistance, Optical Communication Systems, Transconductance Boosting,
Dual-Rail Differential Input

accuracy at the same time [7].

1. Introduction One of the key components in ADC as the fundamental
Generally, comparator is an important part of electronic block for the A/D conversion, are the comparators. In fact they
systems, like Multi-GHz sample rate Analog-to-Digital are the link between analog domain and digital domain for
convertors (ADCs) [1-4] as crucial components in optical compare a set of variable or unknown values against that of a
communication systems. Due to limited accuracy, comparison constant or known reference value [8]. Many high speed
speed and power consumption, comparison of the input data is ADCs demands high-speed, low-power comparators with
regarded as one of the limiting factor of the high speed VLSI small chip area. For low-voltage operation, developing new
data conversion system. There is a growing need for the circuit structures is preferable in order to avoid stacking too
development of low power, low voltage and high speed circuit many transistors between the supply rails [9]. The critical
techniques and system building blocks because of increasing parameters in the ADC circuit design are speed, resolution,
demand for portable and hand held high speed devices. On the and power consumption. The ADC operates continuously,
one hand, low voltage operation is required to use as few however processing digital signals are dependent on specific
batteries as possible for low weight and small size. On the demands.
other hand at the high frequency of operation, Low power The organization of this paper is as follows. Section 2
consumption is demanded to prolong battery lifetime as much described the proposed dynamic comparator. Section 3
as possible [5, 6]. In the recent decade, due to the rapid illustrates the simulation results. A comparison to the
advancement in Analog-to-Digital conversion devices, the conventional comparators is also presented, followed by the
rapid advancement of VLSI technology causes the evolution conclusions in section 4.
of digital integrated circuit technologies for signal processing
systems that operate on a wide variety of continuous-time 2. Proposed Dynamic Comparator
signals including speech, medical imaging, sonar, radar,
consumer electronics and telecommunications. 2.1. Structure
Already with voltage scaling, sub-threshold voltage region
demands require technology for new architecture and The comparators are consists of two parts namely
innovative circuits. Previous advances in MOS technologies pre-amplifier and latch that these parts operate in the same
meet it for higher speed applications, however due to MOS phase. Therefore, comparator can pull the latch. In the second
device mismatches, it is difficult to achieve a high speed and phase, the pre-amplifier output nodes up to the power supply
voltage level. Also, the comparator offset can be cancelled in
94 M. Dashtbayazi et al.: Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

this phase [10-11]. Consequently, the comparator offset effect comparator output, two CMOS inverters have been used to
has not been considered in this paper. Fig. 1 shows the circuit supply capacitive loads. The comparator consumes dynamic
diagram has been used in simulations that has been obtained power because the comparator consists of dynamic latch and
from [12] with adding Q2 and Q4 that a dual rail pre-amplifier pre-amplifier [13].
is achieved. For decreasing the loading effect on the

Fig. 1. Schematics of the dynamic comparator and CMOS inverters.

2.2. Transient Behavior Fig. 2 shows the sketch map of the transient behavior of
the dynamic comparator in the comparison phase. By the
switching transistors Q8, Q9, Q12, and Q13 during the reset
phase, the output terminals and the drain side voltages of Q5
and Q6 are all pulled high to VDD, respectively. By turning
on the two tail transistors Q7 and Q16, the comparison phase
begins. Therefore, the CMOS input stage transfers the
differential small signal to the cross coupled stage. Q2, Q4
are activating when the input common mode is lower than the
Q1 or Q3 threshold voltage. Therefore, the dual-rail
differential input obtain since they are supplies the
preamplifier output. Based on [14], the comparison transition
can be divided into three phases (from phase 1 to phase 3).
The output terminals are pulled down by two tail transistors
Fig. 2. The sketch map for the transition behavior of the dynamic comparator. Q7 and Q16 during the phase 1. Until one of the two output
terminal voltages decreases to (VDD-Vthp), the p-channel
transistors Q10 and Q11 remain cut-off. The Q2 and Q4
activate when the cross-coupled stage composed from Q1,
Q3, Q5 and Q6 cannot start. Therefore, the speed of proposed
idea is more than paper [12]. In order to enhance the voltage
difference between the output terminals, the cross-coupled
inverters provide strong positive feedback in the phase 2.The
transition state changes from phase 2 into phase 3 when one
of the transistors Q14 and Q15 is cut-off. There is no static
power dissipation since the current flows through these
n-channel MOSFETs stop automatically after the transition.
Fig. 3 shows transient behavior of the proposed dynamic
comparator at 1GHz. As seen, both of the output terminals
are pulled low in the beginning of the compare operation.
One of the output terminals charge through the p-channel
Fig. 3. Simulated transient behavior of the proposed comparator structure. transistor when the transition goes from phase 1 into phase 2.
Therefore, the strong positive feedback provided by these
 Journal of Electrical and Electronic Engineering 2015; 3(4): 93-96 95

two cross-coupled inverters separates the output voltages. better. The energy dissipation is 2.5fJ/decision at Clk=1GHz
Against paper [12], this design aren’t use from p-wells, thus and ΔVin=1.5V. That is very better than 71, 88 and
the cost of comparator chip is lower. 90fJ/decision in [12], [14]-[15], respectively. Table I
summarizes the specifications of proposed dynamic
comparator. We demonstrate that our comparator structure has
3. Simulation Results the best delay/log (ΔVin) and energy/decision performance in
comparison with recent publications [12], [14]-[16].

Fig. 4. Simulated Resolution voltages versus Sampling Frequency at 1.5V

supply voltage.
Fig. 6. Simulated Power Consumption versus Sampling Frequency at 1.5V
supply voltage.

Fig. 5. Simulated DC Power Supply versus Sampling Frequency.

Fig. 7. Simulated delay of different dynamic comparators versus differential
The comparator is designed in IBM 130nm CMOS process input voltage. The delay is the time between clock edge and differential output
with 1.5V low threshold voltage device model (Vt≈0.3V). The signal of comparator crosses at 1/2 supply voltage.
resolution voltage (difference between input signals) versus
sampling frequency is shown in Fig. 4. According to this
Figure, resolution voltage is changing in range of 4MHz to
10GHz from 2µv to 700mv. The dc power supply versus
sampling frequency is shown in Fig. 5. According to this
figure, the minimum supply voltage is 250mv and maximum
supply voltage is 1.5V. The power consumption versus
sampling frequency is shown in Fig. 6. According to this
figure, the minimum power consumption is 110nw at 4-MHz
and maximum power consumption is 146µw at 10-GHz.
According to simulation results, the delay versus CMOS
differential input voltage (resolution) is shown in Fig. 7. The
delay/log(ΔVin) in this figure is 10-ps/dec. Fig. 8 and Fig. 9
summarized the simulation results of delay and
energy/decision versus input common-mode voltage,
respectively. The delay of the proposed structure is also
Fig. 8. Simulated delay versus input common mode voltage at 1-GHz and
insensitive to input common-mode voltage (Vcm) that is the 1.5V supply voltage.
same as [15]. According to figure 8, the input common voltage
is dual-rail because the range of common mode is between 0.1
to 1.1V. Therefore the proposed paper than papers [12] is very
96 M. Dashtbayazi et al.: Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

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