Reference Methodology Updates

T-2022.03-SP4

October 2022
Agenda
• set_qor_strategy Update
• Fusion Reference Library Support
• Log Parser
• Library Setup file
• Report_qor.tcl runtime improvements
• FM script alignment with platform RM
• Update to read_saif
• hyper_route_opt PBA/GBA support
• HPC Core Support (FC-RM specific)
• Updates to compile.tcl (FC-RM specific)
• Netlist to GDS Flow (FC-RM specific)
• report_qor.tcl and rm_report_qor
• Makefile "view" Target
• configureRM
• General RM Script Updates
• Makefile Usage Updates (FC-RM specific)
• Design Planning Updates

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set_qor_strategy
Overview
Example : FC-RM • The set_qor_strategy is a mega switch used in the RM to easily and quickly
apply the best-known recipe settings for the design
init_design
– After selecting a single metric target of timing, leakage_power, or total_power,
set_qor_strategy apply a focused recipe to optimize the design
set_technology –node $node
– In addition to the target metric set_qor_strategy can adjust the recipe based on the
mode selected
set_qor_strategy –stage synthesis –metric
timing/total_power/leakage_power • There are two stages for set_qor_strategy to apply metric targeted strategies
-mode balanced/early_design/easy*/extreme_power
for synthesis and place and route
set_stage –step synthesis – The stage synthesis is enabled to apply settings recipes before compile_fusion
compile_fusion –to initial_opto
set_stage –step compile_place
– The stage pnr enables the metric target for the flow after compile_fusion and before
compile_fusion –from final_place
clock_opt
– Changing the metric and mode of SQS is restricted to only certain points in the flow.
set_qor_strategy –stage pnr –metric
timing/total_power/leakage_power – In FC for SQS -stage synthesis the metric and mode are unrestricted prior to initial_place
-mode balanced/early_design/easy*/exteme_power
– In FC for SQS -stage pnr the metric and mode are unrestricted prior to clock_opt
set_stage –step cts – In ICC II, SQS –stage pnr the metric and mode are unrestricted prior to initial_place
clock_opt –from build_clock –to route_clock
• In the fc_setup file, you can specify the metric and mode target for your design
set_stage –step post_cts_opto with the RM tcl variables $SET_QOR_STRATEGY_METRIC and
clock_opt –from final_opto $SET_QOR_STRATEGY_MODE
set_stage –step route – The default metric target in T-2022.03-SP3 is timing
route_auto – The default mode in T-2022.03-SP3 is balanced
set_stage –step post_route
route_opt

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set_qor_strategy
Tiered recipes
• set_qor_strategy –mode enables tool engines to make additional configurations to support the
following flow modes

Mode Description
early Meant for customers with early/dirty collateral. Will have Early Data Check set to lenient mode + additional bailout mechanis ms to get
much faster (close to 2X) runtime and slightly worse PPA

easy (hidden) Meant for Faster TAT, can trade-off QoR for runtime

balanced Default mode. Applicable to most customers/designs.

extreme_power Meant for customers who don't mind spending a bit more runtime for better timing and power

– Easy mode is currently hidden. In a future release, the plan is to tie easy mode to low_effort mode and make the
option public
– Extreme_power does not work with –metric timing. Tool automatically switches to balanced mode

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Fusion Reference Library Support

• In the previous release, RM supports CLIB as reference library for the design library creation. You would specify a list of
CLIB reference libraries using the RM variable REFERENCE_LIBRARY, and then init_design.tcl during design library
creation adds them as reference library.

• In this release, support for fusion reference library has been added.
A. If you already have fusion reference library created, with this enhancement, you will be able to provide either just CLIB, just fusion
library, or both as reference library using the RM variable REFERENCE_LIBRARY in a list. There's no impact on existing CLIB
reference library users
– In design_setup.tcl, simply specify the list of fusion reference library using the existing REFERENCE_LIBRARY variable
B. If you don't have fusion library yet, but have the necessary FRAMs and DBs, RM supports fusion library creation as an optional step
using FRAMs and DBs. You can run this step before init_design to create fusion referebce library first. The steps are shown below:
1. In design_setup.tcl, specify FRAMs and DBs using the new variable FUSION_REFERENCE_LIBRARY_FRAM_LIST and
FUSION_REFERENCE_LIBRARY_DB_LIST, respectively.
2. Run makefile with target create_fusion_reference_library to create fusion reference library.
– In the makefiles, a new optional target create_fusion_reference_library is added for fusion library creation
– The step sources the new script create_fusion_reference_library.tcl to run lc_sh to create fusion reference libraries using FRAMs and DBs.
– Once the step is completed. Fusion library is created under the directory specified by $FUSION_REFERENCE_LIBRARY_DIR
3. Run makefile with init_design target. init_design.tcl during design library creation checks for the existence of $FUSION_REFERENCE_LIBRARY_DIR,
and if it is found, the fusion reference libraries within the directory is added to as reference library.

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Fusion Reference Library Support

• Script changes related to on-the-fly fusion reference library creation

– New variables
– FUSION_REFERENCE_LIBRARY_FRAM_LIST - a list of frames (or ndm) for on-the-fly fusion reference library creation; ex : "[glob /path1/std/ndm/*.ndm
/path2/sram/ndm/*.ndm]"
– FUSION_REFERENCE_LIBRARY_DB_LIST - a list of dbs for on-the-fly fusion reference library creation; ex : "[glob /path1/std/db/*.db /path2/sram/db/*.db]"
– FUSION_REFERENCE_LIBRARY_DIR - fusion library output directory from Makefile's create_fusion_reference_library target; default is "./local_fusion_library"
– Script changes
– New makefile target create_fusion_reference_library which runs create_fusion_reference_library.tcl
– New script create_fusion_reference_library.tcl to run lc_sh to create fusion reference libraries using FRAMs and DBs
– Init_design.tcl is updated to check for the existence of $FUSION_REFERENCE_LIBRARY_DIR, and if it is found, the fusion reference libraries within the directory are
added as reference library
• The user interface for existing CLIB on-the-fly creation (library configuration flow) has been updated
– If you don't have CLIB but have necessary FRAMs and DBs, you can specify FRAMs and DBs using dedicated variables
CLIB_REFERENCE_LIBRARY_CONFIGURATION_FLOW_FRAME_LIST and
– CLIB_REFERENCE_LIBRARY_CONFIGURATION_FLOW_DB_LIST, and init_design.tc during design library creation will call library manager to create CLIB
using the specified FRAMs ann DBS and add them as reference library
– Note that using fusion reference library disqualifies the use of on-the-fly CLIB creation
– If you have fusion library specified, do not specify CLIB_REFERENCE_LIBRARY_CONFIGURATION_FLOW_FRAME_LIST or
CLIB_REFERENCE_LIBRARY_CONFIGURATION_FLOW_DB_LIST

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Log Parser and Error Detection Enhancement

• Log parser utility is made available in 2022.03-SP3 RM to help capture and report summary of
tool and RM-error and RM-warnings in the current session

• At the end of each RM stage script, the log parser is called to parse the log file of the current
stage and output a summary of RM log file messages.
– Goal is to bring the user’s attention to errors and warnings early in the flow (init_design/compile)
– Parser writes out a summary table of error messages found in the log
– Parser provides the line number of the error message and indicate if the error occurred while sourcing a
plug-in script
– Context can help facilitate the debug process narrowing down where and why an error was issued

• The output of the log parser is captured at the end of the logfile that is being parsed so that the
user can locate the information more easily by scrolling directly to the end of the log

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Log Parser and Error Detection Enhancement

• At the end of each stage script the rm_logparse command is called to parse the log

• Sample output from the log parse utility

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Library Setup Plugin

• In SP3 RM will have a dedicated hook to load a

library setup file.
– New plugin TCL_USER_LIBRARY_SETUP_SCRIPT
can be defined in design_setup.tcl

• The library setup script can be used to setup

information related to technology, reference library,
stream files, and link libraries, for example

• In past RM releases the

TCL_USER_INIT_DESIGN_PRE_SCRIPT was
being used to load this file. We have added a
separate hook allowing users to use the
init_design prescript

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report_qor
Runtime Improvement
• T-2022.03-SP3 RM report_qor enhancements based on findings and feedback from the
field/customer
– route_auto Non-SI reporting is now optional. It is controlled by the variable REPORT_DEBUG found in
design_setup.tcl. Default is off

– Clock power reporting to be variable controlled. Set REPORT_CLOCK_POWER in design_setup.tcl

to "true" to enable report_clock_qor -type power during reporting
– Clock power is reported only after CTS and route_opt stages. Default is off

– Reorder reporting commands in report_qor.tcl so that critical reports are executed first, i.e., timing
reports

– Updated all timing related commands to report only for active scenarios

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report_qor

• New variables in design_setup.tcl to allow user to specify which scenarios

must be active and used for reporting
– REPORT_COMPILE_ACTIVE_SCENARIO_LIST
– REPORT_PLACE_OPT_ACTIVE_SCENARIO_LIST
– REPORT_CLOCK_OPT_CTS_ACTIVE_SCENARIO_LIST
– REPORT_CLOCK_OPT_OPTO_ACTIVE_SCENARIO_LIST
– REPORT_ROUTE_AUTO_ACTIVE_SCENARIO_LIST
– REPORT_ROUTE_OPT_ACTIVE_SCENARIO_LIST
– REPORT_CHIP_FINISH_ACTIVE_SCENARIO_LIST
– REPORT_ICV_IN_DESIGN_ACTIVE_SCENARIO_LIST
– REPORT_ENDPOINT_OPT_ACTIVE_SCENARIO_LIST
– REPORT_TIMING_ECO_ACTIVE_SCENARIO_LIST

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Running Formality in FC/ICC2 RM
Alignment with FM RM
• In T-2022.03-SP3 RM release, the formality run script provided with the FC and ICC II RMs will
now be the same FM run script provided with the FM RM

• The FM fm_r2g.tcl script is more complete and offers additional tool configuration options that
are not supported with the script provided in past RM releases.
• Running FM through the FC RM makefile will have the same feel as running the FM RM makefile
– Usage model consistency will make FM RM adoption/transition smoother
– Utilizes the same support files: fm_setup.tcl, header_fm.tcl

• With the script alignment formal verification will work off the native NDM and does not require any
netlisting out

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Running Formality in FC/ICC2 RM
Makefile Example

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Update to read RTL SAIF
reset_switching_activity
• init_design.tcl

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route_opt PBA/GBA

• fc_setup.tcl/ icc2_pnr_setup.tcl

• route_opt.tcl
• PBA

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hyper_route_opt PBA/GBA support

• In fc_setup.tcl/ icc2_pnr_setup.tcl, a new variable is added to toggle PBA on/off before the
hyper_route_opt command

• In route_opt.tcl
– The set_stage -step post_route command reads the value of the variable and enable PBA
– If you set it to false, PBA is disabled

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HPC Core Support (FC-RM specific)

• ASG provides a core specific bundle

• The sidefile_setup_hpc_core.tcl file defines the values of variables used in the RM scripts
to implement the HPC core recipe

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HPC Core Support (FC-RM specific)

• Example of HPC specific variables used in compile.tcl

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compile.tcl Updates (FC-RM specific)
• Standard preamble of the compile.tcl script. These items are evaluated
whenever the compile.tcl script is run. Preamble
– Check to enable early_design mode settings
pre-initial map
– check_stage_settings command
– Check and marking of clock network as ideal
initial map

• TCL_MODE_CORNER_SCENARIO_MODEL_ADJUSTMENT_FILE now sourced before logic optimization

hold scenario check is performed

insert_dft
• Additional user plug-ins added
• TCL_USER_COMPILE_INITIAL_MAP_POST_SCRIPT initial_place

• TCL_USER_COMPILE_LOGIC_OPTO_PRE_SCRIPT
initial_drc
• TCL_USER_COMPILE_LOGIC_OPTO_POST_SCRIPT
• TCL_USER_DFT_REPLACEMENT_SCRIPT initial_opto

• TCL_USER_DFT_POST_SCRIPT
final_place

• Standard postlude of the compile.tcl script. These items are evaluated whenever the final_opto
compile.tcl script is run.
– TCL_USER_CONNECT_PG_NET_SCRIPT or connect_pg_net
– change_names -rules verilog -hierarchy -skip_physical_only_cells Postlude
– Re-enable power analysis if disabled for set_qor_strategy -metric leakage_power*
– write_ascii_files and write saif map
– Create abstract and frame *Fixes bug found in SP3 RM scripts
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 Netlist to GDS flow (FC-RM specific)

• FC-RM now supports gate level netlist input (INIT_DESIGN_INPUT =

FC-RM Makefiles
ASCII) or write_icc2_files output from DC (INIT_DESIGN_INPUT =
DC_ASCII)
– The flow is similar to ICC2-RM flow which runs place_opt.tcl in place of
compile.tcl but with fc_shell as the executable

• How to enable Netlist to GDS flow

1. In design_setup.tcl
a) Set NETLIST2GDS_FLOW to true
b) Set INIT_DESIGN_INPUT to either ASCII, or DC_ASCII
o For ASCII, specify VERILOG_NETLIST_FILES with your gate level netlist input Makefile_netlist2gds
o For DC_ASCII, provide Makefile
${DCRM_RESULTS_DIR}/${DCRM_FINAL_DESIGN_ICC2}/${DESIGN_NAME}.icc2_script.tcl Makefile_handoff
as your design input Makefile_third_party_dft

2. Run Makefile_netlist2gds
o Notice that the flow runs place_opt.tcl instead of compile.tcl

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report_qor.tcl and rm_report_qor

• report_qor.tcl script no longer relies on the block name to determine which reports to execute
– Enabled re-use of the reporting script and for interactive reporting
– Each stage script will set the REPORT_STAGE variable which determines which reports to generate
– Another variable, REPORT_ACTIVE_SCENARIOS, is used to pass a list of scenarios to activate for reporting in each
stage script

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report_qor.tcl and rm_report_qor
• A new proc rm_report_qor is now provided as part of the RM through procs_fc.tcl or procs_icc2.tcl
– Allows the user to execute the report_qor.tcl script as a procedure.
– User can control the reporting behavior by providing arguments that map to the same variables defined in design_setup.tcl
– Facilitates reporting from a standalone session. Through the proc the RM setup files can be loaded to prepare the environment for
reporting

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Makefile "view" Target

• Added a new makefile target "view" for opening an RM saved block or a user saved block in an interactive session
• Required input : VIEW_BLOCK_NAME, which is a variable in the makefiles
• Usage
1. Specify VIEW_BLOCK_NAME with a block name, either in the <design name>/<label> format, such as "RISC_CORE/init_design", or
without using a label, such as "test1"
– Note that RM's saved block format is always $DESIGN_NAME/<stage name>. So if the DESIGN_NAME is RISC_CORE and the stage is init_design,
and you want to open the final saved block from this task, you should specify RISC_CORE/init_design as the VIEW_BLOCK_NAME

2. It is recommended to specify the value of VIEW_BLOCK_NAME when running make so there is no edit needed in the makefile. Here
is the usage example:
– make -f rm_setup/Makefile view VIEW_BLOCK_NAME=RISC_CORE/init_design
– where view is the makefile target, RISC_CORE/init_design is the name of the saved block which you want to open, and
VIEW_BLOCK_NAME=RISC_CORE/init_design is the syntax to specify a value for VIEW_BLOCK_NAME when running make

3. The view target runs a new script view.tcl which opens the design library as specified by the RM variable DESIGN_LIBRARY in
the design_setup.tcl, and the block name as specified by VIEW_BLOCK_NAME
– It also sources RM utility, RM setup files, and sources TCL_USER_NON_PERSISTENT_SCRIPT as specified in design_setup.tcl

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configureRM Initial
Version
• configureRM is a new utility that is provided in the rm_utilities directory to help the user
configure their design_setup.tcl and fc_setup.tcl/icc2_pnr_setup.tcl
• The utility provides a GUI interface that users can use to populate the different variables in the
setup files
• The variables have been organized and categorized to guide the user from initial design setup,
flow step configuration, and advanced flow customization

• How to use configureRM from scratch:

1. cd rm_utilities/
2. From the unix prompt type "configureRM". This will bring up the GUI. The GUI is populated with
variables from design_setup.tcl and fc_setup.tcl/icc2_pnr_setup.tcl.
o In rm_utilities/ there are local copies of design_setup.tcl and fc_setup.tcl or icc2_pnr_setup.tcl.
o These copies serve as templates with improved categories and ordering the variables in the GUI.
3. Fill in the fields for each of the variables with the desired values.
4. When the GUI is populated, to commit the edits and write out updated files click the Save button. By
default, the utility writes out /design_setup.tcl.<processId> and ./fc_setup.tcl.<processId> -or-
./icc2_pnr_setup.tcl.<processId> to rm_utilities/. The new files will be written out in the same format
as the templates.
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configureRM GUI Rendition

VARIABLE NAME

Comments related to below VARIABLE

VARIABLE VALUE editable

Save Changes to Output file

ALL ^set VARs in this TAB are listed in
GENERAL section
Check if changes were made to variables and
not saved. Prompt User to save changes and
Exit Program

TABS of Notebook, captured from Section Headers & Sections

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configureRM
Migrating previous RM setup
• How to use configureRM to migrate design_setup.tcl from previous RM release:
1. cd rm_utilities/
2. From the unix prompt type "configureRM --input user_design_setup.tcl". This action brings up the GUI. The GUI is
populated with variables defined from user_design_setup.tcl.
o Similarly, a previous version of fc_setup.tcl/icc2_pnr_setup.tcl can be provided
3. Update any fields for each of the variables with the desired values.
4. When the GUI is populated, to commit the edits and write out updated files select the "save" button. By default the
utility will write out /design_setup.tcl.<processId> or ./fc_setup.tcl.<processId> -or- ./icc2_pnr_setup.tcl.<processId>
to rm_utilities/. The new files will be written out in the same format as the templates.
• Note: To migrate old versions of fc_setup.tcl or icc2_pnr_setup.tcl
Add to header of file

• Migration from T-2022.03-SP3 to T-2022.03-SP4

– New variables only, No variables renamed
• Migration from T-2022.03 to T-2022.03-SP4
– In design_setup.tcl some user plugin script names were modified to follow a consistent naming convention
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General RM Script Updates
rm_documents
• rm_documents directory
– A new directory called rm_documents is added to the RM release
– All release notes and readme files are moved under rm_documents

– Consistent user plugin naming convention

– i.e. compile_pre_initial_opto_script.tcl changed to compile_initial_opto_pre_script.tcl

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General RM Script Updates
RM Variable changes - applicable to both FC-RM and ICC2-RM
Variable Name Added / Removed Description
FUSION_REFERENCE_LIBRARY_FRAM_LIS T Added a list of frames (or ndm) for on-the-fly fusion reference library creation
FUSION_REFERENCE_LIBRARY_DB _LIS T Added a list of dbs for on-the-fly fusion reference library creation
FUSION_REFERENCE_LIBRARY_DIR Added fusion library output directory from Makefile's create_fusion_reference_library target; default
is "./local_fusion_library"
PARASITIC_TECH_LIB Added Specifies one library as a dedicated parasitic technology library. This is automatically added
to the create_lib -ref_libs list
PHYSICAL_RULES_FILE Added Specify a file in PRF format which specifies tech/library physical rules and attributes
ENABLE_FLOORPLAN_CHECKS Added Enables floorplan checks performed by rm_check_design during init_design stage
ICV_IN_DESIGN_ENABLE_ALL_LAYER_CHECK Added Disables all layer checks to limit false errors from missing layout
ICV_IN_DESIGN_ADR_SELE CT_RULES Added Specify the non DPT rules to be fixed by ADR
ICV_IN_DESIGN_METAL_FILL_COORDINA TES Added Specify the coordinates to be filled. By default, the entire design will be filled.
CHIP_FINISH_FROM_BLOCK_NAME Added Allows you to choose a different starting block other than the default
$ROUTE_OPT_BLOCK_NAME
ENDPOINT_OPT_FROM_BLOCK_NAME Added Allows you to choose a different starting block other than the default
$ROUTE_OPT_BLOCK_NAME
TCL_USER_FLOORPLAN_PRE_S CRIPT Added RM user plugin to be sourced at the beginning of floorplan.tcl
TCL_USER_FLOORPLAN_POS T_SCRIP T Added RM user plugin to be sourced at the end of floorplan.tcl

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General RM Script Updates
RM Variable changes - applicable to both FC-RM and ICC2-RM
Variable Name Added / Removed Description
ENABLE_INLINE_REPORT_QOR Added Enables inline intermediate report_qor calls during the implementation flow
REPORT_DEBUG Added generates non-SI timing reports during route_auto stage
REPORT_CLOCK_POWER Added Enables report_clock_qor -type power after clock_opt_cts and route_opt stages
REPORT_PLACE_OPT_ACTIVE_SCENARIO_LIS T Added A subset of scenarios to be made active when generating reports for the specific stage
REPORT_CLOCK_OPT_CTS_A CTIVE_SCE NARIO_LIS T Added
REPORT_CLOCK_OPT_OP TO_A CTIVE_SCE NARIO_LIS T Added
REPORT_ROUTE_AUTO_ACTIVE_SCENA RIO_LIST Added
REPORT_ROUTE_OPT_ACTIVE_SCE NARIO_LIS T Added
REPORT_CHIP_FINIS H_ACTIVE_SCENA RIO_LIST Added
REPORT_ICV_IN_DESIGN_A CTIVE_SCE NARIO_LIS T Added
REPORT_ENDPOINT_OP T_A CTIVE_SCE NARIO_LIS T Added
REPORT_TIMING_ECO_ACTIVE_SCENARIO_LIS T Added
REPORT_FUNCTIONAL_E CO_ACTIVE_SCENA RIO_LIST Added

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General RM Script Updates
RM Variable changes – FC-RM specific
Variable Name Added / Description
Removed
TCL_USER_DFT_REPLACEMENT_SCRIPT Added User provided DFT insertion script. When provided, the out of the box insert
DFT flow is bypassed
NETLIST2GDS_FLOW Added Specify true if your design input is gated netlist (INIT_DESIGN_INPUT = ASCII)
or write_icc2_files output from DC (INIT_DESIGN_INPUT = DC_ASCII)
VERILOG_NETLIST_FILES Added If NETLIST2GDS_FLOW is set to true, for gated netlist input (if
INIT_DESIGN_INPUT = ASCII)
DCRM_RESULTS_DIR and DCRM_FINAL_DESIGN_ICC2 Added If NETLIST2GDS_FLOW is set to true, for gated netlist input (if
INIT_DESIGN_INPUT = DC_ASCII)
TCL_USER_COMPILE_INITIAL_MAP_POST_SCRIPT Added New RM user plugin scripts for the specific stage
TCL_USER_COMPILE_LOGIC_OPTO_PRE_SCRIPT Added
TCL_USER_COMPILE_LOGIC_OPTO_POST_SCRIPT Added
TCL_USER_DFT_POST_SCRIPT Added
TCL_USER_PLACE_OPT_INCREMENTAL_PLACEMENT_ Added
POST_SCRIPT
RTL_READ_FORMAT Removed RTL_READ_FORMAT is renamed to RTL_SOURCE_FORMAT

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General RM Script Updates
PREVIOUS_STEP / CURRENT_STEP mechanism
• Implemented a PREVIOUS_STEP / CURRENT_STEP mechanism
• Benefits: Scripts become more modular making them easier to re-use for different purposes.
– Compile script re-use for frontend centric flow, third party DFT, integrated floorplanning flow, NDM
management, ideal clock flow
– These two variables are defined in each stage script with default values as part of the default FC -
RM/ICC2-RM flow. They are used to determine the current and previous stage for each stage script
locally.
– Non-default PREVIOUS_STEP settings are set by the appropriate Makefile, depending on the flow that
is being run by the Makefile.
– Utilize RM_VARFILE mechanism in Makefiles to provide PREVIOUS_STEP override.
– When CURRENT_STEP and PREVIOUS_STEP are updated, the new values are passed from the Makefile to the
stage script through the <stage>.varfile, where <stage> is the stage name/Makefile target.
– The <stage>.varfile is then sourced by the stage script after where CURRENT_STEP and PREVIOUS_STEP are
defined in the stage script to override the default values per the flow requires.
– Resolved values for PREVIOUS_STEP & CURRENT_STEP are echoed to the logfiles.

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PREVIOUS_STEP / CURRENT_STEP mechanism
RM_VARFILE Example

compile.tcl Makefile with RM_VARFILE

Default definition

RM_VARFILE

Definition Echoed

current_block opened

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General RM Script Updates
Prelude and Postlude
• Standard script start up and shutdown
– All stage scripts now check and source the RM_VARFILE as part of the script start up.
– All stage scripts include report_msg -summary as part of the script shutdown.

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Makefile Usage Updates
FC-RM Specific
No Makefile name Purpose Note
1 Makefile Default FC-RM for monolothic or DFT centric flow
2 Makefile_handoff Alternative FC-RM to facilitate the handoff of a design from synthesis to
place and route
3 Makefile_third_party_dft Alternative FC-RM which runs the third party dft flow
4 Makefile_netlist2gds new Alternative FC-RM for netlist2gds flow • place_opt executed from FC
5 Makefile_pnr_discrete_fp_steps Alternative FC-RM which runs discrete DP steps • This option allows for optimal floorplan interaction and
• Runs autofloorplanning thru "logic_opto", implements floorplanning via debug
separate steps, then picks up compile from "insert_dft" and runs through rest • If you have finished standalone DP RM
of PNR steps. (Makefile_dp_flat), do not use this Makefile as DP has
new been completed.
6 Makefile_pnr_single_fp_steps Alternative FC-RM which runs DP in a single step • This option is better suited for replay once the floorplan
• Runs autofloorplanning through "logic_opto", implements floorplanning in a parameters have been established
single step, then picks up compile from "insert_dft", and runs thorugh rest of • If you have finished standalone DP RM
PNR steps. (Makefile_dp_flat), do not use this Makefile as DP has
new been completed.
7 Makefile_dp_flat Default Flat DP RM • Standalone DP RM
• After this is done, continue with PNR Makefiles No.1,
2,3, or 4. Do not continue with 5 or 6.
8 Makefile_dp_hier Default Hier DP RM
9 Makefile_dp_flat_netlist2gds Alternative flat DP RM for netlist2gds flow • Standalone DP RM
• After this is done, continue with PNR Makefiles No.1,
new 2,3, or 4. Do not continue with 5 or 6.
10 Makefile_dp_hier_netlist2gds new Alternative hier DP RM for netlist2gds flow
Synopsys Confidential Information © 2022 Synopsys, Inc. 35
Agenda
• set_qor_strategy Update
• Fusion Reference Library Support
• Log Parser
• Library Setup file
• Report_qor.tcl runtime improvements
• FM script alignment with platform RM
• Update to read_saif
• hyper_route_opt PBA/GBA support
• HPC Core Support (FC-RM specific)
• Updates to compile.tcl (FC-RM specific)
• Netlist to GDS Flow (FC-RM specific)
• report_qor.tcl and rm_report_qor
• Makefile "view" Target
• configureRM
• General RM Script Updates
• Design Planning Updates

Synopsys Confidential Information © 2022 Synopsys, Inc. 36

Traditional RM Flat Design Planning Flow through Compile
Design input Design input (PNR)

initial_map/logic_opto Pre-initial map

Floorplan initialization Initial map

VA creation Logic optimization

Auto macro place Insert_dft

PO cell insertion Initial_place

PG Grid Creation Initial_drc

Coarse stdcell place Initial_opto
Pin placement Final_place
Write DP data
Final_opto
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Design Planning Update
Flat Floorplanning embedded in PNR Design input (PNR)
create_floorplan.tcl Pre-initial map floorplan.tcl
Floorplan initialization
Initial map/logic_opto Floorplan initialization
VA creation
VA creation
Auto macro place floorplan
Auto macro place
PO cell insertion Insert_dft
PO cell insertion
create_power.tcl Initial_place
PG Grid Creation
PG Grid Creation
Initial_drc
Coarse stdcell place
Coarse stdcell place
Initial_opto Pin placement
place_pins.tcl
Pin placement Final_place

Final_opto Makefile_pnr.single_fp_step
Makefile_pnr.discrete_fp_steps
Synopsys Confidential Information © 2022 Synopsys, Inc. 38
Design Planning RM 2022.03-SP4
Floorplanning embedded in PNR
Makefile_pnr.discrete_fp_steps
• Added two new flows which embed floorplan creation into the
PNR flow
– Makefile_pnr.discrete_fp_steps
– Makefile_pnr.single_fp_step
• Run compile_fusion through logic_opto using auto-
floorplanning constraints
• Build the floorplan using the RM flat DP collateral
• Run compile_fusion from insert_dft through
final_opto
• The difference between the two Makefiles is how floorplanning
is performed
– Makefile_pnr.discrete_fp_steps ➔ Runs the flat DP scripts as
separate steps providing optimal floorplan iteration and debug
opportunities
– Makefile_pnr.single_fp_step ➔ Runs the entire floorplanning via a
single step and tool invocation. This is better suited for replay
once the floorplan parameters have been established

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Design Planning RM 2022.03-SP4
General Updates
• Added support for netlist input into FC DP flows.
– FC flows will now support both RTL and Netlist input formats.
– Makefiles were added to support the netlist input mode.
– Makefile_dp_flat_netlist2gds
– Makefile_dp_hier_netlist2gds
– Input mode is controlled by the new RM variable "NELIST2GDS_FLOW".
– set NETLIST2GDS_FLOW “true”
• Implemented a PREVIOUS_STEP / CURRENT_STEP mechanism
in the DP flows.
– PREVIOUS_STEP script defaults are set in the flow scripts.
– Non-default PREVIOUS_STEP settings have been moved to the
appropriate Makefiles.
– Utilize RM_VARFILE mechanism in Makefiles to provide
PREVIOUS_STEP override.
– Resolved values for PREVIOUS_STEP & CURRENT_STEP are echoed
to the logfiles.

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Design Planning RM 2022.03-SP4
General Updates
• Added standardized RM header & footer collateral to each DP script
– redirect -tee -file ${REPORTS_DIR}/${REPORT_PREFIX}/run_start.rpt {run_start}
– redirect -tee -file ${REPORTS_DIR}/${REPORT_PREFIX}/run_end.rpt {run_end}
– write_qor_data -report_list "performance host_machine report_app_options"
– report_msg -summary
• A create_fusion_library target was added in each of the Makefiles
– This is an optional step which creates fusion libraries
– Fusion libraries are automatically consumed if created
– The libraries defined via REFERENCE_LIBRARY are used when this target is skipped
• A view target was added to each of the Makefiles
– Opens a previously saved block in an interactive session

Synopsys Confidential Information © 2022 Synopsys, Inc. 41

Design Planning RM 2022.03-SP4
Flat flow scripts
• init_design_dp.tcl
– Code restructuring in support of both RTL and netlist input modes
– Added Parasitic Tech support via PARASITIC_TECH_LIB
– Added Fusion Library support
– Source a post RTL script via TCL_USER_READ_RTL_POST_SCRIPT
– Source a library setup file via TCL_USER_LIBRARY_SETUP_SCRIPT
– Source a PRF via PHYSICAL_RULE_FILE
• create_floorplan.tcl
– Moved sourcing of SIDEFILE_INIT_DESIGN outside of initialize_floorplan conditional so it will always get sourced
– Source a power switch sleep connectivity file via SWITCH_CONNECTIVITY_FILE
– Added check for unplaced ports after port placement
• create_power.tcl
– Updated stdcell placement in the STDCELL_PLACEMENT operation
– Prior code with -floorplan removes placement blockages inserted by fix_floorplan_rules
• place_pins.tcl
– Added floorplanning checks at the end of this script as the floorplan is completed at that point
– Source a new technology sidefile via SIDEFILE_PLACE_PINS
– Added the option to apply fixed status to placed ports
– Added check for unplaced ports after port placement

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Design Planning RM 2022.03-SP4
Hierarchical flow scripts
• split_constraints.tcl
– Source a library setup file via TCL_USER_LIBRARY_SETUP_SCRIPT
• init_dp.tcl
– Added Parasitic Tech support via PARASITIC_TECH_LIB
– Added Fusion Library support
– Source a post RTL script via TCL_USER_READ_RTL_POST_SCRIPT
– Source a library setup file via TCL_USER_LIBRARY_SETUP_SCRIPT
– Source a PRF via PHYSICAL_RULE_FILE
• commit_blocks.tcl
– Source a split_constraints setup file via TCL_SPLIT_CONSTRAINTS_SETUP_FILE
• create_floorplan.tcl
– Moved sourcing of SIDEFILE_INIT_DP_TECH_SETTINGS outside of initialize_floorplan
conditional so it will always get sourced
– Source a custom floorplanning file via TCL_PHYSICAL_CONSTRAINTS_FILE

Synopsys Confidential Information © 2022 Synopsys, Inc. 43

Design Planning RM 2022.03-SP4
Hierarchical flow scripts
• init_compile.tcl
– Added connect_pg_net to connect PG pins of any added cells
• place_pins.tcl
– Added usage of BLOCK_ABSTRACT_TIMING_LEVEL to create_abstract command
– Source a new technology sidefile via SIDEFILE_PLACE_PINS
– Added the option to apply fixed status to top-level and block ports
– Check for unplaced ports after port placement
• top_compile.tcl
– Added usage of BLOCK_ABSTRACT_TIMING_LEVEL to create_abstract command
– Added connect_pg_net to connect PG pins of any added cells
• timing_budget.tcl
– Added usage of BLOCK_ABSTRACT_TIMING_LEVEL to create_abstract commands
– Added usage of COMPUTE_BUDGET_CONSTRAINTS_OPTIONS for compute_budget_constraints
command line options

Synopsys Confidential Information © 2022 Synopsys, Inc. 44

Design Planning RM 2022.03-SP4
Variable updates (fc_dp_setup.tcl / icc2_dp_setup.tcl)
Variable Name Added / Removed Description

INITIALIZE_FLOORPLAN_CUSTOM_OPTIONS Added Provides user flexibility for "initialize_floorplan"

BLOCK_ABSTRACT_TIMING_LEVEL Added Specifies timing detail for create_abstract

TCL_SPLIT_CONSTRAINTS_SETUP_FILE Added Specifies any constraints or options to support split_constraints

COMPUTE_BUDGET_CONSTRAINTS_OPTIONS Added Specifies custom options for compute_budget_constraints

FIX_PORT_PLACEMENT Added Enables port fixing

TCL_UPF_FILE Removed No longer used

FAST_COMPILE_HPC_BLOCK_NAME Added Hierarchical HPC Flow

TCL_USER_FAST_COMPILE_HPC_PRE_SCRIPT Added Hierarchical HPC Flow

TCL_USER_FAST_COMPILE_HPC_POST_SCRIPT Added Hierarchical HPC Flow

FAST_COMPILE_HPC_ACTIVE_SCENARIO_LIST Added Hierarchical HPC Flow

DESIGN_PLANNING_HPC_BLOCK_NAME Added Hierarchical HPC Flow

TCL_USER_DESIGN_PLANNING_HPC_PRE_SCRIPT Added Hierarchical HPC Flow

TCL_USER_DESIGN_PLANNING_HPC_POST_SCRIPT Added Hierarchical HPC Flow

Synopsys Confidential Information © 2022 Synopsys, Inc. 45

Thank You