Pulsed Latch Timing Analysis

Product Version: Tempus 15.1

October, 2015
 Pulsed Latch Timing Analysis

Contents
Introduction .................................................................................................................. 3
Library Cells Required for Pulsed Latch Design .......................................................... 3
Modeling Pulse Generator in Timing Library ................................................................ 5
Timing Analysis for Pulsed Latch Design ................................................................... 10
Constraints ................................................................................................................ 13
Example: Pulse Clock Filtering............................................................................... 16
Support ...................................................................................................................... 21
Feedback ................................................................................................................... 21

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 Pulsed Latch Timing Analysis

Introduction
This document describes the Pulsed Latch Timing Analysis supported in Tempus. It
covers:
• Modeling pulse generator using standard Liberty timing library constructs
• Different aspects of analyzing timing paths related to pulsed latches

Library Cells Required for Pulsed Latch Design

There are three types of standard cells that need to be provided by the
library vendor:

o Regular latch cell mapped to each FF cell

o Pulse generator that could generate pulse clock waveform

with source clock

o Clock dummy buffer cell with exactly the same delay as

pulse generator

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 Pulsed Latch Timing Analysis

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 Pulsed Latch Timing Analysis

Modeling Pulse Generator in Timing Library

The following liberty pin level attribute, defined on the output pin, signifies the cell as a
pulse generator:
pulse_clock : pulse_typeenum ;
pulse_typenum: The valid values are:
rise_triggered_high_pulse,
rise_triggered_low_pulse,
fall_triggered_high_pulse,
fall_triggered_low_pulse.

Pulse type defines the relationship of the pulse with source clock.

Pulse generator

Pulse types rise_triggered_high_pulse and rise_triggered_low_pulse

rise_triggered_high_pulse or rise_triggered_low_pulse pulse generators expect the

following two timing arcs in timing model:

combinational_rise arc with positive unate (Rise-> Rise)

combinational_fall arc with negative unate (Rise->Fall)

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 Pulsed Latch Timing Analysis

However, for rise_triggered_high_pulse, rise->fall arc, delays should be larger than the
rise>rise delays. For the rise_triggered_low_pulse, rise->rise arc delays should be
larger than rise->fall delays.

Here is an example of rise_triggered_high_pulse or rise_triggered_low_pulse pulse

generators:

pin (clk) {
direction : output;
pulse_clock : rise_triggered_high_pulse;

timing () {
related_pin : clk_in; timing_type :
combinational_rise;
timing_sense : positive_unate;
rise_transition(delay_template_7x8){
…….
…….

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 Pulsed Latch Timing Analysis

}
cell_rise (delay_template_7x8) {
……
……
}
}
timing ( ) {
related_pin: clk_in;
timing_type : combinational_fall;
timing_sense : negative_unate;
fall_transition (delay_template_7x8) {
…….
…….
}
cell_fall (delay_template_7x8) {
……
……
}
}

Pulse types fall_triggered_high_pulse and fall_triggered_low_pulse

The fall_triggered_high_pulse or fall_triggered_low_pulse pulse generators expect the

following two timing arcs in timing model:

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 Pulsed Latch Timing Analysis

combinational_rise arc with negative unate (Fall-> Rise)

combinational_fall arc with positive unate (Fall->Fall)

However, for fall_triggered_high_pulse, fall->fall arc, delays should be larger than the
fall>rise delays. For fall_triggered_low_pulse pulse, the fall->rise arc delays should be
larger than the fall->fall delays.

Here is an example of the fall_triggered_high_pulse or fall_triggered_low_pulse pulse

generators:
pin (clk) {
direction : output;
pulse_clock : fall_triggered_high_pulse;
timing () {
related_pin : clk_in;
timing_type : combinational_rise;
timing_sense :negative_unate;
rise_transition (delay_template_7x8) {
…….
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 Pulsed Latch Timing Analysis

…….
}
cell_rise (delay_template_7x8) {
……
……
}
}
timing () {
related_pin : clk_in;
timing_type : combinational_fall;
timing_sense : positive_unate;
fall_transition (delay_template_7x8) {
…….
…….
}
cell_fall (delay_template_7x8) {
……
……
}
}
timing () {
related_pin : clk_in;
timing_type : combinational_fall;
timing_sense : positive_unate;
fall_transition (delay_template_7x8) {
…….
…….
}
cell_fall (delay_template_7x8) {
……
……
}
}

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 Pulsed Latch Timing Analysis

Timing Analysis for Pulsed Latch Design

CTS swaps the desired flip-flops with latch models and inserts pulse generators to
clock those latches. The timing engine recognizes the latches with pulse reaching their
enable pin as pulsed latches, and analyzes the timing paths accordingly.

Timing Analysis with original Netlist (with flip-flops)

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 Pulsed Latch Timing Analysis

Timing analysis after pulse-generator insertion and flip-flop swapped with

latches

The main difference in timing analysis between pulsed latches and regular latches lies
in how the time borrow checks are performed. For pulsed latches, the time borrow
checks are done at one clock later than regular latches.

By replacing flops with pulsed latches, you can reduce power consumption and take
advantage of time borrowing to improve timing. However, if you do not want to take the
advantage of time borrowing and want to check that data arrives before the opening
edge of the pulse, you can perform setup checks in the following manner:

Setup checks are performed at close edge to make sure that the data is stable before
latch closing.

Launch clock

Capture clock Traditional setup checks at

latch closing edge

Traditional setup checks modeled in latches at closing edge

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 Pulsed Latch Timing Analysis

Launch clock

Setup time in library

Capture clock

Pulse derived from

Capture clock

Desired setup time Pulse

(tsetup) width(tpulse_width)

Set_annotated_check –from pulsedlatch/enable –to pulsed-latch/data –setup (tpulse_width

+ tsetup)

Setup time modeled in the library can be overridden with

set_annotated_check constraint. By increasing the setup time by more than
the pulse width, data arrival can be ensured before the latch opening edge.

Note: Pulsed latch analysis is not enabled by default. Set the following variable to
enable pulsed latch analysis, more pulse-clock specific constraint specifications and
reporting capabilities will also be provided:
Set_global timing_enable_pulsed_latch true

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 Pulsed Latch Timing Analysis

Constraints

Constraints: Pulse Clock

set_pulse_clock_{min|max}_transition value <cell,LibCell,Clk,Des>
[-transitive_fanout}
set_pulse_clock_{min|max}_width value <cell,LibCell,clock,design>
[-transitive_fanout]

Description: These four new commands allow you to configure specific DRV
rules for your pulse clock networks. By default, the DRVs apply to the
specified pulse-clock generator start point. Use the –transitive_fanout option
to apply constraints to all the clock network elements between the generator
and the pulse-latch clock inputs.

Use model: Use constrains in the SDC file or as a command-line constraint

Use the report_constraint to report pulse clock DRV
checks

0 5 10
CLK
1 2 4 5
Pulse-clock

minPW=3

maxPW=4

Example: Pulse Clock Constraints

create_clock -name PH1 -waveform {0 5} -period 10 clk

set_propagated_clock PH1
set_pulse_clock_min_width 3.000 [get_cells PG]
set_pulse_clock_max_width 4.000 [get_cells PG]
set_annotated_delay -cell -rise -min 1.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -rise -max 2.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -fall -min 4.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -fall -max 5.000 -from PG/CLK -to PG/PCL

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 Pulsed Latch Timing Analysis

…
report_constraint -check_type pulse_clock_min_width -verbose -all_violators
report_constraint -check_type pulse_clock_max_width -verbose -all_violators

Example: Pulse Generator Liberty Specification

cell (PULSEGEN) {
pin(CLK) {
direction : input;
}

pin(PCLK) {
pulse_clock : rise_triggered_high_pulse;
direction : output;
timing( ) {
related_pin : "CLK";
timing_type : combinational_rise;
timing_sense : positive_unate;
cell_rise(delay_template_2x2) { … }
rise_transition(delay_template_2x2) { …}
}

timing() {
related_pin : "CLK";
timing_type : combinational_fall;
timing_sense : negative_unate;
cell_fall(delay_template_2x2) { … }

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 Pulsed Latch Timing Analysis

Constraints: set_clock_sense –pulse

set_clock_sense
-pulse {rise_triggered_high_pulse|rise_triggered_low_pulse|
fall_triggered_high_pulse|fall_triggered_low_pulse}

Description: set_clock_sense –pulse option provides an alternate method

of selecting the edge-to-edge relationship of a non-unate timing arc used to
construct the output clock.

This option is also used to declare the clock to be a pulse-clock generator

when both the output edges are derived from the same source edge.

Use model: set_clock_sense constraint (in general) is not allowed on hierarchical

ports.

Derivation of Derivation of Pulse type

output rising edge output falling (which output edge
set_clock_sense edge happens first)
option

-positive rise -> rise fall -> fall NA

-negative fall -> rise rise -> fall NA

-pulse rise_triggered_high_pulse rise -> rise rise -> fall high

-pulse rise_triggered_low_pulse rise -> rise rise ->fall low

-pulse_fall_triggered_high_pulse fall -> rise fall -> fall high

-pulse_fall_triggered_low_pulse fall -> rise fall -> fall low

Note: Pulse-clock generation via set_clock_sense is still in the development

stage.

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 Pulsed Latch Timing Analysis

Example: Pulse Clock Filtering

set_clock_sense -pulse fall_triggered_high_pulse [get_pins C3/Y]

set_clock_sense -pulse rise_triggered_high_pulse [get_pins C3/Y]

0 5 10
CLK
1 2 4 5

6 7 8 9
Pulse-clock (FTH)

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 Pulsed Latch Timing Analysis

+------------------------------------------------------+
| Timing | Cell | Delay | Arrival | Edge |
| Point | | | Time | |
|-------------+--------------+-------+---------+-------|
| clk | | | 5.000 | v |
| clk | (net) | | | |
| PG_FTH/CLK | PULSEGEN_FTH | 0.000 | 5.000 | v |
| PG_FTH/PCLK | PULSEGEN_FTH | 1.000 | 6.000 | ^ |
| fth_clk | (net) | | | |
| C2/A | BUFX1 | 0.000 | 6.000 | ^ |
| C2/Y | BUFX1 | 1.000 | 7.000 | ^ |
| fth_clk_1 | (net) | | | |
| C3/B | MX2X1 | 0.000 | 7.000 | ^ |
| C3/Y | MX2X1 | 1.000 | 8.000 | ^ |
| mux_clk | (net) | | | |
| C4/A | BUFX1 | 0.000 | 8.000 | ^ |
| C4/Y | BUFX1 | 1.000 | 9.000 | ^ |
| mux_clk_1 | (net) | | | |
| L1/G | TLATRX1 | 0.000 | 9.000 | ^ |
+------------------------------------------------------+

Timing report of “set_clock_sense -pulse fall_triggered_high_pulse [get_pins C3/Y]”

+---------------------------------------------------+
| Timing | Cell | Delay | Arrival | Edge |
| Point | | | Time | |
|-------------+----------+--------+---------+-------|
| clk | | | 0.000 | ^ |
| clk | (net) | | | |
| PG_RTH/CLK | PULSEGEN | 0.000 | 0.000 | ^ |
| PG_RTH/PCLK | PULSEGEN | 1.000 | 1.000 | ^ |
| rth_clk | (net) | | | |
| C1/A | BUFX1 | -0.000 | 1.000 | ^ |
| C1/Y | BUFX1 | 1.000 | 2.000 | ^ |
| rth_clk_1 | (net) | | | |
| C3/A | MX2X1 | 0.000 | 2.000 | ^ |
| C3/Y | MX2X1 | 1.000 | 3.000 | ^ |
| mux_clk | (net) | | | |
| C4/A | BUFX1 | 0.000 | 3.000 | ^ |
| C4/Y | BUFX1 | 1.000 | 4.000 | ^ |
| mux_clk_1 | (net) | | | |
| L1/G | TLATRX1 | 0.000 | 4.000 | ^ |
+---------------------------------------------------+

Timing report of “set_clock_sense -pulse rise_triggered_high_pulse [get_pins C3/Y]”

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 Pulsed Latch Timing Analysis

Reports: report_constraint for Pulse Clocks

report_constraint

-check_type
{pulse_width|clock_period|recovery|removal|clock_gating_setup|clock_gating_ho
ld|skew|pulse_clock_max_width|pulse_clock_min_width}

-drv_violation_type
{max_capacitance|max_transition|max_fanout|min_capacitance|min_transition|mi
n_fanout|pulse_clock_max_transition|pulse_clock_min_transition}

Description: Provides specific analysis for pulse clock constraints set by

set_pulse_clock_{min|max}_{width|transition} commands
Default: Is not enabled by default

Use model: Report max transition constraints in Setup analysis mode, and min
transition constraints in Hold analysis mode

Note: Timing global timing_enable_pulsed_latch must be set to true to enable pulse-

clock analysis.

PG PL
C1 C2 C3

CLK PCLK A Y A Y A Y PG
CLK

Pulse generator Pulse latch

Design schematic

0 5 10
CLK
1 2 4 5
Pulse-clock

minPW=3

maxPW=4

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 Pulsed Latch Timing Analysis

Constraints:

create_clock -name PH1 -waveform {0 5} -period 10 clk

set_propagated_clock PH1
set_pulse_clock_min_width 3.000 [get_cells PG]
set_pulse_clock_max_width 4.000 [get_cells PG]
set_annotated_delay -cell -rise -min 1.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -rise -max 2.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -fall -min 4.000 -from PG/CLK -to PG/PCLK
set_annotated_delay -cell -fall -max 5.000 -from PG/CLK -to PG/PCL
…
report_constraint -check_type pulse_clock_min_width -verbose
-all_violators
report_constraint -check_type pulse_clock_max_width -verbose
-all_violators

Min Pulse Clock Width Check

CLOCK TREE PULSE WIDTH
----------------------
Ending Clock Edge: PG/PCLK (v) checked with trailing edge of ' PH1'
Beginning Clock Edge: PG/PCLK (^) triggered by trailing edge of ' PH1'
Other End Arrival Time 4.000
- PulseWidth 3.000
+ Phase Shift 0.000
= Required Time 1.000
- Arrival Time 2.000
= Slack Time -1.000
Clock Rise Edge 0.000
+ Clock Network Latency (Ideal) 0.000
= Beginpoint Arrival Time 0.000
-----------------------------------------
Pin Cell Delay Arrival Edge
Time
-----------------------------------------
PG/PCLK PULSEGEN 2.000 2.000 ^
-----------------------------------------

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 Pulsed Latch Timing Analysis

Max Pulse Clock Width Check

CLOCK TREE PULSE WIDTH
----------------------
Endpoint: pg1/lclk (^) checked with trailing edge of ' PH1'
Beginpoint: pg1/lclk (^) triggered by trailing edge of 'PH1'
Other End Arrival Time 5.000
- PulseWidth 4.000
+ Phase Shift 0.000
= Required Time 1.000
Arrival Time 1.000
Slack Time -0.000
Clock Rise Edge 0.000
+ Clock Network Latency (Ideal) 0.000
= Beginpoint Arrival Time 0.000
-----------------------------------------
Pin Cell Delay Arrival Edge
Time
-----------------------------------------
C1/A BUFX1 1.000 1.000 ^
-----------------------------------------

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 Pulsed Latch Timing Analysis

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Feedback
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